Associate Professor Mahyar Shirvanimoghaddam is a distinguished academic at The University of Sydney's School of Electrical & Computer Engineering, specializing in IoT, Telecommunications, and Coding Theory. His research focuses on 6G communication strategies, ultra-reliable low-latency systems, and machine learning integration in wireless networks. He holds a PhD from The University of Sydney and has received multiple accolades, including the World Economic Forum's Young Scientist award (2018) and the Australian Award for University Teaching (2020). Education: B.Sc. (1st Class Honors) in Electrical Engineering, University of Tehran (2008) M.Sc. (1st Class Honors) in Electrical Engineering, Sharif University of Technology (2010) PhD in Electrical Engineering (Telecommunications), The University of Sydney (2015) Research Interests: IoT Communication Protocols, Rateless Coding, Non-Orthogonal Multiple Access (NOMA), 5G/6G Technologies, and Federated Learning in Wireless Networks. His work on channel coding for massive IoT and URLLC has been funded by ARC Discovery Projects and European Research Council grants. He pioneered the 'Idea Factory' interdisciplinary teaching project, blending engineering and business education. Key projects include designing 6G communication strategies (ARC 2022-2024) and robust coding for mission-critical communications (ARC 2019-2021). Awards: Over 20 awards, including teaching excellence (Vice-Chancellor's Awards 2019, 2022), research recognition (IEEE Best Paper Awards), and leadership roles in IEEE and the Higher Education Academy. He supervises 1 PhD student (Tyseer BASHIR) and actively engages in editorial roles for IEEE Transactions and other journals. His team's innovations aim to bridge technological and societal challenges in IoT and smart infrastructure.









