Gene Cooperman is a Professor at the Khoury College of Computer Sciences at Northeastern University, with an affiliation in the College of Engineering. His research focuses on high-performance computing (HPC), transparent checkpoint-restart systems, and model checking. He leads the High Performance Computing Laboratory, where he explores checkpointing technologies like DMTCP, MANA for MPI, and CRAC for CUDA, aiming to enhance HPC workflows on supercomputers such as NERSC's Perlmutter. His work bridges distributed computing, parallel algorithms, and system software to address challenges in fault tolerance, scalability, and resource management. Cooperman has advised 10 PhD students and co-authored over 125 refereed publications, contributing to projects like Geant4-MultiThreaded and Roomy for disk-based computation. His teaching includes courses on computer systems and HPC seminars. Education: Background in computational algebra and parallel computing, transitioning to HPC systems and checkpointing. Research Themes: Transparent checkpointing, MPI agnostic solutions, CUDA integration, and HPC resource optimization. Recent articles emphasize MPI checkpointing, reversible debugging (FReD), and CUDA support, reflecting trends in distributed and GPU-accelerated systems. His grants include NSF, NERSC/DOE, and MemVerge funding. Cooperman collaborates with institutions like CERN and NERSC, advancing applications in particle physics simulations and supercomputing. Current students include Aayushi Gautam, Jiajun Cao, Rohan Garg, and Twinkle Jain.
Joseph Devietti is an Associate Professor in the Department of Computer & Information Science at the University of Pennsylvania. His research focuses on improving programmability and performance of multiprocessor systems through architectural and programming model innovations. He actively advises PhD students and has supervised numerous graduates now employed at leading tech companies and academic institutions. Education: PhD (2012), MS (2009) in Computer Science and Engineering from University of Washington; BSE (2006) in Computer Science and BA (2006) in English from University of Pennsylvania. Employment: Associate Professor (2020–present), Assistant Professor (2013–2020) at University of Pennsylvania; Principal Scientist & Co-founder at Cloudseal, Inc. (2018–2020). Devietti’s research spans computer architecture, parallel programming, and deterministic execution. Key areas include cache/memory optimization (prefetching, false sharing repair), GPU programming models (race detection, block-size independence), and hardware-software co-design for concurrency safety. His recent work addresses dynamic runtime prefetch tuning (RPG 2 ), online code layout optimization (OCOLOS), and intelligent BTB prefetching (Twig) for data center applications. His publications from 2024–2017 reveal trends in instruction/cache optimization (2024–2020), GPU determinism (2018–2017), and race detection (2018–2016). Awards include the 2024 Penn Engineering Ford Motor Company Award, Radhia Cousot Best Paper (2018), and IEEE Micro Top Picks recognition (2023, 2009, 2008). Scientific Awards : 2024 Penn Engineering Ford Motor Company Award Radhia Cousot Young Researcher Best Paper Award (SAS 2018) IEEE Micro Top Picks (2023, 2009, 2008) Intel Early Career Faculty Honor Program (2013) Intel Ph.D. Fellowship (2011) Advising : Supervised 15+ PhD/Master’s students with placements at Google, Microsoft, Amazon, NYU, and the United States Naval Academy. Collaborations : Works with industry leaders (NVIDIA, Facebook) and academic institutions (University of Washington, Penn).
Ahmed Saeed is an Assistant Professor in the School of Computer Science at Georgia Institute of Technology, specializing in scalable computer networks and systems. His research spans congestion control, operating systems, LEO satellite networks, and formal methods, with a strong record of publications and active mentorship. Education: PhD in Computer Science, Georgia Institute of Technology (2019) Bachelor's in Computer and Systems Engineering, Alexandria University (2010) Postdoctoral Associate, MIT (with Prof. Mohammad Alizadeh) Research Interests: Ahmed's work focuses on the theory, design, and implementation of scalable networked systems. Key themes include: Congestion control algorithms for datacenter and WAN traffic Overload control mechanisms for microsecond-scale RPCs Performance debugging tools for datacenter applications LEO satellite network modeling and policy analysis Formal verification of network protocols and resource schedulers Recent Publications Trend: His 2024-2025 papers emphasize LEO satellite resilience and datacenter performance , with contributions to emergency failover modeling, latency debugging tools, and congestion control protocols. These works combine empirical measurement, formal modeling, and policy recommendations. Awards & Funding: NSF CAREER Award (2024) – LEO satellite variability ($600k) NSF CNS Core Awards (2022) – Edge server stacks & formal verification (total $2.38M) Google Research Award (2022) – Scalable edge systems ($80k) DARPA Risers Top 5 Poster (2022) Spec Tech Award (2023) – Nanomodular electronics routing ($40k) Teaching & Service: He regularly teaches Computer Networking I (CS 3251) and Datacenter Networks & Systems (CS 8803) . Service includes PC roles for SIGCOMM, NSDI, CoNEXT, and Networking area co-chair for JSys. Lab & Students: Ahmed leads an active research group with PhD students Peidi Song, Bhaskar Pardeshi, Sherif Abdelrazek; MS students Dhyey Thummar, Pratyush Sahu, Sammy Kapoor; and undergraduate Demi Lei. Alumni have joined industry leaders like Juniper, Microsoft, and Snowflake.
Carlos Molina Clemente is an Associate Professor of Computer Architecture at Rovira i Virgili University in Tarragona, Spain. He holds a M.Sc. in Computer Engineering (Universitat Politècnica de Catalunya, 1996) and a Ph.D. in Computer Science (UPC, 2005). His research focuses on Computer Architecture, Mobile/Sensor Networks, and Cloud Computing. He leads the Cloudlab research group and coordinates initiatives like GTDAWIN and BIOGEI. Key research areas include multicore scheduling, LoRaWAN protocols, LIDAR data analysis, and serverless computing. He has published over 50 articles in top-tier conferences/journals and supervised three doctoral theses. His work spans projects on cache architectures, real-time systems, and educational multicomputing solutions. Affiliations include the Department of Computer Engineering and Mathematics (DEIM) at URV, with offices at Campus Sescelades (Avinguda Països Catalans 26, Tarragona). Research highlights include contributions to non-uniform cache policies, predictive mobile network algorithms, and energy-efficient sensor networks.
Shubhendu Mukherjee is a Distinguished Engineer at Cavium Networks and Adjunct Professor at the Indian Institute of Technology Kanpur. He is a Fellow of IEEE and ACM, and recipient of the 2009 Maurice-Wilkes Award for outstanding contributions to computer architecture. His career spans leadership roles at Intel and Compaq, where he pioneered fault-tolerant microarchitectures and performance modeling innovations. Education: PhD (1998) and MS (1993) in Computer Science from University of Wisconsin-Madison; B.Tech (1991) in Computer Science and Engineering from IIT Kanpur. Research Interests Mukherjee specializes in computer architecture , soft error modeling , and fault-tolerant design . His work includes Redundant Multithreading (RMT), architectural vulnerability modeling, and on-chip interconnect optimization. Recent publications focus on cache soft error anomalies, quantized AVF analysis, and architectural core salvaging for hard error tolerance. Scientific Awards Maurice-Wilkes Award (2009) IEEE Fellow (2009) ACM Fellow (2011) IEEE Top Picks Awards (2003, 2004) Intel Divisional Recognition Awards (2002–2009) Professional Activities Mukherjee served as General Chair of ASPLOS 2004 , Program Chair of HPCA 2011 , and editorial board member for IEEE Micro, IEEE Computer Architecture Letters, and IEEE Transactions on Dependable and Secure Computing. He also led Intel's SPEARS group (2001–2010), driving architectural innovations in enterprise processors.
Michael Huang is a Professor in the Department of Electrical and Computer Engineering and Computer Science at the University of Rochester's Hajim School of Engineering & Applied Sciences. He holds a PhD from the University of Illinois at Urbana-Champaign (2002) and has been faculty since 2002. His research focuses on high-performance computing, including processor microarchitecture, energy-efficient design, and non-von Neumann systems like Ising machines. He has received the NSF CAREER Award and is a member of ISCA/HPCA Hall of Fame. Education: BS (Tsinghua University, 1994), MS/PhD (UIUC, 1999/2002). Research emphasizes co-design of device, circuit, and system technologies. Notable projects include multi-chip Ising machine architectures and optical interconnects. Collaborates with IBM Research on future processor concepts. Active in top conferences like ISCA, HPCA, and ICLR. Key achievements include pioneering work on Ising machines for combinatorial optimization, energy-efficient architectures, and secure branch predictors. His work bridges traditional computer architecture with emerging technologies like optics and mixed-signal circuits.
Cormac Flanagan is a Professor in the Department of Computer Science and Engineering at the Baskin School of Engineering, University of California Santa Cruz. His research focuses on programming languages, security, and software verification, with particular expertise in concurrent programming, information flow control, and program analysis. Flanagan's research interests span multiple areas of programming languages and software security. He has made significant contributions to the fields of information flow control, concurrent programming verification, and dynamic analysis techniques. His work on dynamic race detection, particularly the FastTrack algorithm, has been highly influential in the field, earning him a PLDI Most Influential Paper Award. He has also pioneered techniques for secure information flow, including the development of faceted values and secure multi-execution approaches, which earned him a POPL Most Influential Paper Award. His recent publications demonstrate a continued focus on program verification, with particular attention to concurrent software, JavaScript verification, and serverless computing security. Flanagan's work often bridges theoretical foundations with practical implementations, resulting in tools like the Anchor Verifier for concurrent software that provide practical verification solutions for real-world programming challenges. Fellow of the Association for Computing Machinery Alfred P. Sloan Foundation Fellow POPL Most Influential Paper Award for 'Multiple Facets for Dynamic Information Flow' PLDI Most Influential Paper Award for 'FastTrack: Efficient and Precise Dynamic Race Detection' PLDI Most Influential Paper Award for 'Extended Static Checking for Java' ECOOP 2024 Distinguished Paper Award for 'Mover Logic: A Concurrent Program Logic for Reduction and Rely-Guarantee Reasoning' CSF Distinguished Paper Award for 'Transparent IFC Enforcement: Possibility and (In)Efficiency Results' PLDI Distinguished Artifact Award for 'BigFoot: Static Check Placement for Dynamic Race Detection' ECOOP Best Paper Award for 'RedCard: Redundant Check Elimination for Dynamic Race Detectors' ISSTA Distinguished Paper Award for 'Exploiting Purity for Atomicity' UCSC Excellence in Teaching Award Professor Flanagan has advised numerous PhD students who have gone on to successful careers in industry and academia, including positions at Google, Shape Security, and San Jose State University. He serves as Steering Committee Chair for the ACM Conference on Programming Language Design and Implementation (PLDI) and as Associate Editor for ACM Transactions on Programming Languages and Systems (TOPLAS). His research has been supported by various grants from funding agencies, though specific details are not provided in the available information. Flanagan leads research projects including the Anchor Verifier for Concurrent Software, data race detection tools, the RoadRunner dynamic analysis infrastructure, and work on cooperable concurrency. His research group at UC Santa Cruz focuses on developing practical techniques for ensuring software reliability and security, with applications to concurrent programming, web security, and cloud computing environments.
Sebastian Altmeyer is a Professor holding the Chair for Embedded Systems at the Institute of Computer Science within the Faculty of Applied Computer Science at the University of Augsburg. He has been in this position since August 2019, following his role as Assistant Professor at the University of Amsterdam from September 2017 to July 2019. Professor Altmeyer's research focuses on real-time systems and embedded computing, with particular expertise in multi-core architectures, cache analysis, scheduling algorithms, and response time analysis. His work bridges theoretical computer science with practical applications in safety-critical systems. He leads research projects including ADMORPH EU H2020, Multi-Core Response Time Analysis (MRTA), Design of Hardware Transactional Memory for Embedded Systems, and several others focused on manycore architectures and embedded system design. His extensive publication record demonstrates consistent contributions to the field of real-time systems, with recent work focusing on systematic evaluation techniques for real-time systems, multicore interference analysis, safety-critical edge robotics, and hardware transactional memory. His research shows a clear trajectory toward addressing the challenges of modern embedded systems with increasingly complex hardware architectures while maintaining real-time guarantees. Professor Altmeyer leads the Chair for Embedded Systems team at the University of Augsburg, which includes Prof. Dr. Theo Ungerer, Petra Zettl, Dr.-Ing. Martin Frieb, and several other researchers. The team conducts research in areas including hardware transactional memory, manycore architectures, and real-time system analysis. Their work has practical applications in safety-critical systems where timing guarantees are essential.
Eric Roman is a Computer Systems Engineer and Manager at the National Energy Research Scientific Computing Center (NERSC), part of Lawrence Berkeley National Laboratory. He has been with Berkeley Lab since 1999 and currently works in the HPC Technology Department within the Computing Sciences division. Dr. Roman earned his PhD in physics from the University of California, Berkeley in 2010, with a dissertation entitled "Orientation Dependence of the Anomalous Hall Effect in 3D Ferromagnets." His doctoral research involved ab initio simulations of nonlinear optical properties of semiconductors, spin transport in metals, and the anomalous Hall effect. Roman's primary research focus is on operating systems for high performance computing, with significant contributions to Berkeley Lab's Checkpoint/Restart (BLCR) technology since 2001. His work spans several key areas: Development of multithreaded checkpoints and restarts Implementation of file and pipe support in BLCR On-the-fly compression of checkpoint files Direct I/O capabilities for HPC systems Integration with batch systems like Torque Optimization of file I/O operations His publication record shows consistent contributions to HPC systems research over 15+ years, with recent work focusing on resilience techniques, failure prediction, and system optimization. Roman has collaborated with researchers from multiple institutions, advancing parallel computing, fault tolerance, and system-level technologies that enable scientific discovery at scale. His highly cited works on live migration and checkpoint/restart frameworks demonstrate significant impact in the field. Roman has been actively involved in the HPC community, leading Linux kernel seminars and organizing projects like "High-End Computing with K42" under the FastOS initiative. He continues to collaborate with the Berkeley ParLab on cutting-edge research in high-performance computing systems.
Paulo Garcia is an Assistant Professor in the Department of Systems and Computer Engineering at Carleton University, Ottawa, Canada. He holds a Ph.D. in Computer Engineering from the University of Minho, Portugal, with research periods at Asian Institute of Technology and University of Würzburg. His academic roles include serving as a faculty member, thesis chair/examiner, and committee member in multiple university initiatives. Research Focus: Embedded real-time systems, hardware/software co-design, FPGA acceleration, and engineering pedagogy. Specific technical areas include multicore architectures, runtime systems, and hardware accelerators for embedded applications. His work emphasizes synergies between processor architectures, compilers, and FPGA-based solutions. Teaching: Courses include SYSC 3310 (Real-Time Systems), SYSC 4310 (Computer Architecture), and SYSC 5807 (Hardware/Software Co-Design). He supervises senior projects like robotic systems and eHealth wearable devices. Awards & Grants: Includes 2020 awards from General Dynamics Mission Systems and Carleton’s Rapid Response Grant, plus multiple scholarships from FCT Portugal and EU programs. His research has been supported by industry partnerships and defense collaborations. Service: Active in academic service as a thesis evaluator, member of student mental health committees, and representative in university governance bodies. Engaged in curriculum development and embedded systems program revisions.
