Priyanka Raina is an Assistant Professor of Electrical Engineering at Stanford University, with a courtesy appointment in Computer Science. She leads the Stanford Accelerate research group, focusing on domain-specific hardware architectures and agile hardware-software co-design. Her work emphasizes high-performance, energy-efficient accelerators for emerging technologies. Education: B.Tech. from IIT Delhi (2011), M.S. and Ph.D. from MIT (2013/2018). Postdoctoral experience includes NVIDIA Research (2018) and Amazon Visiting Academic (2023–present). Awards include the Sloan Research Fellowship (2024), NSF CAREER Award (2023), and Terman Faculty Fellowship (2018). Research Interests: Domain-specific architectures, near-memory computing, design productivity, and machine learning acceleration. Her group develops frameworks like AHA (Agile Hardware) for efficient accelerator design and compilers. Awards: Over 10 major awards, including best paper recognitions at VLSI, MICRO, and JSSC. Active roles as Associate Editor for IEEE JSSC and Program Chair for IEEE Hot Chips (2020). Advising & Teaching: Supervises multiple PhD and MS students in hardware design, CGRAs, and ML accelerators. Teaches VLSI design courses (EE271/272/372) and oversees independent studies in embedded systems and chip design. Labs & Collaborations: Affiliated with Stanford PORTAL Center, AHA Center, and SystemX Alliance. Projects include MINOTAUR (edge AI accelerator), Amber (CGRA-based SoC), and EMBER (RRAM macros).
Subhasish Mitra is the William E. Ayer Professor of Electrical Engineering and Computer Science at Stanford University, holding dual appointments in both departments. He leads the Stanford Robust Systems Group and serves on the leadership team of the Microelectronics Commons AI Hardware Hub under the US CHIPS and Science Act. His research spans Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences, with breakthroughs in X-Compact test compression, carbon nanotube computing, and 3D integration. He has held international roles like the Carnot Chair at CEA-LETI and Visiting Professorships globally. Education & Honors: Recipient of over 40 awards including the IEEE Computer Society’s Harry H. Goode Memorial Award, ACM/IEEE’s A. Richard Newton Technical Impact Award, and the Intel Achievement Award. He earned top academic accolades from IIT Kharagpur and Jadavpur University, and is a Fellow of ACM and IEEE. Research Impact: Pioneered first-of-their-kind systems like the carbon nanotube computer and monolithic 3D integration. His work on robust computing techniques like QED validation and X-Compact compression has industry-wide adoption, saving billions in manufacturing costs. Collaborates with industry leaders like Intel, Google, and Samsung. Publications & Grants: Over 400 publications, including award-winning papers in DAC, ISSCC, and IEEE journals. Leads grants from NSF, DoE, and industry partnerships. His lab explores cutting-edge topics like neuromorphic computing, 3D thermal scaffolding, and AI hardware acceleration. Administration & Outreach: Serves as Associate Chair (Faculty Affairs) for Stanford’s Computer Science Department. Recognized by students for mentorship, and frequently invited to global forums like the World Economic Forum and National Academy of Engineering.
Haitong Li is an Assistant Professor in the School of Electrical and Computer Engineering at Purdue University's College of Engineering, joining the faculty in 2022. His research bridges nanoelectronic devices, integrated circuits, and nanotechnology-inspired AI hardware to address critical challenges in energy-efficient artificial intelligence systems. Education: Ph.D. in Electrical Engineering, Stanford University Research Interests: Dr. Li pioneers emerging memory technologies—particularly Resistive RAM (RRAM)—for in-memory computing and neuromorphic systems. His work focuses on 3D monolithic integration of RRAM and gain cell memory with CMOS to enable edge AI, with recent breakthroughs in hardware acceleration for large language models and sustainable computing. Key innovations include carbon footprint prediction for LLMs and zeroth-order fine-tuning techniques. Publication Trends: Dr. Li's 2023-2025 publications reveal a strategic shift toward sustainable AI hardware, emphasizing carbon-aware LLM inference and edge deployment. His research consistently targets data movement reduction through memory-centric architectures, spanning photonic accelerators, neuro-symbolic computing, and heterogeneous 3D integration. Awards: No scientific awards were documented in the provided sources. Advising and Grants: Current advisees and grant funding details were not specified in the available materials. Labs and Teams: Research group composition and laboratory facilities were not described in the source text.
Gert Cauwenberghs is a Professor of Bioengineering at the University of California San Diego (UCSD), affiliated with the Jacobs School of Engineering. He co-directs the Institute for Neural Computation and holds a visiting professorship at MIT. His research focuses on neuromorphic engineering, energy-efficient neural interfaces, and wearable biosensors. Key contributions include silicon-based adaptive neural circuits, implantable neural recording systems, and in-ear biosensing devices. Education: M.Eng. in Applied Physics (University of Brussels, 1988), M.S. and Ph.D. in Electrical Engineering (Caltech, 1989–1994). Prior roles include Professorships at Johns Hopkins University and Visiting Professor at MIT. Research Interests: Biomedical integrated circuits, neuromorphic computing, brain-machine interfaces, and energy-efficient neural systems. His work bridges neuroengineering and clinical applications, emphasizing adaptive intelligence and low-power designs. Recent Work: Development of femtojoule-efficient neural chips, high-density neural interfaces, and closed-loop wearable systems. Projects include neurobench benchmarking frameworks and RRAM-based neuromorphic hardware. Awards: NSF Career Award (1997), ONR Young Investigator (1999), PECASE (2000), IEEE Distinguished Lecturer (2003–2004). Grants & Labs: Active in NIH and DoD-funded projects, co-directs the UCSD Institute for Neural Computation. Collaborates with industry on neural interface technologies. Labs/Teams: Cauwenberghs Lab at UCSD focuses on integrated neuroengineering systems, including neural recording systems and neuromorphic computing architectures.
Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology and serves as the Director of the 3D Systems Packaging Research Center. His research focuses on heterogeneous integration of microsystems, including 2.5D and 3D ICs and packaging technologies, with significant contributions to advanced cooling systems, electrical and photonic interconnects, and biosensor integration with CMOS. Dr. Bakir's research interests span heterogeneous microsystem design and integration, advanced cooling and power delivery for emerging architectures, electrical and photonic interconnect technologies, biosensor technologies, and nanofabrication. His work addresses critical challenges in next-generation electronics, enabling polylithic integration that concatenates heterogeneous ICs of various functionalities while mimicking monolithic-like densities. His research particularly focuses on co-design of thermal technologies, power delivery networks, and signaling networks for silicon nanoelectronic systems. His recent publications demonstrate strong trends in fused-silica stitch-chip technology for heterogeneous integration, with particular emphasis on RF and mm-wave applications, power delivery for AI accelerators, and thermal management solutions. His work bridges electrical engineering, materials science, and thermal management to solve critical bottlenecks in computing performance and efficiency. 2013 Intel Early Career Faculty Honor Award 2012 DARPA Young Faculty Award 2011 IEEE CPMT Society Outstanding Young Engineer Award 2012 National Academy of Engineering Frontiers of Engineering Symposium Invited Participant 2015 IEEE CPMT Society Distinguished Lecturer 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology More than 25 conference and student paper awards Twelve issued US Patents Dr. Bakir leads the Integrated 3D Systems Lab (I3DS) at Georgia Tech, which is actively researching advanced packaging, interconnects, electrical and thermal design, and system integration. His team has received significant recognition for their work, including multiple best paper awards from major conferences like ECTC, IITC, and CICC. The lab is currently seeking postdoctoral researchers and research faculty to advance next-generation electronics through collaborative research. His lab focuses on enabling the next phase of Moore's Law through polylithic integration, which concatenates heterogeneous ICs of various functionalities (digital, analog, photonic, and mm-wave) using advanced off-chip '2.5D' and '3D' heterogeneous interconnects and packaging. This work impacts applications in high-performance computing, machine learning, edge intelligence, autonomous vehicles, augmented/virtual reality, and healthcare.
Naresh R. Shanbhag is the Jack Kilby Professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. He serves as Director of the Systems on Nanoscale Information fabriCs (SONIC) Center and held the D.J. Gandhi Distinguished Visiting Professorship at IIT Mumbai from 2015-2020. Previously, he was a visiting faculty member at National Taiwan University (2007) and Stanford University (2014). Dr. Shanbhag received his doctorate from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories as the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. His research focuses on the design of energy-efficient machine learning, communications, and signal processing systems on resource-constrained embedded platforms. He explores fundamental trade-offs between energy efficiency, latency and accuracy of decision-making systems implemented in nanoscale technologies, with applications to computer vision, biomedicine, automatic target recognition, and imaging. His work spans four primary focus areas: Resource-efficient Machine Learning for the Edge, In-memory Computing (IMC), Energy-efficient High Data Rate Communications, and Shannon-inspired Statistical Error Compensation (SEC). Analysis of his recent publications reveals a strong emphasis on in-memory computing architectures (SRAM, MRAM, RRAM) for machine learning acceleration. His work consistently addresses energy-accuracy trade-offs, with increasing attention to security aspects of hardware implementations and applications to MIMO signal processing and edge AI systems. His research demonstrates a progression from theoretical foundations to practical silicon implementations. 2024 Semiconductor Research Corporation Innovation Award 2018 Semiconductor Industry Association/Semiconductor Research Corporation University Researcher Award 2018 IEEE International Symposium on Circuits and Systems Best Paper Award 2006 IEEE Fellow 1996 National Science Foundation CAREER Award Professor Shanbhag has mentored over 50 graduate students who now work at leading technology companies including Qualcomm, Amazon, Nvidia, Intel, and Apple. His research has been generously supported by the National Science Foundation, DARPA, AFRL, Semiconductor Research Corporation, Texas Instruments, Sandia National Laboratories, and industry partners including IBM, GlobalFoundries, and Intel Corporation. He led the Alternative Computational Models research theme (2006-2012) and was the founding Director of the SONIC Center (2013-2017), a 5-year multi-university center funded by DARPA and SRC. Currently, he leads research themes in the SRC and DARPA funded JUMP 2.0 Program's Center for Co-Design of Cognitive Systems and the Center for Ubiquitous Connectivity, and in the NSF IUCRC Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). As Director of the Systems on Nanoscale Information fabriCs (SONIC) Center, Professor Shanbhag leads a multidisciplinary team exploring novel computing paradigms for the nanoscale era. His group has benchmarked an extensive collection of in-memory computing and digital accelerator IC designs, maintaining a publicly available IMC benchmarking repository of metrics extracted from published IC prototypes. His research philosophy integrates concepts from information theory, statistical signal processing, detection and estimation, VLSI architectures, and digital and analog integrated circuits to develop energy-efficient systems from algorithms to silicon implementations.
H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering at Stanford University, where he has been since 2004. He holds the rank of Professor in the Department of Electrical Engineering and serves as the Director of the Stanford Nanofabrication Facility. Prior to Stanford, he spent 16 years at IBM’s T.J. Watson Research Center and served as Vice President of Corporate Research at TSMC (2018–2020), remaining as Chief Scientist in an advisory role thereafter. Leadership roles include founding the Stanford SystemX Alliance and leading the Microelectronics Commons AI Hardware Hub funded by the CHIPS Act. Research focuses on nanotechnology, semiconductor devices, and next-generation computing architectures, including carbon nanotube electronics, 3D integration (N3XT/MOSAIC), and neuromorphic computing. Awarded IEEE Fellow (2001), the IEEE Andrew S. Grove Award, and the J.J. Ebers Award for contributions to electron devices. His work spans device physics, fabrication, and system integration, with over 600 publications. Key contributions include advancements in phase-change memory, carbon nanotube transistors, and compute-in-memory systems. He advises numerous students and collaborates with industry through initiatives like the Stanford Non-Volatile Memory Technology Research Initiative. Recent efforts emphasize AI hardware acceleration, cryo-CMOS for quantum computing, and scalable memory architectures. His lab innovations include CellChips for synthetic biology and hyperdimensional computing using 3D RRAM.
Prof. Baker Mohammad serves as Professor and Director of the System on Chip Lab in the Department of Computer and Information Engineering at Khalifa University. With over 15 years of industrial experience at Intel and Qualcomm designing microprocessors and DSP chips, he bridges academic research with real-world engineering challenges in high-performance computing and low-power systems. His educational background includes: Ph.D. in Electrical and Computer Engineering, University of Texas at Austin (2008) M.S. in Electrical and Computer Engineering, Arizona State University B.S. in Electrical Engineering, University of New Mexico Dr. Mohammad's research spans cutting-edge domains where VLSI design converges with AI acceleration and emerging memory technologies . His work pioneers Memristor applications in environmental sensing (radiation, vacuum, glucose) and neuromorphic computing, while advancing energy harvesting systems for wearable electronics. The integration of in-memory computing with security primitives represents a paradigm shift in hardware design, moving beyond traditional CMOS limitations. His publication trajectory reveals accelerating focus on self-powered neuromorphic systems and RRAM-based architectures, with recent work (2021-2023) emphasizing hardware-software co-design for edge AI. Over 75% of his recent publications involve cross-disciplinary collaborations spanning materials science, chemistry, and biomedical engineering. Notable scientific recognition includes: IEEE TVLSI Best Paper Award 2016 IEEE MWSCAS Myrill B. Reed Best Paper Award Qualcomm Qstar Award for Performance Leadership KUSTAR IP Excellence Award Multiple SRC Techon Best Session Papers As a dedicated mentor, he has supervised over 15 graduate students while securing competitive funding from Khalifa University, ADEK, Qualcomm, Tii, and UAE space agencies. His grant portfolio demonstrates exceptional translational impact, converting fundamental research in memristive devices into drone flight computers and medical sensors. Current projects integrate academic rigor with industrial deployment timelines. The System on Chip Lab operates as a multidisciplinary hub where semiconductor physicists collaborate with AI researchers to develop RISC-V-based secure processors and piezoelectric nanogenerator systems. Recent expansions include partnerships with Tii for aerospace applications and medical device startups for glucose monitoring technology.
Nam Sung Kim is the W. J. "Jerry" Sanders III-Advanced Micro Devices Inc. Endowed Chair and holds a Professorship in Electrical and Computer Engineering at the University of Illinois. He is also affiliated with the Siebel School of Computing and Data Science, Coordinated Science Lab, and National Center for Supercomputing Applications (NCSA). His research focuses on computer architecture, memory systems, chiplet integration, and hardware security. Key areas include energy-efficient computing, processing-in-memory (PIM), and mitigating hardware vulnerabilities like rowhammer attacks. Kim has received prestigious awards including IEEE Fellow (2016), MICRO Hall of Fame (2018), NAI Fellow (2023), and NSF CAREER Award (2015). His work spans publications in top venues like ASPLOS and IEEE journals, addressing topics such as CXL-based memory systems, DRAM module optimization, and GPU architecture improvements. Collaborations emphasize interdisciplinary research in hardware-software co-design and emerging technologies. His labs and teams at Coordinated Science Lab and NCSA drive innovations in scalable computing, near-memory processing, and cloud infrastructure for AI workloads. Ongoing projects include developing resilient memory hierarchies and accelerating large-scale machine learning models through novel architecture designs.
Lan Wei is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Waterloo, Canada. She leads the Waterloo Emerging Integrated Systems Group, focusing on device-circuit co-optimization, cryogenic CMOS for quantum computing, and emerging technologies like GaN, RRAM, and low-dimensional materials. Her work bridges nanoelectronics and system-level applications, with notable contributions to the MIT Virtual Source GaN HEMT (MVSG) compact model, an industry-standard tool. Education: B.S. in Microelectronics and Economics, Peking University (2005) M.S. and Ph.D. in Electrical Engineering, Stanford University (2007, 2010) Research Interests: Nanoelectronic devices Cryogenic CMOS for quantum computing GaN-based circuits and systems RRAM-based neuromorphic computing Device-circuit interactive design Publications reflect her expertise in GaN modeling, quantum computing hardware, and RRAM applications. Recent work emphasizes scalable quantum control circuits and error-resilient neural networks using emerging technologies. Awards include the 2019 Ontario Early Researcher Award and the 2020 UWaterloo President's Excellence Award in Research. She has served on technical committees for IEDM, DATE, and ICCAD, and contributed to the ITRS roadmap. Teaching includes courses like ECE 240 (Electronic Circuits) and ECE 730 (Solid State Devices). Her group actively seeks graduate students with interest in integrated systems and nanoelectronics.
Prof. Dr. Amelie Hagelauer holds a professorship in Micro- and Nanosystem Technology at the TUM School of Computation, Information and Technology, Technical University of Munich. Her work focuses on advanced electronics and systems integration across quantum computing hardware, resistive memory technologies, and high-frequency RF systems. She has contributed to innovations in superconducting qubit readout architectures, multi-level RRAM designs, and 3D-integrated CMOS-compatible quantum devices. Research interests span quantum hardware design, nanoelectronic devices, RF front-end systems, and emerging memory technologies. Her work emphasizes practical implementation challenges such as low-power operation, high-voltage handling in RF switches, and wafer-scale fabrication processes. Recent projects include D-band radar systems, energy-efficient 60 GHz transceivers, and antenna tuning solutions for 5G applications. Publications from 2023-2025 showcase advancements in resistive switching device characterization, mitigation of TLS losses in superconducting qubits, and reconfigurable AI accelerators using RRAM-based digital twins. Her work bridges theoretical device physics with practical integrated circuit design, addressing scalability and reliability in next-gen electronics. Awards and grants: None explicitly listed in provided texts. Active collaborations include EU-funded projects on quantum computing platforms and TUM's Electronic Photonic Integration initiatives. Leads research teams in microsystem technology with emphasis on cross-disciplinary approaches combining CMOS processes, MEMS, and quantum engineering.
Dr. Jing Li is an Associate Professor and Eduardo D. Glandt Faculty Fellow at the University of Pennsylvania , holding dual appointments in the Electrical and Systems Engineering and Computer and Information Science departments. As co-director of the CyberSavvy nationwide security research center and director of the Penn Computational Intelligence Lab (PennCIL) , she pioneers innovations in non-von Neumann computing paradigms. Her research spans post-CMOS technologies, in-memory computing, and hardware-software co-design for security and AI applications. PhD in Computer Engineering, Purdue University (2009) BSc in Electrical Engineering, Shanghai Jiaotong University (2004) Research Focus: Dr. Li's work addresses fundamental challenges in computer systems across the stack. Key areas include: In-Memory Computing: Liquid Silicon architecture combining RRAM with silicon CMOS through monolithic 3D integration Security Engineering: Transforming computer security from "Art" to formal "Engineering" discipline within CyberSavvy Virtualization: Cloud FPGA abstraction layers decoupling compilation from runtime resource management Graph Analytics: Degree-aware optimization techniques for massive-scale graph processing Deep Learning Systems: Roofline model extensions for FPGA-based CNN acceleration Scientific Impact: Awarded DARPA Young Faculty Award , NSF CAREER Award , and IBM CEO Milestone Award , her team has achieved world records in energy-efficient computing (ENIAD supercomputer). With 46 U.S. patents and over 80 publications, she leads ecosystem development for emerging computing architectures through initiatives like the open-source MEG simulation platform . Community Leadership: Dr. Li serves on program committees for flagship conferences ( ISCA , FPGA Symposium ), chairs the International Memory Workshop , and contributes to the MLsys conference's inaugural committee. She actively mentors through multiple PhD openings and industry collaborations.
Daniele Ielmini is a Professor at the Department of Electronics, Information and Bioengineering at Politecnico di Milano, Italy, where he leads research in non-volatile memory technologies and neuromorphic computing. He received his Laurea (with merit) and Ph.D. in Nuclear Engineering from Politecnico di Milano in 1995 and 2000, respectively, and has held visiting positions at Intel Corporation (2006), Stanford University (2006), and the University of Illinois at Urbana-Champaign (2010). His research focuses on the modeling and characterization of non-volatile memories, including nanocrystal memory, charge trap memory, phase change memory (PCM), resistive switching memory (RRAM), and spin-transfer torque magnetic memory (STT-MRAM). He has co-edited the book 'Resistive switching – from fundamental redox-processes to device applications' and published over 300 papers with more than 10,000 citations and an H-index of 69 (Scopus, September 2023). Prof. Ielmini's recent publications demonstrate a strong trend toward in-memory computing and neuromorphic applications, with particular emphasis on closed-loop analog computing architectures, reservoir computing with 2D materials, and hardware security implementations using emerging memory technologies. His work bridges fundamental device physics with practical computing applications, especially for energy-efficient AI acceleration. Intel Outstanding Researcher Award (2013) ERC Consolidator Grant (2014) IEEE-EDS Paul Rappaport Award (2015) Fellow of the IEEE Prof. Ielmini leads multiple ERC-funded projects including SHANNON (Secure Hardware with Advanced Nonvolatile memories), NEURO2D (neuromorphic systems based on reservoir computing in MoS2), and ANIMATE (closed-loop in-memory computing). His research group includes post-doctoral researchers, PhD students, and M.Sc. students working on various aspects of emerging memory technologies and their applications. He serves as Associate Editor for IEEE Trans. Nanotechnology and Semiconductor Science and Technology (IOP), and has served in several Technical Subcommittees of international conferences including IEEE-IEDM, IEEE-IRPS, and IEEE-ISCAS. His laboratory at Politecnico di Milano is equipped with advanced semiconductor device testing equipment including probe-stations, semiconductor parameter analyzers, high-speed waveform generators, and other specialized instruments for nano-electronic research. The lab collaborates with major semiconductor companies including Micron Technology Inc. and STMicroelectronics, as well as participating in national and international research projects.
Boris Murmann is Professor at Stanford University, specializing in integrated circuit design, mixed-signal computing, and energy-efficient AI hardware. His research advances neural interface technologies, analog design automation, and tinyML systems. Recent work develops ultra-low-power neural recording ICs for brain-computer interfaces, RRAM-based memory systems, and open-source semiconductor design frameworks. Publications demonstrate innovations in compressive sensing for neural data, hardware-algorithm co-design, and reinforcement learning for analog circuit synthesis. Significant contributions include Medusa (TinyML processor), EMBER (RRAM macro), and methodologies for coarsely-quantized computer vision and analog design automation.
Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology, and Director of the 3D Systems Packaging Research Center . His research focuses on heterogeneous integration , electrical/photonic interconnects , thermal modeling , and electronics for healthcare , with over 180 publications and 12 U.S. patents. Research areas include: Advanced cooling and power delivery for emerging systems Biosensor-CMOS integration 2.5D/3D IC packaging Polylithic integration technology Nanofabrication for microsystems Scientific accolades include: 2018 IEEE EPS Exceptional Technical Achievement Award 2013 Intel Early Career Faculty Honor Award 2012 DARPA Young Faculty Award 2011 IEEE CPMT Outstanding Young Engineer Award Best paper awards at IEEE ECTC, IITC, and CICC 2020 Georgia Tech Doctoral Thesis Advisor Award His lab explores integrated 3D systems with emphasis on co-design of thermal, power, and electrical networks for machine learning and healthcare applications.
