Luciano Lavagno is a Full Professor at the Department of Electronics and Telecommunications, Polytechnic University of Turin, with over two decades of academic and research contributions. His work bridges hardware acceleration, low-power electronics, and intelligent system design. Research Focus: Hardware-accelerated machine learning, high-level synthesis (HLS) for FPGA/ASIC, heterogeneous CPU/GPU/FPGA platforms Key Projects: SPACE (predictable acceleration), REBECCA (secure AI acceleration), HPC-National Center (quantum computing), and oral history preservation via "Ti racconto una storia" initiative His recent publications analyze CNN inference optimization, subgraph isomorphism, and superword-level parallelism exploitation. Lavagno supervises multiple PhD students working on FPGA acceleration, neural network hardware, and embedded systems. As Principal Investigator for national and EU-funded projects (PRIN, JTI-ECSEL, PNRR), he drives advancements in sustainable computing infrastructure. His patented technologies include MIx&Latch timing methodology, capacitive sensing innovations, and 5G acceleration frameworks.
Prof. Dr.-Ing. Jürgen Teich is a full Professor and Chair for Hardware-Software Co-Design at the Department of Computer Science, Friedrich Alexander University Erlangen-Nuremberg (FAU). He serves as Head of Department Computer Science and Vice Dean of the Technical Faculty since August 2024, and has been Speaker of the FAU Research Center Embedded System Initiative (FAU ESI) since 2023. His educational background includes: Diploma degree in Electrical Engineering, University of Kaiserslautern (1989) Dr.-Ing. degree in Electrical Engineering, University of Saarland (1993) Habilitation (PD Dr.-Ing.) entitled "Synthesis and Optimization of Digital Hardware/Software Systems" (1996) Prof. Teich's research focuses on Embedded Systems , Invasive Computing , Hardware-Software Co-Design , and Reconfigurable Computing . His work spans from theoretical foundations to practical implementations, with particular emphasis on resource-constrained systems, many-core architectures, and energy-efficient computing. He has pioneered research in invasive computing paradigms that enable more efficient use of many-core processors by allowing applications to dynamically claim resources. His recent publications reveal a strong trend toward energy-efficient AI deployment on embedded devices , security of embedded systems , and novel memory technologies . There's a clear focus on practical implementations of machine learning on microcontrollers (TinyML), hardware acceleration for data processing, and innovative approaches to power management in self-powered systems. Among his notable scientific awards are: IEEE Fellow (since 2018) Member of Academia Europaea, Section Informatics (since 2011) Member of the National Academy of Science and Engineering (acatech) (since 2018) Member of the German Society of Humboldtians (since 2021) Prof. Teich has been Principal Investigator for numerous DFG-funded projects including SFB/Transregio 89 "Invasive Computing" (2010-2022), SFB 694, and multiple priority programs. He has coordinated large collaborative research efforts across Germany and internationally, with significant funding from DFG and other sources. His research group has produced influential work in embedded systems design and co-design methodologies. He leads the Hardware-Software Co-Design research group at FAU, which focuses on innovative approaches to embedded system design, invasive computing architectures, and efficient implementation of machine learning on resource-constrained devices. The group maintains strong collaborations with industry partners including Intel, Xilinx, and automotive companies.
Maurizio Martina is a Full Professor at the Department of Electronics and Telecommunications (DET) of Politecnico di Torino. He is a member of the Interdepartmental Center PEIC - Power Electronics Innovation Center and serves as an Associate Editor for the IEEE Transactions on Circuits and Systems I (2018-2023). His research focuses include: Digital circuits and signal processing Machine learning hardware architectures RISC-V extensions and post-quantum cryptography VLSI design for edge computing and IoT Recent publications emphasize cryptographic hardware implementations (CHIMERA, Keccak co-processors), RISC-V integration methodologies, and privacy-preserving neural network frameworks. His work spans VLSI architectures for video processing, bio-inspired electronics, and error correcting codes, with applications in cybersecurity, robotics, and biomedical systems. Scientific Recognition : Premio Nazionale Innovazione (2013) Premio dei Premi (2014) He supervises 12 PhD students across cycles 35-40 in Electrical, Electronics and Communications Engineering, including: Valeria Piscopo (2024-in progress) Alessandra Dolmeta (2022-in progress) Luigi Giuffrida (2022-in progress) Walid Walid (2019-2023) As part of the VLSILAB Group , his research explores hardware accelerators for machine learning, post-quantum cryptography on RISC-V, and bio-inspired embedded systems. Teaching activities include courses on Integrated Systems Architecture and Hardware & Wireless Security at Politecnico di Torino and Università di Pavia.
Dr. Brett J. Borghetti is a Professor of Computer Science in the Department of Electrical and Computer Engineering at the Air Force Institute of Technology (AFIT), Graduate School of Engineering and Management, Wright-Patterson AFB, OH. He was promoted to Professor in July 2022, following prior appointments as Associate Professor (2017) and Assistant Professor (2008/2013). His expertise lies in artificial intelligence, machine learning, deep learning, cybersecurity, and human-machine teaming. Education: Ph.D. in Computer Science, University of Minnesota, Twin Cities (2008) M.S. in Computer Systems, Air Force Institute of Technology (1996) B.S. in Electrical Engineering, Worcester Polytechnic Institute (1992) Dr. Borghetti's research focuses on applying machine learning to physical science sensors (hyperspectral, seismic, RF), cybersecurity, and enhancing human-machine team performance. He teaches graduate courses in machine learning, AI, data security, and algorithm design, and advises numerous MS and PhD students in areas such as sensor exploitation, cognitive workload, and cyber situational awareness. His recent publications demonstrate strong trends in deep learning for multimodal sensor fusion, nuclear security, and neuroergonomics. Scientific Awards: AETC Educator of the Year (2021, Civilian) AFIT Ezra Kotcher Teaching Award (2021) AFIT Teaching Excellence Award (2019) AF STEM Outstanding Science and Educator Award (2015) Multiple Eta Kappa Nu Outstanding Instructor Awards Air Force Meritorious Service Medal and other military honors Dr. Borghetti has advised numerous graduate students and led research projects with significant funding and applications in defense and national security. He has directed research in AI-driven sensor analysis, cyber defense systems, and adaptive automation. His work often involves collaboration with national labs and DoD agencies. He has contributed to major research initiatives in human factors, cyber intruder detection, and machine learning for operational environments. Labs and Research Teams: His work is associated with AFIT's research in cyber security, sensor exploitation, and human-machine systems. He collaborates with teams working on the Cyber Intruder Alert Testbed (CIAT), neuroergonomic modeling, and machine learning for defense applications.
Dr. Christoph Leitner is a Research Fellow at ETH Zurich's Integrated Systems Laboratory under Prof. Luca Benini, focusing on biomedical and IoT applications. His work integrates printed piezoelectric transducers and flexible electronics with energy-efficient systems. He holds a PhD in Biomedical Engineering from TU Graz (2022) and has collaborated with institutions like Sant'Anna School of Advanced Studies and KTH Stockholm. Notable achievements include the Josef Krainer Young Researcher Award and Motorik Scholarship. Leitner's research spans ultrasonics, machine learning, and wearable devices, with contributions to muscle-tendon dynamics and real-time biofeedback systems. Education: PhD in Biomedical Engineering, TU Graz (2022), Advisor: Prof. Christian Baumgartner Previous roles: University Assistant (2006–2011) and R&D Engineer at Virtual Vehicle GmbH Research Interests: Convergent technologies merging biomedical engineering and IoT Ultrasound-based monitoring for musculoskeletal systems Energy-efficient embedded systems for wearable applications Collaborations & Awards: Recipient of Josef Krainer Young Researcher Award (2023) and Motorik Scholarship (2018) Active collaborations with University of Zurich, Veterinary University of Vienna, and Queensland University of Technology Labs & Projects: Integrated Systems Laboratory at ETH Zurich Developed a patented ultrasound-transparent tattoo-based SEMG system with Prof. Francesco Greco
Simon Moore is a Professor of Computer Engineering at the University of Cambridge's Department of Computer Science and Technology. He leads the Computer Architecture research group, focusing on secure processors and subsystems, particularly the CHERI project. His work emphasizes formal verification, hardware-software co-design, and scalable security solutions. He is a Fellow and Director of Studies at Trinity Hall, overseeing undergraduate admissions and mentoring in Computer Science. Research Interests: Moore's primary focus is the CHERI secure processor architecture, integrating RISC-V cores with formal verification. His work spans secure hardware design, memory safety, and embedded systems. Notable contributions include the CHERI-RISC-V microarchitecture, CheriABI, and formal verification frameworks. Key Projects: CHERI, CheriBSD, Morello (ARM collaboration) Recent Achievements: Test of Time Award (IEEE Security & Privacy 2025), finalist for Bhattacharyya Award (2022) Grants: Innovate UK Digital Security by Design, DARPA Mission Oriented Resilient Clouds Publications: Over 200 papers on secure architectures, including influential work on CHERI's capability model, formal verification, and hardware security. Recent focus areas include temporal memory safety, embedded system security, and GPU-based capability systems. Labs/Teams: Directs the Computer Architecture Group and collaborates with industry partners like ARM and Microsoft on CHERI implementations.
Dr Graeme Bragg is a Senior Teaching Fellow at the University of Southampton within the Department of Electronics and Computer Science . His work spans teaching, research, and technical development with a focus on event-driven computing, bioinformatics, and computational modeling. He actively supervises PhD students and collaborates on interdisciplinary projects. Research Interests: Parallel computing, event-driven systems, genotype imputation, Petri net simulations, subglacial hydrology modeling Teaching: Specializes in hardware description languages and computational methods for engineering students Technical Expertise: RISC-V architecture, FPGA acceleration, bespoke compute fabric development His recent publications demonstrate expertise in applying event-driven computing to diverse problems including: 2025: Automated marking systems for SystemVerilog labs 2025: Seasonal dynamics in subglacial hydrology 2023: Genotype imputation using custom hardware 2022: Optimization algorithms and graph analysis Current research explores: Custom RISC-V FPGA clusters for bioinformatics Event-triggered systems for scientific simulations Parallel computing solutions for molecular modeling Contact: gmb@ecs.soton.ac.uk | +44 23 8059 2784
Professor Klaus McDonald-Maier is a full Professor in the School of Computer Science and Electronic Engineering (CSEE) at the University of Essex , where he leads the Embedded and Intelligent Systems (EIS) Research Laboratory and heads the Intelligent Embedded Systems and Environments Research Group . He is also Director of Impact , Visiting Professor at the University of Kent, and Visiting Research Affiliate at NASA Jet Propulsion Laboratory, California Institute of Technology. Education PhD in High-Performance Parallel Neural Network Architectures, Friedrich-Schiller-University Jena (Germany, 1999) Electronic Engineering studies, University of Ulm (Germany) Electronic Engineering studies, Cardiff University (Wales) Electronic Engineering studies, École Supérieur de Chimie Physique Électronique de Lyon (CPE-Lyon) (France) Research Interests Professor McDonald-Maier’s research integrates embedded systems , System-on-Chip (SoC) architectures , and AI-driven robotics . He pioneers visual place recognition techniques that remain robust under severe appearance and viewpoint changes, develops cybersecurity frameworks based on ICMetrics for autonomous vehicles and IoT, and designs approximate real-time computing solutions for energy-constrained multicore and FPGA platforms. His work on radiation-tolerant systems supports space and nuclear applications, while his bio-inspired algorithms enable lightweight, neuromorphic perception on resource-limited robots. Publication Trends Between 2022 and 2025 his output converges on FPGA-accelerated AI , secure edge intelligence , visual navigation for autonomous systems , and healthcare analytics . He repeatedly couples rigorous algorithmic innovation with practical hardware deployment, yielding energy-efficient, real-time systems validated in domains ranging from autonomous driving to post-stroke rehabilitation. Scientific Awards & Recognition Best Paper Award – IEEE Transactions on Sustainable Computing (2024) Best Paper Award – IEEE/ACM DATE (2024) Best Paper Award – IEEE Systems Journal (2022) Best Paper Award – IEEE Sensors Journal (2021) Best Paper Award – IEEE Access (2020) Research Grants & Industrial Collaboration He has secured major funding from EPSRC , EU Horizon 2020 , Innovate UK , and industry partners. Current projects span trustworthy autonomy, radiation-hardened edge AI, and AI-enhanced rehabilitation technologies. He is Chief Scientist of UltraSoC Technologies Ltd and CEO of Metrarc Ltd , commercialising University research in semiconductor debug and cybersecurity respectively. Laboratory & Team Leadership As Director of the Embedded and Intelligent Systems Laboratory (EIS Lab) , he oversees a multidisciplinary team of researchers and PhD students, providing state-of-the-art FPGA, robotics, and embedded-systems facilities. The lab collaborates closely with NASA JPL, UK Atomic Energy Authority, and leading semiconductor firms to translate fundamental research into high-impact industrial solutions.
Pasquale Davide Schiavone holds multiple research and teaching positions at École Polytechnique Fédérale de Lausanne (EPFL), serving as a Lecturer at the School of Computer and Communication Sciences (IC) and as a Scientist at both the Embedded Systems Laboratory (ESL) within the School of Engineering (STI) and PAT Administration. His interdisciplinary work bridges computer architecture, embedded systems design, and biomedical applications, with office located at ELG 136 in Lausanne, Switzerland. Dr. Schiavone's research focuses on ultra-low-power computing systems, particularly RISC-V architectures and TinyML applications for edge devices. His work develops open-source hardware platforms like X-HEEP and HEEPOCRATES that enable energy-efficient AI at the edge, with applications spanning biomedical monitoring, neural interfaces, and wearable computing. He explores innovative hardware-software co-design approaches to overcome energy constraints in resource-limited environments. His recent publications reveal a consistent research trajectory centered on open, configurable computing platforms for specialized applications. The work spans from fundamental RISC-V architecture improvements (ARCANE, e-GPU) to application-specific implementations for biomedical contexts (BiomedBench, neural interfaces). A strong emphasis on energy efficiency permeates all his research, whether through novel arithmetic approaches (Posit), system architecture (near-memory computing), or specialized accelerators (Strela, Quadrilatero). Lecturer, School of Computer and Communication Sciences (IC) Scientist, Embedded Systems Laboratory (ESL), School of Engineering (STI) Scientist, PAT Administration, School of Engineering (STI) Dr. Schiavone teaches courses on hardware compilation, presenting algorithms and methods for transforming hardware description languages into optimized circuit implementations. His Embedded Systems Laboratory work places him at the forefront of developing practical, open-source solutions for next-generation computing challenges in energy-constrained environments.
Luca Sterpone is a Full Professor at the Department of Control and Computer Science (DAUIN), Politecnico di Torino. He serves as Head of the Control and Computer Engineering Department (2023-2027), coordinates the Aerospace and Safety Computing Lab, and is a member of the Academic Senate and Power Electronics Innovation Center (PEIC). His research spans reconfigurable computing, fault tolerance, and radiation effects analysis in electronic systems. Professor since 2021 Department Head (DAUIN) since 2023 Coordinates international collaborations with ESA, AMD Xilinx, NVIDIA, and Thales Alenia Space Develops radiation-hardened FPGA tools (SETA, VERI-Place, PyXEL) 2007 EDAA Outstanding Dissertation Award and 2005 IEEE Best Paper Award Research Focus : Designing radiation-tolerant systems for aerospace, including fault-tolerant AI accelerators, FPGA reliability, and software-based error mitigation. He investigates soft error propagation in nanoscale circuits and develops tools for radiation sensitivity analysis in VLSI. His work integrates hardware-software co-design for mission-critical applications. Awards : EDAA Outstanding Dissertation Award (2007) IEEE European Test Symposium Best Paper (2005) SMACD Best EDA Tool Award (2018) ARC Best Paper candidate (2018) Teaching : He leads courses in Reconfigurable Computing (PhD level), GPU Programming , and Operating Systems . He has formal responsibility for teaching roles across 9 bachelor's and 7 master's years, and mentors multiple PhD students. Collaborations : Coordinates with the European Space Agency (ESA), University of Bielefeld, Universidad de Sevilla, and industrial partners like AMD Xilinx, NVIDIA, and General Motors. He leads projects such as RESCHIP4EU, VEGAS, and TERRAC for radiation-hardened computing solutions.
Pablo Parra Espada is an Associate Professor at the Department of Automática, University of Alcalá (Spain), affiliated with the Space Research Group (SRG-UAH). He holds a PhD from the University of Alcalá (2012) titled Integración de tecnologías de desarrollo y análisis basadas en componentes bajo un enfoque multi-plataforma , supervised by Dr. Sebastián Sánchez Prieto and Dr. Óscar Rodríguez Polo. His research focuses on space systems engineering , particularly in RISC-V processor design , embedded systems , and model-driven engineering . Key areas include hardware-software co-design for satellite systems, real-time computing, and fault-tolerant architectures. He has contributed to the Solar Orbiter mission through work on the Energetic Particle Detector (EPD) and its on-board software validation. His recent work emphasizes virtualization techniques for LEON processors, FPGA-based digital beamforming , and spaceborne phased array systems . He also explores model-driven approaches for automated configuration of ground support equipment. His interdisciplinary contributions bridge computer architecture with aerospace applications. Prof. Parra Espada has published extensively on topics such as hardware performance monitoring, memory management units for satellites, and system-level verification of space software. His work combines rigorous engineering methodologies with cutting-edge technologies to address challenges in space instrumentation and embedded systems.
Guido Masera is a Full Professor at the Department of Electronics and Telecommunications (DET) at the Polytechnic University of Turin, where he has been actively involved in teaching and research for over two decades. He serves as a Member of the Board of Directors, Member of the GEDI Observatory for Gender Equality, Diversity and Inclusion, and Member of the Permanent University Observatory for monitoring the academic supply chain. His research interests span across channel decoders, circuits for communications, cryptography, deep learning, digital integrated circuits, field programmable gate arrays (FPGA), and hardware design. His work focuses on VLSI architectures for image and video coding, digital architectures for error correcting codes, application specific approximate computing, VLSI architectures for machine learning, digital architectures for bio-inspired processing, digital architectures for post-quantum cryptography, bio-inspired electronics for robotics and biomedical applications, RISC-V extensions and hardware accelerators, and circuit architectures for efficient machine learning and artificial intelligence. His recent publications (2025) demonstrate a strong focus on RISC-V architecture, particularly in the context of cryptographic implementations, hardware security, and post-quantum cryptography. His research group VLSILAB is actively engaged in cutting-edge research in hardware security, efficient processor design, and specialized computing architectures. Among his notable recognitions are the Premio Francesco Carassa awarded by the Telecommunications and Information Technologies Group Association (gtti) in 2010, and his recognition as a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) since 2007. He also serves as an Associate Editor for several prestigious journals including ELECTRONICS (2019-present), IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS (2015-2019), and IET CIRCUITS, DEVICES & SYSTEMS (2013-2016). Professor Masera has advised numerous PhD students working on advanced topics in VLSI design, post-quantum cryptography, hardware accelerators, and machine learning implementations. His current research projects include ISOLDE (2023-2026) and TRISTAN (2022-2025), both EU-funded projects focused on RISC-V technology and domain-specific ecosystems. He leads the VLSILAB research group at the Department of Electronics and Telecommunications, which focuses on cutting-edge research in VLSI architectures, hardware security, and specialized computing systems. The group collaborates with industry partners and participates in major European research initiatives.
Prof. Dr.-Ing. Marc Reichenbach serves as the Chair of Integrated Systems at the Institute for Applied Microelectronics and Data Technology at the University of Rostock. His office is located at Albert-Einstein-Straße 26, 18059 Rostock, Room 102 (1st floor), with contact information including telephone (0381) 498 7270 and email marc.reichenbach@uni-rostock.de. Professor Reichenbach's research focuses on the intersection of hardware design and artificial intelligence, with particular expertise in memory technologies and computing architectures. His work spans several key areas: Development of specialized computer architectures for deep learning applications Advanced VLSI design and CPU architecture Emerging memory technologies, particularly RRAM (Resistive Random-Access Memory) FPGA-based acceleration systems Hardware implementations for neural networks and AI applications Analysis of Professor Reichenbach's recent publications (2023-2025) reveals a strong focus on memory computing technologies, particularly RRAM-based systems. His work demonstrates expertise across multiple dimensions of computer architecture including ASIC design, FPGA acceleration, and novel memory systems. The publications show a clear trajectory toward implementing AI and machine learning capabilities directly in hardware, with applications ranging from edge computing to satellite systems. A significant portion of his recent work addresses the challenges of implementing neural networks using emerging memory technologies, focusing on efficiency, reliability, and performance optimization. Professor Reichenbach teaches several advanced courses including: Computer architectures for deep learning applications Project seminar Embedded Systems Advanced VLSI Design (Advanced CPU Design) His research group appears to be actively engaged in several cutting-edge projects related to hardware acceleration for AI applications, memory computing, and embedded systems design. The group collaborates on projects involving digital twins for hardware systems, real-time operating systems for heterogeneous architectures, and specialized computing systems for various applications from medical devices to drone technology.
Daniel Müller-Gritschneder is an Adjunct Teaching Professor (Privatdozent) at the Technical University of Munich (TUM), affiliated with the Chair of Electronic Design Automation. He leads the 'Electronic System Level' research group, focusing on embedded systems, TinyML, virtual prototyping, and hardware resilience. He temporarily served as head of the Chair of Real-Time Systems (2019–2020) and holds a senior membership in IEEE. His research spans: TinyML : Optimizing neural network inference for microcontrollers. Virtual Prototyping : Fast simulation for embedded software development (e.g., ETISS simulator). Runtime Verification : Hardware monitoring for safety-critical systems. Fault Tolerance : Cross-layer resilience against soft errors. Design Automation : NoC synthesis and RISC-V toolchain optimization. His publications emphasize RISC-V-based systems, TinyML deployment, fault injection, and embedded AI. Recent works show trends toward compiler-assisted security, thermal management, and automated design-space exploration for edge devices. Awards: Best Paper Award (SiPS 2019) Habilitation Award (Bund der Freunde der TUM, 2019) 2nd Best Paper (SMACD'15) Best Paper nominations at DAC'07, DATE'10, Analog'10, NOCS'13 He advises researchers in the Electronic System Level group and contributes to EU projects (e.g., Scale4Edge). His lab develops tools like ETISS, MLonMCU, and Seal5 for RISC-V and TinyML ecosystems.
Maria Mushtaq is an Associate Professor at Telecom Paris , affiliated with the Information Processing and Communication Laboratory (LTCI) and the Secure and Safe Hardware (SSH) Lab . She received her PhD in Information Security from the University of South Brittany, France (2019) and completed 2 years of postdoctoral research at LIRMM, University of Montpellier under the CNRS excellence post-doc grant. Research Focus: Microarchitectural vulnerability assessment, runtime mitigation against side/covert-channel attacks, cryptanalysis, OS-based security primitives, and hardware-software interface security Technical Expertise: Cache timing attacks, transient execution attacks (Spectre/Meltdown), Hardware Performance Counter analysis, gem5 simulation Her recent work involves RISC-V security analysis using gem5 simulations and machine learning for attack detection. She serves as Guest Editor for the Journal of Applied Sciences special issue on Side Channel Attacks in Embedded Systems and has been on the Program Committee for the European Test Symposium (2020-2021). 2021 HiPEAC Collaboration Grant recipient Organized IP Paris Winter School on Microarchitectural Security (2022) Active in international conferences as panelist and keynote speaker
