جست‌وجوی استاد و پژوهشگر

• Computer Engineering
• Circuit Design
• Fault Tolerance
• +۶ مورد دیگر

Matteo Sonza Reorda is a Full Professor at the Polytechnic University of Turin, affiliated with the Department of Automatic Control and Computer Science (DAUIN). He holds roles such as Partnership Agreement Coordinator with SMAT and has served as Vice-Rector for Research (2021–2024). His research focuses on fault tolerance, hardware reliability, and AI acceleration, with contributions to GPU/CNN reliability, self-test libraries, and defect-oriented testing. Education: M.S. in Electronics Engineering, Politecnico di Torino (1986) Ph.D. in Computer Engineering, Politecnico di Torino (1990) Research Interests: His work spans automatic test equipment, circuit reliability, GPU fault tolerance, neural network hardening, and embedded systems safety . He leads the Electronic CAD & Reliability Group and collaborates with institutions like the ISI Foundation and the National Research Council (CNR). Publications & Impact: With over 180 publications, his recent work emphasizes AI accelerator reliability, fault injection techniques, and safety-critical systems. Key trends include GPU resilience for CNNs, self-test library optimization, and radiation fault modeling in neural networks. Awards & Recognition: IEEE Fellow (2016–) Multiple best-paper awards at IEEE conferences (DDECS, DATE, etc.) Grants & Collaborations: Coordinator of EU projects (RESCUE, TUTORIAL) Partnerships with EDF, Marelli Europe, and SMAT Lead on National HPC/Quantum Computing Spoke 1 (2022–2025) Labs/Teams: Leads the CAD Group and collaborates with the French-Italian LIA LAFISI lab on hardware-software integration.

• Computer Engineering
• Embedded Systems
• Fault Tolerance
• +۴ مورد دیگر

Corrado De Sio is a Fixed-term Researcher at the Department of Control and Computer Science (DAUIN) , Politecnico di Torino , affiliated with the College of Computer, Film, and Mechatronics Engineering . His academic roles include course instruction and collaboration for Reconfigurable Computing , High Performance Computing (HPC) , and Operating Systems for High-Performance Supercomputers across multiple academic years (2020-2025). Research Interests focus on: Reliability of reconfigurable systems and FPGAs under radiation effects Hardware-software co-design for fault tolerance Embedded systems in aerospace and safety-critical applications Machine learning acceleration on reconfigurable hardware Radiation effects on real-time operating systems and CNN implementations Recent publications address: 2025: Selective hardening of RISCV soft-processors for space applications 2025: Real-time 'signal for help' gesture recognition systems 2024: Reliability analysis of RISC-V processors and CNN placement algorithms 2023: Fault tolerance in FPGA-based CNNs and radiation effects on RTOS Patents include: PyXEL - Python Toolkit for Reconfigurable Hardware Surveillance Software for Real-Time Violence Detection Academic Supervision : Co-supervisor for PhD candidate Arash Amini Bardpareh in Computer and Systems Engineering .

• Digital Hardware Design
• Reliability Engineering
• Reconfigurable Devices
• +۳ مورد دیگر

Eleonora Vacca is a PhD student and Research Fellow in the Department of Automatic Control and Computer Science (DAUIN) at the Polytechnic University of Turin. She holds a B.S. in Electronic Engineering from the University of Palermo (2018) and an M.S. in Electronic Engineering-Embedded Systems from Politecnico di Torino (2021). Her research focuses on digital hardware design, reliability engineering, reconfigurable devices, and AI applications in aerospace and safety-critical systems. She is a member of the Aerospace and Safety Computing Lab and the CAD - Electronic CAD & Reliability Group (DAUIN). Her work addresses challenges such as radiation effects mitigation in space missions, fault-tolerant AI accelerators, and real-time anomaly detection in satellite telemetry. She has contributed to projects like the RAMSES CubeSat-1 Development (2025-2026), funded by commercial contracts. In 2024, she won the Best Student Paper Award at the NEWCAS Conference for her research on radiation effects in space missions. Vacca collaborates on teaching, including assisting in the course 'Electronic Calculators' for Computer Engineering students. Her recent publications explore AI resilience in RISC-V ecosystems, radiation environment analysis for space missions, and gesture recognition systems for smart cities. She actively contributes to conferences such as the ACM International Conference on Computing Frontiers and the IEEE International Smart Cities Conference.

Luciano Lavagnoمشاهده پروفایل

استاد

• Field Programmable Gate Arrays (FPGA)
• High-Level Synthesis
• Indoor Positioning
• +۱۰ مورد دیگر

Luciano Lavagno is a Full Professor at the Department of Electronics and Telecommunications, Polytechnic University of Turin, with over two decades of academic and research contributions. His work bridges hardware acceleration, low-power electronics, and intelligent system design. Research Focus: Hardware-accelerated machine learning, high-level synthesis (HLS) for FPGA/ASIC, heterogeneous CPU/GPU/FPGA platforms Key Projects: SPACE (predictable acceleration), REBECCA (secure AI acceleration), HPC-National Center (quantum computing), and oral history preservation via "Ti racconto una storia" initiative His recent publications analyze CNN inference optimization, subgraph isomorphism, and superword-level parallelism exploitation. Lavagno supervises multiple PhD students working on FPGA acceleration, neural network hardware, and embedded systems. As Principal Investigator for national and EU-funded projects (PRIN, JTI-ECSEL, PNRR), he drives advancements in sustainable computing infrastructure. His patented technologies include MIx&Latch timing methodology, capacitive sensing innovations, and 5G acceleration frameworks.

• Digital Circuits
• Digital Signal Processing
• Machine Learning
• +۱۰ مورد دیگر

Maurizio Martina is a Full Professor at the Department of Electronics and Telecommunications (DET) of Politecnico di Torino. He is a member of the Interdepartmental Center PEIC - Power Electronics Innovation Center and serves as an Associate Editor for the IEEE Transactions on Circuits and Systems I (2018-2023). His research focuses include: Digital circuits and signal processing Machine learning hardware architectures RISC-V extensions and post-quantum cryptography VLSI design for edge computing and IoT Recent publications emphasize cryptographic hardware implementations (CHIMERA, Keccak co-processors), RISC-V integration methodologies, and privacy-preserving neural network frameworks. His work spans VLSI architectures for video processing, bio-inspired electronics, and error correcting codes, with applications in cybersecurity, robotics, and biomedical systems. Scientific Recognition : Premio Nazionale Innovazione (2013) Premio dei Premi (2014) He supervises 12 PhD students across cycles 35-40 in Electrical, Electronics and Communications Engineering, including: Valeria Piscopo (2024-in progress) Alessandra Dolmeta (2022-in progress) Luigi Giuffrida (2022-in progress) Walid Walid (2019-2023) As part of the VLSILAB Group , his research explores hardware accelerators for machine learning, post-quantum cryptography on RISC-V, and bio-inspired embedded systems. Teaching activities include courses on Integrated Systems Architecture and Hardware & Wireless Security at Politecnico di Torino and Università di Pavia.

Luca Sterponeمشاهده پروفایل

استاد

• Reconfigurable computing
• Computer-aided design algorithms
• Fault tolerance and reliability
• +۷ مورد دیگر

Luca Sterpone is a Full Professor at the Department of Control and Computer Science (DAUIN), Politecnico di Torino. He serves as Head of the Control and Computer Engineering Department (2023-2027), coordinates the Aerospace and Safety Computing Lab, and is a member of the Academic Senate and Power Electronics Innovation Center (PEIC). His research spans reconfigurable computing, fault tolerance, and radiation effects analysis in electronic systems. Professor since 2021 Department Head (DAUIN) since 2023 Coordinates international collaborations with ESA, AMD Xilinx, NVIDIA, and Thales Alenia Space Develops radiation-hardened FPGA tools (SETA, VERI-Place, PyXEL) 2007 EDAA Outstanding Dissertation Award and 2005 IEEE Best Paper Award Research Focus : Designing radiation-tolerant systems for aerospace, including fault-tolerant AI accelerators, FPGA reliability, and software-based error mitigation. He investigates soft error propagation in nanoscale circuits and develops tools for radiation sensitivity analysis in VLSI. His work integrates hardware-software co-design for mission-critical applications. Awards : EDAA Outstanding Dissertation Award (2007) IEEE European Test Symposium Best Paper (2005) SMACD Best EDA Tool Award (2018) ARC Best Paper candidate (2018) Teaching : He leads courses in Reconfigurable Computing (PhD level), GPU Programming , and Operating Systems . He has formal responsibility for teaching roles across 9 bachelor's and 7 master's years, and mentors multiple PhD students. Collaborations : Coordinates with the European Space Agency (ESA), University of Bielefeld, Universidad de Sevilla, and industrial partners like AMD Xilinx, NVIDIA, and General Motors. He leads projects such as RESCHIP4EU, VEGAS, and TERRAC for radiation-hardened computing solutions.

• Reliable and Fault-Tolerant Computing
• RISC-V Architecture
• FPGA-Based Systems
• +۱۲ مورد دیگر

Sarah Azimi is a fixed-term researcher at the Department of Control and Computer Science (DAUIN) within the College of Computer, Film and Mechatronics Engineering at Politecnico di Torino. She actively contributes to research and teaching in the domains of reliable computing, reconfigurable systems, and AI applications for space and smart city security. Research Interests: Reliability and fault tolerance in safety-critical and space systems RISC-V and FPGA-based architectures High-performance computing (HPC) and reconfigurable computing AI resilience and real-time gesture recognition for public safety Radiation effects and hardening techniques for aerospace applications Publication Trends: Her recent publications focus on RISC-V reliability, radiation effects in space missions, AI resilience in reconfigurable platforms, and smart city security through gesture recognition. Her work spans both journal and conference venues, emphasizing practical and mission-tailored solutions in embedded and aerospace computing. Scientific Awards: No awards explicitly mentioned in the provided text. Advising and Grants: Sarah Azimi supervises multiple PhD students including Federico Buccellato, Aobo Cui, and Giorgio Cora. She leads the competitive research project Safe Smart City: Detecting Violence and Requests for Help in Real Time Through Video Surveillance Devices (2024). She is also a member of the RAMSES CubeSat-1 Development project (2025–2026) and led the commercial research project on the Rempro fault-tolerant processor (2022–2023). Labs and Teams: She is a key member of the CAD - Electronic CAD & Reliability Group (DAUIN) at Politecnico di Torino, contributing to cutting-edge research in electronic design automation and system reliability for aerospace and terrestrial applications.

• AI Safety
• Reliability of AI Systems
• Testing of Digital Circuits
• +۱ مورد دیگر

Annachiara Ruospo is a Assistant Professor at the Department of Control and Computer Engineering (DAUIN) at Politecnico di Torino. She holds a Fixed-Term Researcher position under Italian Law 240/10, art.24-A, and is actively involved in teaching and research projects. Research Interests : AI Safety, Reliability of AI Systems, Testing of Digital Circuits, Statistical Reliability Investigations. Her recent research focuses on hardware reliability for AI systems , including fault injection methodologies, quantized neural networks, and side-channel vulnerabilities. She collaborates on EU-funded projects like REACT and commercial contracts such as TC4xx NVM Test Strategies . Scientific Awards : None explicitly mentioned. Supervised Students : Antonio Porsia (PhD candidate, Reliability and Security of AI-Based Systems) and Vittorio Turco (PhD candidate, Reliability Evaluation and Hardening of AI Accelerators). She contributes to AI hardware security through patents like A Shannon-Hartley-Based Approach to Measure the Criticality of Synaptic Weights and actively participates in conferences such as the IEEE Latin American Test Symposium and IEEE VLSI Test Symposium .

Roberto Giorgiمشاهده پروفایل

دانشیار

• Computer Architecture
• Multiprocessor Systems
• Multicore Architectures
• +۶ مورد دیگر

Roberto Giorgi is an Associate Professor of Computer Engineering at the Department of Information Engineering, University of Siena, Italy. He has held this position since October 1, 2006, following his tenure as an Assistant Professor since March 15, 1999. His educational background includes a Ph.D. in Computer Engineering from the University of Pisa (1999) with a thesis on coherence protocols for shared-memory multiprocessors, and an Electronic Engineering degree (1995) with a thesis on trace-driven performance evaluation of multiprocessors. Giorgi's primary research focuses on Computer Architecture , particularly on multiprocessor/multicore issues including processor design, coherence protocols, programmability, and energy efficiency. His work spans both theoretical and practical aspects of computer architecture, with emphasis on real-world implementations and educational tools. He has coordinated significant EU-funded projects including AXIOM (2014-2018) on Smart Cyber-Physical Systems and TERAFLUX (2009-2014) on Many-Cores. His recent publications (2022-2025) demonstrate a strong progression toward practical applications of computer architecture research, with particular emphasis on RISC-V architecture, FPGA-based acceleration, dataflow computing models (especially DF-Threads), and graph processing. Many of his papers address educational tools for computer architecture education, real-time object detection on embedded platforms, and novel execution paradigms for edge computing and HPC. IEEE Senior Member ACM Lifetime Member Coordinator of EU-funded AXIOM project (2014-2018) on Smart Cyber-Physical Systems Coordinator of EU-funded TERAFLUX project (2009-2014) on Many-Cores Giorgi has been actively involved in securing research funding and building collaborations, particularly in high-performance computer architecture research with emphasis on scalable architectures and embedded systems. He leads the Computer Architecture Lab (ROOM 223) at the University of Siena, which was established in 2007, and has been instrumental in developing practical implementations of architectural concepts including the AXIOM platform for cyber-physical systems.

• Channel decoders
• Circuits for communications
• Cryptography
• +۸ مورد دیگر

Guido Masera is a Full Professor at the Department of Electronics and Telecommunications (DET) at the Polytechnic University of Turin, where he has been actively involved in teaching and research for over two decades. He serves as a Member of the Board of Directors, Member of the GEDI Observatory for Gender Equality, Diversity and Inclusion, and Member of the Permanent University Observatory for monitoring the academic supply chain. His research interests span across channel decoders, circuits for communications, cryptography, deep learning, digital integrated circuits, field programmable gate arrays (FPGA), and hardware design. His work focuses on VLSI architectures for image and video coding, digital architectures for error correcting codes, application specific approximate computing, VLSI architectures for machine learning, digital architectures for bio-inspired processing, digital architectures for post-quantum cryptography, bio-inspired electronics for robotics and biomedical applications, RISC-V extensions and hardware accelerators, and circuit architectures for efficient machine learning and artificial intelligence. His recent publications (2025) demonstrate a strong focus on RISC-V architecture, particularly in the context of cryptographic implementations, hardware security, and post-quantum cryptography. His research group VLSILAB is actively engaged in cutting-edge research in hardware security, efficient processor design, and specialized computing architectures. Among his notable recognitions are the Premio Francesco Carassa awarded by the Telecommunications and Information Technologies Group Association (gtti) in 2010, and his recognition as a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) since 2007. He also serves as an Associate Editor for several prestigious journals including ELECTRONICS (2019-present), IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS (2015-2019), and IET CIRCUITS, DEVICES & SYSTEMS (2013-2016). Professor Masera has advised numerous PhD students working on advanced topics in VLSI design, post-quantum cryptography, hardware accelerators, and machine learning implementations. His current research projects include ISOLDE (2023-2026) and TRISTAN (2022-2025), both EU-funded projects focused on RISC-V technology and domain-specific ecosystems. He leads the VLSILAB research group at the Department of Electronics and Telecommunications, which focuses on cutting-edge research in VLSI architectures, hardware security, and specialized computing systems. The group collaborates with industry partners and participates in major European research initiatives.

• Digital Circuits and Systems
• Energy-Efficient Circuits and Systems
• Embedded Systems
• +۷ مورد دیگر

Massimo Poncino is a Full Professor at the Department of Control and Computer Science (DAUIN) within the Faculty of Engineering at Politecnico di Torino. He serves as Scientific Advisor for the STMicroelectronics partnership and coordinates basic engineering subjects. A Senior Member of IEEE since 2012 and Fellow since 2012, he has served on editorial boards for IEEE Transactions on Computer-Aided Design, IEEE Design & Test of Computers, and ACM Transactions on Design Automation. Education: Laurea in Electronic Engineering (1989) and PhD in Computer and Systems Engineering (1993) from Politecnico di Torino Academic Career: Visiting Scientist University of Colorado (1993-1994), Researcher at Politecnico di Torino (1995-2001), Associate Professor at University of Verona (2001-2004), Full Professor at Politecnico di Torino (2006-present) His research focuses on energy-efficient digital systems , including design automation of SoCs, hardware-aware AI, battery management, cyber-physical systems, and embedded systems. Recent publications highlight advancements in digital twins for batteries , low-power neural network deployment , and IoT privacy . Scientific Awards: Recognition of Service Award - ACM (2013) Certificate of Appreciation - IEEE Circuits and Systems Society (2006, 2008, 2009) IEEE Fellow (2012-) Research Involvement: EU H2020, VI/VII Framework Programs evaluator Scientific Director for projects: Approxim@ction, EMBAI, DISLO-MAN, DAMASCO Member of EDA research group Teaching: Course director for Energy Management for IoT (2019-2025) Lecturer for Computer Science courses (2003-2025)

Marco Aldinucciمشاهده پروفایل

استاد

• Parallel Computing
• High-Performance Computing (HPC)
• Cloud Engineering
• +۷ مورد دیگر

Marco Aldinucci is a Full Professor and Head of the Parallel Computing group at the University of Torino's Computer Science Department. He leads the HPC Key Technologies and Tools (HPC-KTT) national lab under CINI, involving 38 Italian universities. His expertise spans parallel programming models, HPC systems, federated learning, and energy-efficient computing. Aldinucci has secured over €10M in EU research funding, contributed to frameworks like Fastflow and Streamflow, and pioneered initiatives like the HPC4AI lab and the CINI HPC-KTT lab. His research focuses on advancing exascale computing, cloud-HPC integration, and AI-driven medical solutions. Notable projects include the Gaia AVU-GSR solver for exascale systems and the DeepHealth Toolkit for medical AI. He has held governance roles in EuroHPC and chairs the Observatory on Trends and Applications of Supercomputing in Italy. Aldinucci’s publications (150+) address parallel algorithms, distributed learning, and sustainable HPC infrastructure. His work has been recognized with awards from HPC Advisory Council, NVIDIA, IBM, and Autodesk. Current initiatives include the Software & Integration lab at the Italian National HPC Centre (ICSC) and leadership in the OpenScience working group at Torino. His advising includes Iacopo Colonelli, whose thesis won CINI’s 2023 best award. He actively engages in EU projects, workflow systems, and standards for hybrid computing environments. Aldinucci’s labs and collaborations drive innovations in HPC portability, energy efficiency, and AI scalability.

• Logic-in-memory
• Machine learning
• Nanocomputing
• +۷ مورد دیگر

Marco Vacca is an Associate Professor in the Department of Electronics and Telecommunications (DET) at Politecnico di Torino and a member of the Interdepartmental Center PIC4SeR - PoliTO Interdepartmental Centre for Service Robotics. His work bridges electronics, nanotechnology, and computing architecture with a focus on innovative solutions to the memory wall problem. His research spans Logic-in-memory computing, Machine learning hardware acceleration, and Nanocomputing with specific emphasis on circuit architectures for probabilistic computing, magnetic devices, hybrid technologies integration, and CAD tools for emerging technologies. Dr. Vacca leads research in RISC-V extensions, hardware accelerators for AI, and autonomous robot systems for agricultural applications through the VLSILAB research group. Recent publications reveal a strong trend toward solving fundamental computing challenges through nanoscale innovations, particularly in memory-centric architectures, molecular field-coupled computing, and novel transistor technologies. His work demonstrates how logic-in-memory approaches can overcome traditional von Neumann limitations while improving energy efficiency for AI workloads. Editorial board member of ELECTRONICS (2021-2023) Program committee member for Design, Automation and Test in Europe Conference (DATE) 2020-2021 Dr. Vacca supervises PhD student Alessandro Varaldi working on 'Hardware AI Accelerators for Automotive Applications' and has led significant research projects including 'Device for Storage and Processing Data and Related Method' (2020-2021) and 'Quantum Computing and Quantum Communication: State of the Art and Applications in the Telco Sector' (2020). His grant portfolio shows strong industry and competitive funding support. As a core member of the VLSILAB research group, Dr. Vacca contributes to advancing VLSI theory and design applications with particular focus on implementing Big Data, Machine Learning, and Neural Networks in specialized hardware architectures that push the boundaries of conventional computing.

Luca Crocettiمشاهده پروفایل

استادیار

• Cybersecurity in Automotive Systems
• Embedded Systems Design
• VLSI Systems for Space Applications
• +۳ مورد دیگر

Luca Crocetti is an Assistant Professor at the Department of Information Engineering (DII) of the University of Pisa. His research focuses on hardware security, embedded systems, and VLSI design for applications in Automotive, Space, IoT, and High-Performance Computing. He specializes in cybersecurity modules for automotive systems, space-grade FPGAs, and digital signal processing in satellite communications. His teaching includes electronics laboratory practices and cybersecurity principles, with a recent course on hardware's role in security for the Ph.D. program in Information Engineering. He has authored over 20 publications and holds 3 patents (1 national, 2 international), with notable work on cryptographic cores, secure boot mechanisms, and automotive cybersecurity. His contributions span efficient hardware implementations of AES, SHA-3, and other cryptographic algorithms, emphasizing compliance with standards like CCSDS for space applications. His research trends highlight a focus on hardware-efficient architectures, modular design for scalability, and robust security protocols for trusted environments. Notable publications address cryptographic co-processors for the European Processor Initiative, PUF-based security for RISC-V, and FPGA-based RNGs. While no formal awards are listed, his active role in cutting-edge cybersecurity projects underscores his contributions to embedded and space system security. His teaching and research emphasize hands-on lab experiences and real-world applications of hardware security principles.

Federico Reghenzaniمشاهده پروفایل

استادیار

• Computer Science
• Embedded Systems
• Fault Tolerance
• +۳ مورد دیگر

Federico Reghenzani is an Assistant Professor at Politecnico di Milano in the Department of Electronics, Information and Bioengineering. His research focuses on computer science, embedded systems, fault tolerance, high-performance computing, real-time systems, and compiler technology. He leads the HEAP Lab where his team investigates reliability engineering and hardware-software co-design for safety-critical applications. Reghenzani's research examines software-based approaches to hardware fault tolerance, compiler technologies for reliability enhancement, and resource management in high-performance computing environments. His work has significant applications in aerospace systems, real-time embedded platforms, and next-generation computing architectures. His publications demonstrate a consistent focus on improving system reliability through compiler techniques, fault injection methodologies, and hardware-software co-design. The research spans theoretical frameworks, practical implementations, and experimental validation across diverse computing environments.