Dr. Alessandro Ottaviano is a Researcher affiliated with the Department of Digital Integrated Circuits and Systems at ETH Zürich. His work focuses on advanced computer architecture and embedded systems, particularly in the domains of RISC-V processors, real-time systems, and heterogeneous computing. He contributes to the design of time-predictable virtual memory solutions, mixed-criticality systems, and energy-efficient hardware-software interfaces. Key research areas include modular processor architectures, hardware monitoring for safety-critical applications, and power management in high-performance computing (HPC) systems. His recent projects involve developing controllers for 2.5D systems-in-package and creating open-source networking solutions for mixed-criticality environments. Ottaviano’s work often emphasizes open-source hardware design and scalable system-level approaches to address challenges in autonomous systems and edge computing. He collaborates on advancements in interrupt handling for virtualized systems, peripheral event linking for IoT devices, and FPGA-based thermal emulation for many-core processors. His research bridges theoretical computer architecture principles with practical implementations in embedded and real-time systems.
Melissa C. Smith is a Professor of Electrical and Computer Engineering and Associate Dean for Graduate Studies at Clemson University. She holds a Ph.D. from the University of Tennessee and degrees from Florida State University. Her research focuses on machine learning, reconfigurable computing, and high-performance systems, with applications in embedded systems and interdisciplinary scientific advancements. Before joining Clemson in 2006, she was a research associate at Oak Ridge National Laboratory (ORNL), contributing to projects like the Spallation Neutron Source and PHENIX experiments. Education: Ph.D., Electrical and Computer Engineering, University of Tennessee M.S., Electrical Engineering, Florida State University B.S., Electrical Engineering, Florida State University Research Interests: Machine Learning and AI High-Performance and Reconfigurable Computing System Performance Modeling Embedded Systems Articles Summary: Her recent work spans machine learning applications, GPU/FPGA architectures, speech enhancement, and medical systems. Key themes include optimizing heterogeneous computing for real-time and scientific workloads, and advancing interdisciplinary solutions through architecture-application co-design. Lab & Collaborations: Leads the Future Computing Technologies Lab and collaborates with ORNL and national labs on projects like GEMmaker and HPC-enabled medical systems.
Caroline Trippel is an Assistant Professor in the Departments of Computer Science and Electrical Engineering at Stanford University. Her research focuses on ensuring correctness and security in computer systems through formal methods, with particular emphasis on hardware verification, memory consistency models, and mitigating vulnerabilities like Spectre/Meltdown. She previously worked at Facebook’s FAIR SysML group before joining Stanford. Education: PhD in Computer Science, Princeton University BS in Computer Engineering, Purdue University Her work has influenced the RISC-V ISA memory consistency model and produced tools like CheckMate, which automatically synthesizes hardware exploits for security verification. She explores privacy-preserving ML, ML-driven hardware optimizations (e.g., neural recommendation), and datacenter reliability. Her research has earned awards including the 2020 ACM SIGARCH Dissertation Award and NVIDIA Fellowship. Key contributions include: Formal analysis of RISC-V memory models Exploitation synthesis frameworks (CheckMate) Hardware-software contracts for security Defenses against microarchitectural side-channel attacks Current projects include: VeriCoder: LLM-enhanced RTL code verification Multi-μPATH synthesis for security validation Near-data processing (RecSSD) for recommendation systems
Luca Carloni is a Professor of Computer Science and Department Chair at Columbia University's Columbia Engineering. He leads the System-Level Design Group, focusing on heterogeneous system-on-chip (SoC) architectures, networks-on-chip (NoC), and embedded systems. Carloni holds a Laurea Summa Cum Laude in Electronics Engineering from the University of Bologna and a PhD in Electrical Engineering and Computer Sciences from UC Berkeley. His work emphasizes specialized hardware design, energy-efficient computing, and FPGA-based prototyping. Research interests include system-level design methodologies for SoCs, embedded accelerators, and quantum computing hardware. He has pioneered frameworks like Embedded Scalable Platforms (ESP) and tools like MosaicSim for rapid SoC prototyping. Carloni has received numerous awards, including the NSF CAREER Award (2006), IEEE Fellow (2017), and multiple best paper awards at DATE and CloudCom conferences. He has served on editorial boards of IEEE Transactions on CAD and ACM Transactions on Embedded Computing , and chaired key conferences like EMSOFT and ESWeek. His research addresses challenges in heterogeneous architectures, power management, and the intersection of machine learning with embedded systems. Current projects explore quantum control systems, brain-computer interfaces, and energy-efficient datacenter computing.
Eleonora Vacca is a PhD student and Research Fellow in the Department of Automatic Control and Computer Science (DAUIN) at the Polytechnic University of Turin. She holds a B.S. in Electronic Engineering from the University of Palermo (2018) and an M.S. in Electronic Engineering-Embedded Systems from Politecnico di Torino (2021). Her research focuses on digital hardware design, reliability engineering, reconfigurable devices, and AI applications in aerospace and safety-critical systems. She is a member of the Aerospace and Safety Computing Lab and the CAD - Electronic CAD & Reliability Group (DAUIN). Her work addresses challenges such as radiation effects mitigation in space missions, fault-tolerant AI accelerators, and real-time anomaly detection in satellite telemetry. She has contributed to projects like the RAMSES CubeSat-1 Development (2025-2026), funded by commercial contracts. In 2024, she won the Best Student Paper Award at the NEWCAS Conference for her research on radiation effects in space missions. Vacca collaborates on teaching, including assisting in the course 'Electronic Calculators' for Computer Engineering students. Her recent publications explore AI resilience in RISC-V ecosystems, radiation environment analysis for space missions, and gesture recognition systems for smart cities. She actively contributes to conferences such as the ACM International Conference on Computing Frontiers and the IEEE International Smart Cities Conference.
David Wentzlaff is a Professor of Electrical and Computer Engineering at Princeton University, with associated faculty roles in Computer Science and the High Meadows Environmental Institute (HMEI). He leads research in computing architecture, green computing, and sustainable system design. As Director of Undergraduate Studies, he shapes educational programs in his field. Education: Ph.D., Electrical Engineering, MIT (2012) M.S., Electrical Engineering and Computer Science, MIT (2002) B.S., Electrical Engineering, University of Illinois at Urbana-Champaign (2000) Research Focus: Future Computing Systems: Designing manycore architectures, cloud computing infrastructure, and chiplet-based systems for exascale computing. Sustainability: Developing energy-efficient hardware, recyclable computing systems, and eco-friendly decommissioning strategies. Hardware-Software Co-Design: Exploring FPGA integration, in-memory computing, and parallel processing frameworks. Advising & Grants: Advises 8 current graduate students, focusing on topics like chiplet design, neural acceleration, and sustainable computing. Recipient of NSF grants for projects like OpenPiton (open-source manycore research platform) and CAREER awards for energy-efficient architectures. Labs & Collaborations: Leads the Wentzlaff Research Group at Princeton. Develops open-source frameworks like PRGA (FPGA prototyping) and OpenPiton (manycore processor).
Dr. Andrea Bastoni is a Postdoctoral Researcher and Research Fellow at the Chair of Cyber-Physical Systems in Production Engineering at Technical University of Munich (TUM), Faculty of Mechanical Engineering. He is also the CTO and co-founder of Minerva Systems , developing operating system solutions for AI-ready embedded applications. His expertise spans real-time operating systems, cyber-physical systems, and predictable system design for heterogeneous platforms. His research focuses on enhancing predictability of memory hierarchies in complex SoCs through techniques like memory bandwidth regulation and cache partitioning. This work has industrial applications in safety-critical domains such as avionics and railways, where he contributes to certifiable hypervisors and operating systems. As former Software Architect of the PikeOS hypervisor at SYSGO GmbH (2012-2020), he specialized in DO-178C, IEC 61508, and EN 50128 standards. His academic background includes a Ph.D. in Computer Engineering from the University of Rome Tor Vergata (2007-2011), where he developed LITMUS^RT as part of UNC's Real-Time Systems Group during a visiting researcher period (2009-2010). His publications reflect ongoing work on Multicore Real-Time Scheduling , Mixed-Criticality Task Isolation, and Arm DynamIQ shared unit analysis. He actively participates in program committees for conferences like RTSS, DSN, and DATE.
Chester Rebeiro is an Associate Professor at the Department of Computer Science and Engineering within the Indian Institute of Technology Madras . His work spans hardware and software security with a focus on cryptographic implementations and microarchitectural vulnerabilities. Research interests include hardware security, applied cryptography, side channel analysis, and operating system security. He develops frameworks for automatic vulnerability detection and mitigation in cryptographic systems. Editorial Board: Associate Editor at Journal of Hardware and Systems Security (Springer, 2021-2024) Conference Leadership: General Co-Chair for SPACE 2024, Program Co-Chair for ATS 2024, and Program Co-Chair for INDOCRYPT 2023 Professional Activities: Organizer of e-CTF Embedded Capture The Flag and contributor to cybersecurity workshops across India and abroad Scientific contributions highlight two major awards: a Distinguished Paper Award at USENIX Security 2024 and a Best Paper Award at IEEE HOST 2020. His research focuses on practical security solutions for processors and cryptographic systems. Advising includes mentoring 11 PhD students and 7 MS by Research candidates, with notable co-guided projects in fault attack detection and side-channel mitigation. He actively contributes to educational initiatives through courses on Secure Processor Microarchitecture and Operating Systems.
Prof. Daniel Große serves as Professor at the Institute for Complex Systems (ICS) within Johannes Kepler University Linz, Austria, while maintaining a dual affiliation with the German Research Center for Artificial Intelligence (DFKI) in Bremen. His research centers on Electronic Design Automation (EDA), specializing in verification, debugging, and synthesis of complex hardware/software systems through advanced virtual prototyping techniques. His primary research domains include Formal Verification , Hardware Verification , and Virtual Prototyping , with significant contributions to RISC-V architecture development and embedded systems validation. Current projects like PaSVer (automotive electronics), AUTOASSERT (analog-digital verification), and VerSys (RISC-V software platforms) demonstrate his focus on bridging simulation and formal methods for safety-critical applications. Recent publications reveal accelerating trends in metamorphic testing for embedded graphics libraries and RISC-V vector extensions, alongside innovations in waveform analysis tools like Surfer. His work increasingly integrates AI-assisted verification while maintaining rigorous formal methods foundations. Prof. Große actively supervises student research, having guided Lucas Klemmer's PhD thesis and nine Bachelor theses on topics ranging from RISC-V processor design to transaction visualization. His projects including SATiSFy (autonomous vehicle security) and CONVERS (complex system design automation) secure substantial research funding from academic and industry partners. He leads the Institute for Complex Systems' development of open-source tools such as RISC-V VP++ and contributes to international standards through program committee roles at DATE, ICCAD, and RISC-V Summit Europe.
Luciano Lavagno is a Full Professor at the Department of Electronics and Telecommunications, Polytechnic University of Turin, with over two decades of academic and research contributions. His work bridges hardware acceleration, low-power electronics, and intelligent system design. Research Focus: Hardware-accelerated machine learning, high-level synthesis (HLS) for FPGA/ASIC, heterogeneous CPU/GPU/FPGA platforms Key Projects: SPACE (predictable acceleration), REBECCA (secure AI acceleration), HPC-National Center (quantum computing), and oral history preservation via "Ti racconto una storia" initiative His recent publications analyze CNN inference optimization, subgraph isomorphism, and superword-level parallelism exploitation. Lavagno supervises multiple PhD students working on FPGA acceleration, neural network hardware, and embedded systems. As Principal Investigator for national and EU-funded projects (PRIN, JTI-ECSEL, PNRR), he drives advancements in sustainable computing infrastructure. His patented technologies include MIx&Latch timing methodology, capacitive sensing innovations, and 5G acceleration frameworks.
Prof. Dr.-Ing. Jürgen Teich is a full Professor and Chair for Hardware-Software Co-Design at the Department of Computer Science, Friedrich Alexander University Erlangen-Nuremberg (FAU). He serves as Head of Department Computer Science and Vice Dean of the Technical Faculty since August 2024, and has been Speaker of the FAU Research Center Embedded System Initiative (FAU ESI) since 2023. His educational background includes: Diploma degree in Electrical Engineering, University of Kaiserslautern (1989) Dr.-Ing. degree in Electrical Engineering, University of Saarland (1993) Habilitation (PD Dr.-Ing.) entitled "Synthesis and Optimization of Digital Hardware/Software Systems" (1996) Prof. Teich's research focuses on Embedded Systems , Invasive Computing , Hardware-Software Co-Design , and Reconfigurable Computing . His work spans from theoretical foundations to practical implementations, with particular emphasis on resource-constrained systems, many-core architectures, and energy-efficient computing. He has pioneered research in invasive computing paradigms that enable more efficient use of many-core processors by allowing applications to dynamically claim resources. His recent publications reveal a strong trend toward energy-efficient AI deployment on embedded devices , security of embedded systems , and novel memory technologies . There's a clear focus on practical implementations of machine learning on microcontrollers (TinyML), hardware acceleration for data processing, and innovative approaches to power management in self-powered systems. Among his notable scientific awards are: IEEE Fellow (since 2018) Member of Academia Europaea, Section Informatics (since 2011) Member of the National Academy of Science and Engineering (acatech) (since 2018) Member of the German Society of Humboldtians (since 2021) Prof. Teich has been Principal Investigator for numerous DFG-funded projects including SFB/Transregio 89 "Invasive Computing" (2010-2022), SFB 694, and multiple priority programs. He has coordinated large collaborative research efforts across Germany and internationally, with significant funding from DFG and other sources. His research group has produced influential work in embedded systems design and co-design methodologies. He leads the Hardware-Software Co-Design research group at FAU, which focuses on innovative approaches to embedded system design, invasive computing architectures, and efficient implementation of machine learning on resource-constrained devices. The group maintains strong collaborations with industry partners including Intel, Xilinx, and automotive companies.
Maurizio Martina is a Full Professor at the Department of Electronics and Telecommunications (DET) of Politecnico di Torino. He is a member of the Interdepartmental Center PEIC - Power Electronics Innovation Center and serves as an Associate Editor for the IEEE Transactions on Circuits and Systems I (2018-2023). His research focuses include: Digital circuits and signal processing Machine learning hardware architectures RISC-V extensions and post-quantum cryptography VLSI design for edge computing and IoT Recent publications emphasize cryptographic hardware implementations (CHIMERA, Keccak co-processors), RISC-V integration methodologies, and privacy-preserving neural network frameworks. His work spans VLSI architectures for video processing, bio-inspired electronics, and error correcting codes, with applications in cybersecurity, robotics, and biomedical systems. Scientific Recognition : Premio Nazionale Innovazione (2013) Premio dei Premi (2014) He supervises 12 PhD students across cycles 35-40 in Electrical, Electronics and Communications Engineering, including: Valeria Piscopo (2024-in progress) Alessandra Dolmeta (2022-in progress) Luigi Giuffrida (2022-in progress) Walid Walid (2019-2023) As part of the VLSILAB Group , his research explores hardware accelerators for machine learning, post-quantum cryptography on RISC-V, and bio-inspired embedded systems. Teaching activities include courses on Integrated Systems Architecture and Hardware & Wireless Security at Politecnico di Torino and Università di Pavia.
Dominique Devriese is a professor at the Department of Computer Science, KU Leuven, and a member of the DistriNet research group. His work bridges computer security, programming languages, and formal verification. Research interests: Functional Programming, Object Capabilities, Secure Compilation, Dependently-typed Programming, Modal Type Theory Teaching: Formal Systems, Object-Oriented Programming, CyberSecurity, Secure Software His research focuses on rigorous software systems security through capability machines and secure compilation techniques. He actively contributes to formal verification using Agda and Haskell, with recent work on multimode type theory and effect parametricity. Key publication trends include: multimode/presheaf type theory, capability-based security models, formal verification of hardware/software abstractions, and parametricity applications in programming languages. Contact: Email: dominique.devriese@kuleuven.be ORCID: 0000-0002-3862-6856
Simon Moore is a Professor of Computer Engineering at the University of Cambridge's Department of Computer Science and Technology. He leads the Computer Architecture research group, focusing on secure processors and subsystems, particularly the CHERI project. His work emphasizes formal verification, hardware-software co-design, and scalable security solutions. He is a Fellow and Director of Studies at Trinity Hall, overseeing undergraduate admissions and mentoring in Computer Science. Research Interests: Moore's primary focus is the CHERI secure processor architecture, integrating RISC-V cores with formal verification. His work spans secure hardware design, memory safety, and embedded systems. Notable contributions include the CHERI-RISC-V microarchitecture, CheriABI, and formal verification frameworks. Key Projects: CHERI, CheriBSD, Morello (ARM collaboration) Recent Achievements: Test of Time Award (IEEE Security & Privacy 2025), finalist for Bhattacharyya Award (2022) Grants: Innovate UK Digital Security by Design, DARPA Mission Oriented Resilient Clouds Publications: Over 200 papers on secure architectures, including influential work on CHERI's capability model, formal verification, and hardware security. Recent focus areas include temporal memory safety, embedded system security, and GPU-based capability systems. Labs/Teams: Directs the Computer Architecture Group and collaborates with industry partners like ARM and Microsoft on CHERI implementations.
Dr Graeme Bragg is a Senior Teaching Fellow at the University of Southampton within the Department of Electronics and Computer Science . His work spans teaching, research, and technical development with a focus on event-driven computing, bioinformatics, and computational modeling. He actively supervises PhD students and collaborates on interdisciplinary projects. Research Interests: Parallel computing, event-driven systems, genotype imputation, Petri net simulations, subglacial hydrology modeling Teaching: Specializes in hardware description languages and computational methods for engineering students Technical Expertise: RISC-V architecture, FPGA acceleration, bespoke compute fabric development His recent publications demonstrate expertise in applying event-driven computing to diverse problems including: 2025: Automated marking systems for SystemVerilog labs 2025: Seasonal dynamics in subglacial hydrology 2023: Genotype imputation using custom hardware 2022: Optimization algorithms and graph analysis Current research explores: Custom RISC-V FPGA clusters for bioinformatics Event-triggered systems for scientific simulations Parallel computing solutions for molecular modeling Contact: gmb@ecs.soton.ac.uk | +44 23 8059 2784
