جست‌وجوی استاد و پژوهشگر

• AI Safety
• Reliability of AI Systems
• Testing of Digital Circuits
• +۱ مورد دیگر

Annachiara Ruospo is a Assistant Professor at the Department of Control and Computer Engineering (DAUIN) at Politecnico di Torino. She holds a Fixed-Term Researcher position under Italian Law 240/10, art.24-A, and is actively involved in teaching and research projects. Research Interests : AI Safety, Reliability of AI Systems, Testing of Digital Circuits, Statistical Reliability Investigations. Her recent research focuses on hardware reliability for AI systems , including fault injection methodologies, quantized neural networks, and side-channel vulnerabilities. She collaborates on EU-funded projects like REACT and commercial contracts such as TC4xx NVM Test Strategies . Scientific Awards : None explicitly mentioned. Supervised Students : Antonio Porsia (PhD candidate, Reliability and Security of AI-Based Systems) and Vittorio Turco (PhD candidate, Reliability Evaluation and Hardening of AI Accelerators). She contributes to AI hardware security through patents like A Shannon-Hartley-Based Approach to Measure the Criticality of Synaptic Weights and actively participates in conferences such as the IEEE Latin American Test Symposium and IEEE VLSI Test Symposium .

Marc Reichenbachمشاهده پروفایل

استاد

• Integrated Circuits
• Embedded Systems
• VLSI Design
• +۷ مورد دیگر

Prof. Dr.-Ing. Marc Reichenbach serves as the Chair of Integrated Systems at the Institute for Applied Microelectronics and Data Technology at the University of Rostock. His office is located at Albert-Einstein-Straße 26, 18059 Rostock, Room 102 (1st floor), with contact information including telephone (0381) 498 7270 and email marc.reichenbach@uni-rostock.de. Professor Reichenbach's research focuses on the intersection of hardware design and artificial intelligence, with particular expertise in memory technologies and computing architectures. His work spans several key areas: Development of specialized computer architectures for deep learning applications Advanced VLSI design and CPU architecture Emerging memory technologies, particularly RRAM (Resistive Random-Access Memory) FPGA-based acceleration systems Hardware implementations for neural networks and AI applications Analysis of Professor Reichenbach's recent publications (2023-2025) reveals a strong focus on memory computing technologies, particularly RRAM-based systems. His work demonstrates expertise across multiple dimensions of computer architecture including ASIC design, FPGA acceleration, and novel memory systems. The publications show a clear trajectory toward implementing AI and machine learning capabilities directly in hardware, with applications ranging from edge computing to satellite systems. A significant portion of his recent work addresses the challenges of implementing neural networks using emerging memory technologies, focusing on efficiency, reliability, and performance optimization. Professor Reichenbach teaches several advanced courses including: Computer architectures for deep learning applications Project seminar Embedded Systems Advanced VLSI Design (Advanced CPU Design) His research group appears to be actively engaged in several cutting-edge projects related to hardware acceleration for AI applications, memory computing, and embedded systems design. The group collaborates on projects involving digital twins for hardware systems, real-time operating systems for heterogeneous architectures, and specialized computing systems for various applications from medical devices to drone technology.

David Atienzaمشاهده پروفایل

استاد

• Embedded Systems
• Low-Power Computing
• Edge AI
• +۳ مورد دیگر

David Atienza is a Professor in the Department of Electrical Engineering at the School of Engineering, Swiss Federal Institute of Technology in Lausanne (EPFL), renowned for pioneering embedded systems education and research in ultra-low power computing. His innovative teaching methods, including using Nintendo DS consoles and smartphones to teach embedded systems, earned him the 2015 EPFL Teaching Award in Electrical Engineering. His research focuses on Embedded Systems , Edge AI , and Wearable Healthcare , with breakthroughs in energy-efficient hardware-software co-design for biomedical applications. Key contributions include open-source platforms like X-HEEP and HEEPocrates for ultra-low power edge computing, and frameworks like SzCORE for seizure detection benchmarking. His work bridges computer architecture with real-world healthcare challenges, emphasizing privacy-preserving algorithms and sustainable computing. Recent publications (2023-2025) reveal a dominant trend toward biomedical edge AI and sustainable computing , with 70% of articles targeting healthcare wearables (seizure detection, cough monitoring) and 30% addressing energy efficiency in data centers and edge devices. His research consistently integrates open-hardware principles (RISC-V) with novel algorithm-hardware co-design. Awards include: 2015 EPFL Teaching Award in Electrical Engineering section While specific advising details are unreported, his extensive publication record and leadership in multi-partner projects like Sustainable Textile Electronics (STELEC) indicate active graduate supervision and significant research funding. His group develops open-source hardware frameworks used globally in academia and industry. He leads the Embedded Systems Laboratory at EPFL, driving projects in ultra-low power RISC-V architectures, biomedical wearables, and sustainable computing. Current initiatives include carbon-aware data center frameworks and multi-modal health monitoring systems deployable on commercial wearables.

• Embedded Systems
• Compilers
• Hardware-Software Co-Design
• +۵ مورد دیگر

Prof. Dr. rer. nat. Rainer Leupers is a faculty member at RWTH Aachen University, chairing the Department of Software for Systems on Silicon. His research focuses on embedded systems, hardware-software co-design, virtual prototyping, and security in computing-in-memory architectures. He has published extensively on RRAM accelerators, logic locking, and neuromorphic security. Chair of Software for Systems on Silicon Research in hardware security and deep learning accelerators Recent publications on cross-tool virtual frameworks and thermal side-channel attacks His work bridges system-level modeling with practical security implementations, emphasizing reliability and performance in heterogeneous computing environments. Key trends in his 2025-2023 articles include compute-in-memory optimization, neural network inference efficiency, and security vulnerabilities in emerging hardware. Awards and formal recognitions are not explicitly detailed in the provided materials. He has not directly mentioned advising students or research grants in the given text fragments. The chair's contact information includes an office at ICT Cube 1, Electrical Engineering, Aachen, with direct email and website links.

• Cybersecurity
• Machine Learning for Security
• IoT Security
• +۵ مورد دیگر

Dr Raja Akrom is a Senior Lecturer in the Department of Computer Science , School of Natural and Computing Sciences , University of Aberdeen since July 2020. Previously, he held research positions at Royal Holloway, University of London (Post Doctoral Research Assistant), University of Waikato (Research Fellow), and Edinburgh Napier University (Senior Research Fellow). PhD in Information Security from Royal Holloway, University of London MSc in Information Security and Computer Science from Royal Holloway and University of Agriculture, Faisalabad BSc in Mathematics and Physics from University of the Punjab His research focuses on user-centric applied security and privacy architectures , data ownership in heterogeneous computing , security for machine learning , and security in emerging technologies such as blockchain, UAVs/drones, and autonomous vehicles. Key technical interests include smart card security, cryptographic protocols, IoT security, and Trusted Execution Environments. The article list reveals expertise in: edge computing security (DECML 2025), medical AI applications (2024), embedded device ownership (CO-TSM 2024), NFC transaction security (2024), and malware detection with ML (2024). Earlier work explored UAV security , blockchain governance , and smart card protocols . Currently teaching courses in Operating Systems , Secure Software Design , and Enterprise Security Architecture . Supervises postgraduate MSc Cybersecurity program.

• Information Security
• Cybersecurity
• Smart Card Security
• +۱۵ مورد دیگر

Konstantinos Markantonakis is a Professor of Information Security in the Department of Information Security at Royal Holloway, University of London, where he also serves as Director of the Smart Card and IoT Security Centre and the Transformative Digital Technologies, Security and Society Catalyst. He is a leading figure in embedded systems and IoT security, with extensive research and consultancy experience. BSc (Hons) in Computer Science, Lancaster University, 1995 MSc in Information Security, Royal Holloway, 1996 PhD in Smart Card Security, Royal Holloway, 2000 MBA in International Management, Royal Holloway, 2005 His research focuses on securing embedded and cyber-physical systems, including smart cards, mobile devices, drones, automotive systems, and IoT. He investigates trusted execution environments, side-channel analysis, secure protocols, and hardware-software binding. His work bridges theoretical security and practical implementation, often uncovering zero-day vulnerabilities in consumer devices. The recent publications highlight a strong trend in trusted computing, remote attestation, secure embedded systems, and privacy-preserving technologies. His research integrates blockchain for secure energy trading, develops frameworks for edge machine learning, and advances forensic techniques for damaged storage media. He also explores covert channels in mobile and cloud environments, demonstrating a deep understanding of both offensive and defensive security. Best Paper Award Markantonakis has led major research projects such as EXFILES (forensic extraction from encrypted smartphones), Future TPM (quantum-resistant trusted modules), and the Academic Centre of Excellence in Cyber Security Research. He has supervised numerous PhD students and delivered keynotes at international conferences. His consultancy work has impacted financial institutions, transport operators, and mobile platform security. He leads the Smart Card and IoT Security Centre, a research hub focusing on practical security for connected devices. The centre conducts cutting-edge research in side-channel attacks, secure application execution, and forensic analysis, contributing significantly to both academic and industrial advancements in cybersecurity.

• Reliable and Fault-Tolerant Computing
• RISC-V Architecture
• FPGA-Based Systems
• +۱۲ مورد دیگر

Sarah Azimi is a fixed-term researcher at the Department of Control and Computer Science (DAUIN) within the College of Computer, Film and Mechatronics Engineering at Politecnico di Torino. She actively contributes to research and teaching in the domains of reliable computing, reconfigurable systems, and AI applications for space and smart city security. Research Interests: Reliability and fault tolerance in safety-critical and space systems RISC-V and FPGA-based architectures High-performance computing (HPC) and reconfigurable computing AI resilience and real-time gesture recognition for public safety Radiation effects and hardening techniques for aerospace applications Publication Trends: Her recent publications focus on RISC-V reliability, radiation effects in space missions, AI resilience in reconfigurable platforms, and smart city security through gesture recognition. Her work spans both journal and conference venues, emphasizing practical and mission-tailored solutions in embedded and aerospace computing. Scientific Awards: No awards explicitly mentioned in the provided text. Advising and Grants: Sarah Azimi supervises multiple PhD students including Federico Buccellato, Aobo Cui, and Giorgio Cora. She leads the competitive research project Safe Smart City: Detecting Violence and Requests for Help in Real Time Through Video Surveillance Devices (2024). She is also a member of the RAMSES CubeSat-1 Development project (2025–2026) and led the commercial research project on the Rempro fault-tolerant processor (2022–2023). Labs and Teams: She is a key member of the CAD - Electronic CAD & Reliability Group (DAUIN) at Politecnico di Torino, contributing to cutting-edge research in electronic design automation and system reliability for aerospace and terrestrial applications.

Tanvir Arafinمشاهده پروفایل

استادیار

• Hardware Security
• Trusted Computing
• IoT Security
• +۴ مورد دیگر

Tanvir Arafin serves as an Assistant Professor in the Department of Cyber Security Engineering at George Mason University, where his research focuses on hardware security and trust mechanisms for emerging computing platforms. With publications in premier venues including IEEE Transactions on Very Large Scale Integration Systems, IEEE Transactions on Computers, and ACM International Conference on Computer-Aided Design, he addresses critical security challenges in next-generation systems through rigorous hardware-software co-design approaches. His research portfolio spans Hardware Security, Trusted Computing, and IoT Security, with specialized expertise in Side-Channel Attacks and Secure Hardware Design. Dr. Arafin investigates electromagnetic side-channel vulnerabilities in O-RAN networks, develops countermeasures for autonomous vehicle cybersecurity, and pioneers RRAM-based security solutions for memory-constrained devices. His work bridges theoretical security models with practical implementations, emphasizing real-world applicability in edge computing environments and autonomous navigation systems. Current projects explore machine learning integration for anomaly detection in connected vehicles and secure acceleration of cryptographic operations. Analysis of Dr. Arafin's 2022-2025 publications reveals strategic focus areas: electromagnetic fingerprinting for radio units in O-RAN (2025), spatial acceleration of Kolmogorov-Arnold Networks (2025), and NTT-based cryptography accelerators (2024). His research demonstrates consistent innovation in securing autonomous navigation systems and edge devices, with emerging work on in-memory computing architectures using resistive memory technologies. Key trends include hardware-centric defense against model inversion attacks, voltage overscaling for lightweight authentication, and robust multi-robot coordination in dynamic environments. Scientific Awards: No scientific awards, fellowships, or medals were documented in the source materials. Dr. Arafin leads significant collaborative research, including the NSF CISE-MSI grant (DP: CNS) for edge-based robust multi-robot systems. His educational initiatives feature Capture-the-Flag competitions targeting underrepresented students in cybersecurity. Current grant activities emphasize practical security solutions for autonomous navigation, multi-robot coordination, and IoT edge devices, with demonstrated focus on translating research into deployable countermeasures for real-world threats in dynamic operational environments.

• Digital Circuits and Systems
• Energy-Efficient Circuits and Systems
• Embedded Systems
• +۷ مورد دیگر

Massimo Poncino is a Full Professor at the Department of Control and Computer Science (DAUIN) within the Faculty of Engineering at Politecnico di Torino. He serves as Scientific Advisor for the STMicroelectronics partnership and coordinates basic engineering subjects. A Senior Member of IEEE since 2012 and Fellow since 2012, he has served on editorial boards for IEEE Transactions on Computer-Aided Design, IEEE Design & Test of Computers, and ACM Transactions on Design Automation. Education: Laurea in Electronic Engineering (1989) and PhD in Computer and Systems Engineering (1993) from Politecnico di Torino Academic Career: Visiting Scientist University of Colorado (1993-1994), Researcher at Politecnico di Torino (1995-2001), Associate Professor at University of Verona (2001-2004), Full Professor at Politecnico di Torino (2006-present) His research focuses on energy-efficient digital systems , including design automation of SoCs, hardware-aware AI, battery management, cyber-physical systems, and embedded systems. Recent publications highlight advancements in digital twins for batteries , low-power neural network deployment , and IoT privacy . Scientific Awards: Recognition of Service Award - ACM (2013) Certificate of Appreciation - IEEE Circuits and Systems Society (2006, 2008, 2009) IEEE Fellow (2012-) Research Involvement: EU H2020, VI/VII Framework Programs evaluator Scientific Director for projects: Approxim@ction, EMBAI, DISLO-MAN, DAMASCO Member of EDA research group Teaching: Course director for Energy Management for IoT (2019-2025) Lecturer for Computer Science courses (2003-2025)

• Computer Architecture
• Embedded Systems
• Machine Learning Accelerators
• +۵ مورد دیگر

Marina Zapater Sancho is a researcher at the Embedded Systems Laboratory (ESL) within the School of Engineering at École Polytechnique Fédérale de Lausanne (EPFL) . She specializes in computer architecture, with a focus on energy-efficient systems, AI accelerators, and memory-centric computing paradigms. Research Interests: Compute-Near-Memory (CnM) : Pioneering architectures like SideDRAM and processing-near-bank designs to reduce energy consumption and latency in DRAM systems. AI Accelerators : Frameworks such as LIONHEART for analog-digital hybrid systems, and Gem5-AcceSys for exploring interconnects in ML accelerators. System Simulation : Contributions to RISC-V full-system simulation validation (gXR5) and component-level calibration methodologies. Her work bridges software and hardware, addressing challenges in heterogeneous systems, thermal management in 2.5D/3D packages, and virtual memory optimization for cache-intensive workloads. Recent trends emphasize energy-proportional computing and edge AI deployment . Grants & Collaborations: Funded by EU H2020 programs and the ACCESS-AI Chip Center (Hong Kong), her research is conducted within the ESL team led by Prof. David Atienza Alonso.

Hamed Nematiمشاهده پروفایل

استادیار

• Security of systems software
• Formal methods and program logics
• Interactive theorem proving
• +۲ مورد دیگر

Hamed Nemati is an Assistant Professor at the Division of Network and Systems Engineering under the School of Electrical Engineering and Computer Science at KTH Royal Institute of Technology in Stockholm, Sweden. He was previously a Visiting Assistant Professor at Stanford University and a Research Group Leader at the Helmholtz Center for Information Security (CISPA) , where he also worked as a PostDoc and Research Fellow. Education : PhD in Computer Science from KTH Royal Institute of Technology Research Interests : Security of systems software, formal methods and program logics, interactive theorem proving, machine code analysis, applied machine learning Current Projects : Systematic verification of multi-language security protocols, hardware-software co-design for Spectre mitigation, capability-based access control models Scientific Awards : WASP (Wallenberg AI, Autonomous Systems and Software Program) faculty member Teaching Activities : Formal Methods in Security (Fall 2020-2023) at CISPA/Saarland University Digital Forensics and Incident Response (EP2780) (Fall 2024) at KTH

Mircea R. Stanمشاهده پروفایل

استاد

• AI Hardware
• Processing in Memory
• Low Power Design
• +۷ مورد دیگر

Mircea R. Stan is a Professor of Electrical and Computer Engineering at the University of Virginia, serving as Director of Computer Engineering and Virginia Microelectronics Consortium (VMEC) Professor. He leads the High-Performance Low-Power (HPLP) lab and is an associate director of the Center for Automata Processing (CAP). His research focuses on AI hardware, Processing in Memory, Low Power Design, Cyber-Physical Systems, and Spintronics. Education: Ph.D. (1996) and M.S. (1994) from UMass Amherst; Diploma (1984) from Politehnica University, Bucharest. Research interests include energy-efficient computing architectures, IoT systems, and emerging technologies like magnetic skyrmions and memristors. He has pioneered work on asynchronous stochastic computing, thermal-aware microarchitecture, and microfluidic cooling for 3D-ICs. Key awards include the 2024 A. Richard Newton Technical Impact Award, 2018 ISCA Influential Paper Award, and IEEE Fellow (2014). He has held editorial roles at IEEE TVLSI, IEEE TNano, and IEEE Design & Test. Notable contributions include the HPLP lab’s advancements in low-power logic computing, the VCRFID framework for Industry 4.0, and thermal-aware design tools like Hot-LEGO and Cool-3D.

Marco Aldinucciمشاهده پروفایل

استاد

• Parallel Computing
• High-Performance Computing (HPC)
• Cloud Engineering
• +۷ مورد دیگر

Marco Aldinucci is a Full Professor and Head of the Parallel Computing group at the University of Torino's Computer Science Department. He leads the HPC Key Technologies and Tools (HPC-KTT) national lab under CINI, involving 38 Italian universities. His expertise spans parallel programming models, HPC systems, federated learning, and energy-efficient computing. Aldinucci has secured over €10M in EU research funding, contributed to frameworks like Fastflow and Streamflow, and pioneered initiatives like the HPC4AI lab and the CINI HPC-KTT lab. His research focuses on advancing exascale computing, cloud-HPC integration, and AI-driven medical solutions. Notable projects include the Gaia AVU-GSR solver for exascale systems and the DeepHealth Toolkit for medical AI. He has held governance roles in EuroHPC and chairs the Observatory on Trends and Applications of Supercomputing in Italy. Aldinucci’s publications (150+) address parallel algorithms, distributed learning, and sustainable HPC infrastructure. His work has been recognized with awards from HPC Advisory Council, NVIDIA, IBM, and Autodesk. Current initiatives include the Software & Integration lab at the Italian National HPC Centre (ICSC) and leadership in the OpenScience working group at Torino. His advising includes Iacopo Colonelli, whose thesis won CINI’s 2023 best award. He actively engages in EU projects, workflow systems, and standards for hybrid computing environments. Aldinucci’s labs and collaborations drive innovations in HPC portability, energy efficiency, and AI scalability.

• Electronic Design Automation (EDA)
• Computer Architecture
• Embedded Systems
• +۵ مورد دیگر

Prof. Wolfgang Ecker is a Professor at the Technical University of Munich (TUM), affiliated with the Chair of Design Automation within the TUM School of Computation, Information and Technology . His research focuses on Electronic Design Automation (EDA), RISC-V processor architectures, and hardware-software co-design. He leads projects advancing EDA tools for embedded systems, neural network acceleration, and formal verification methodologies. Ecker's work bridges machine learning techniques with traditional EDA challenges, addressing topics like energy-efficient AI inference and automated documentation generation. His contributions span compiler optimization, FPGA implementations, and fault analysis in digital systems. Recent research highlights include contributions to the TRISTAN project for RISC-V ecosystem development, model-driven architecture frameworks, and AI-driven timing analysis. He actively collaborates on open-source EDA tools and explores Rust-based embedded systems development. Ecker’s lab emphasizes practical applications in edge computing and automotive microcontroller safety, with a strong emphasis on interdisciplinary collaboration across TUM’s CIT School. His publications (15 most recent listed) reflect a focus on EDA tool innovation, processor design, and leveraging machine learning for hardware optimization. While no specific awards are mentioned, his involvement in ERC-funded projects and leadership in international collaborations underscores his academic impact.

Batuhan Sesliمشاهده پروفایل

پژوهشگر

• Embedded Systems
• Machine Learning Hardware Acceleration
• RISC-V Architecture
• +۳ مورد دیگر

Batuhan Sesli is a Researcher at the Department of Computer Science 12 (Hardware-Software-Co-Design) at Friedrich-Alexander University Erlangen-Nuremberg (FAU), Germany, since July 2024. His work focuses on embedded systems with emphasis on hardware acceleration for machine learning and efficient deployment of TinyML applications on resource-constrained devices. His educational background includes: M.Sc. in Information and Communication Technology from FAU (2022-2024) B.Sc. in Electrical & Electronics Engineering from Istanbul Ozyegin University, Turkey, with a minor in Computer Science (2016-2021) Research interests span acceleration techniques for machine learning workloads via RISC-V ISA extensions and specialized hardware accelerators, efficient deployment of TinyML on low-power devices, and co-design of AI algorithms and hardware. His work optimizes the synergy between algorithmic requirements and hardware capabilities in embedded systems, targeting practical solutions for edge AI applications. His recent DATE 2024 publication on DNN acceleration through weight clustering on RISC-V custom functional units exemplifies the trend toward energy-efficient specialized hardware, reflecting his focus on bridging algorithmic demands with hardware constraints in real-world embedded scenarios. He teaches a tutorial on Embedded Systems for Winter Semester 2024/2025 and offers thesis opportunities in his research domain, though no current open theses are listed.