جست‌وجوی استاد و پژوهشگر

• High-Performance Computing (HPC)
• Artificial Intelligence
• Machine Learning
• +۵ مورد دیگر

Murali Emani is a researcher affiliated with Argonne National Laboratory, IL, USA. His work focuses on High-Performance Computing (HPC), machine learning, and artificial intelligence acceleration. Emani holds a PhD in Computer Science from the University of Edinburgh (2015). He specializes in optimizing large-scale systems, including performance evaluation of AI accelerators, transformer models, and neural architecture search. His research bridges HPC infrastructure with AI applications, addressing challenges in resource allocation, inference efficiency, and cross-architecture benchmarking. Key contributions include frameworks for GPU memory optimization (XUnified) and holistic performance evaluation of large language models across diverse hardware (e.g., BaKlaVa, Centimani). He collaborates extensively with institutions like the University of Chicago, NVIDIA, and MLCommons on initiatives such as DeepSpeed4Science and GenSLMs for genome-scale language models. His work frequently appears in top venues like IPDPS, SC, and Euro-Par. Emani’s research emphasizes practical system-level innovations, with applications spanning bioinformatics (SARS-CoV-2 evolutionary analysis), protein design, and exascale computing. He advocates for FAIR principles in HPC data management and contributes to open benchmarks like MLPerf HPC.

• Computer-Aided Design
• Energy-Efficient Systems
• VLSI Design
• +۳ مورد دیگر

Sarma Vrudhula is a Professor at the School of Computing and Augmented Intelligence, Arizona State University (ASU). He holds a Ph.D. in Electrical Engineering from the University of Southern California (1985). Previously, he was a professor at the University of Arizona and served as the founding director of the NSF UA/ASU Center for Low Power Electronics. He is an IEEE Fellow recognized for contributions to low-power and energy-efficient digital circuit design. Educations: Ph.D. Electrical Engineering, University of Southern California (1985) M.S. Electrical Engineering, University of Southern California (1980) Bachelor's in Mathematics (Computer Science and Mathematical Statistics), University of Waterloo, Canada (1976) Research Interests: His work focuses on design automation, energy management in digital systems, statistical analysis of process variations, threshold logic circuits, and emerging technologies. He has pioneered methodologies for low-power VLSI design, thermal management of multi-core processors, and hardware implementations of threshold logic using spintronic devices. Publications: His recent research includes scalable energy-efficient architectures for AI, in-memory computing, and reconfigurable threshold logic gates. Key topics span energy efficiency in edge computing, neuromorphic systems, and sustainable VLSI design. Awards: IEEE Fellow (2005) Best Paper Award (2008) for macro cell characterization methodology Service & Grants: He led the NSF IUCRC Consortium for Embedded Systems and served on editorial boards. His grants include projects on threshold logic synthesis, energy-aware embedded systems, and hardware acceleration for neural networks. Courses Taught: Algorithmic Foundations of CAD for Digital Systems Computer Architecture Discrete Mathematics for Engineers

Lizhong Chenمشاهده پروفایل

استاد

• Computer Architecture
• Machine Learning Accelerators
• GPU Architecture
• +۶ مورد دیگر

Lizhong Chen is a Professor in the School of Electrical Engineering and Computer Science at Oregon State University and a core AI faculty member in the Collaborative Robotics and Intelligent Systems (CoRIS) Institute. He leads the STAR Lab which focuses on computing systems and AI applications with emphasis on computing efficiency across various computing platforms from embedded devices to supercomputers. Ph.D., Computer Engineering, University of Southern California, 2014 M.S., Electrical Engineering, University of Southern California, 2011 B.S., Electrical Engineering, Zhejiang University, 2009 Chen's research focuses on efficient computer systems (GPUs, accelerators, HPCs, IoT devices) and their applications in machine learning and natural language processing, especially large language models. His work spans machine learning accelerators, GPU architecture, AI-assisted design for computer architecture, and energy-efficient computing systems. He has made significant contributions to NoC (Network-on-Chip) power-gating research and developed the Agate simulator for simulating NoC power-gating. His recent publications (2023-2025) show a strong focus on large language models, particularly for simultaneous translation tasks, Kolmogorov-Arnold networks, and efficient model architectures. His work bridges computer architecture design with AI applications, creating synergies between hardware efficiency and machine learning performance. Scientific Awards: NSF CRII Award (2016) NSF CAREER Award (2018) Best Paper Nomination at IEEE NAS (2018) Best Paper Runner-up Award at HPCA (2020) Chu Kochen Award from Zhejiang University IEEE HPCA Hall of Fame (2020) Chen has served as an Associate Editor of IEEE Transactions on Computers and as program committee member for top computer system and machine learning conferences. He is the founder and organizer of the Annual International Workshop on AIDArc (AI-assisted Design for Architecture). His research is supported by multiple grants from NSF, NIH, Department of Energy, and the Northwest-AI-Hub supported by the CHIPS and Science Act. He teaches courses in computer architecture, high-performance computing, and specialized topics in AI accelerators and GPU architecture. As director of the STAR Lab, Chen leads research on computing efficiency across the spectrum from embedded and mobile devices to supercomputers and data centers. The lab's recent focuses include machine learning accelerators, GPU architecture, applications of AI in architecture designs, and improving the computing efficiency of machine learning and natural language processing models.

Salim Ullahمشاهده پروفایل

پژوهشگر

• Approximate Computing
• FPGA-Based Hardware Accelerators
• Embedded Systems Design
• +۳ مورد دیگر

Salim Ullah is a researcher in the Department of Embedded Systems at Ruhr University Bochum. His work focuses on FPGA-based approximate computing, hardware accelerators, and embedded systems design. He leads the Embedded Systems Team, contributing to advancements in reconfigurable logic and neuromorphic computing. Research Interests: Approximate arithmetic circuits, FPGA design methodologies, neural network implementation on FPGAs Key Projects: AxOCS (approximate operator scaling), AxOMaP (mathematical programming for arithmetic operators), AxOSpike (spiking neural networks for operator design) Publications (2024-2020) highlight innovations in error resilience, quantization techniques, and hardware-software co-design. Collaborations include work on RISC-V emulation (NvMISC), energy-efficient multipliers, and embedded AI acceleration frameworks.

Andrea Albarelliمشاهده پروفایل

دانشیار

• Artificial Intelligence
• Machine Learning
• Computer Vision
• +۳ مورد دیگر

Andrea Albarelli is an Associate Professor at Ca' Foscari University of Venice, affiliated with the Department of Environmental Sciences, Informatics and Statistics. His research focuses on Artificial Intelligence, Machine Learning, and Computer Vision, with a particular emphasis on Explainable AI, Pattern Recognition, and Data Analytics applications. He has contributed to numerous peer-reviewed publications, including studies on hierarchical text classification, fruit ripeness analysis, and embedded vision systems. His teaching activities include courses on Data Analytics for Business and Society, emphasizing practical applications of AI and informatics. Albarelli's work spans theoretical frameworks and applied research, addressing challenges in both academic and industrial contexts. Research Interests: Machine Learning algorithms, computer vision techniques, and their applications in agriculture, edge computing, and multi-camera systems. Recent Contributions: Over 90 publications, including high-impact journals like Electronics and Expert Systems with Applications . His academic contributions reflect a balance between foundational research and real-world problem-solving, with notable projects on model explainability, quantization-aware neural networks, and calibration techniques for vision systems. Albarelli serves as a faculty member in both undergraduate and graduate programs, integrating cutting-edge research into curriculum design.

• Sparse optimization
• Machine learning
• Convex and nonconvex optimization
• +۷ مورد دیگر

Sophie Fosson is an Associate Professor in the Department of Control and Computer Science (DAUIN) at the Polytechnic University of Turin, Italy. She is a member of the System Identification & Control (SIC) research group and teaches courses such as Automatic Control and Modeling and Control of Cyberphysical Systems at both the master's and doctoral levels. Education: PhD in Mathematics for Industrial Technologies, Scuola Normale Superiore di Pisa Master’s in Mathematical Engineering, Politecnico di Torino Her research focuses on sparse optimization, machine learning, system identification, and control theory . She integrates mathematical modeling with practical applications in cyber-physical systems and neural networks. Her work emphasizes efficient and robust optimization techniques for deep learning and control systems. The recent publications highlight a strong trend in optimization of neural networks , particularly through sparse training, binary and ternary quantization, self-supervised learning, and fault tolerance . Her research bridges control theory with machine learning, applying mathematical rigor to modern AI challenges in safety-critical and embedded environments. Scientific Awards: No awards explicitly mentioned. She supervises several PhD students including Alice Re, Rosario Milazzo, and Simone Pirrera , and has been involved in research projects such as CRISP and collaborations with Centre Tecnològic de Telecomunicacions de Catalunya . She has held postdoctoral positions at DISMA and DET (Politecnico di Torino) and worked as a researcher at Istituto Superiore Mario Boella. Laboratories and Research Groups: System Identification & Control (SIC), DAUIN, Politecnico di Torin

• Computer Architecture
• Systems & Networking
• Approximate Computing
• +۶ مورد دیگر

Weng Fai WONG is an Associate Professor and Deputy Head of the Department of Computer Science at the School of Computing, National University of Singapore (NUS). With over three decades of academic experience at NUS, he has established himself as a leading researcher in computer systems, with particular expertise in the interface between hardware and software stacks. Dr. Wong received his B.Sc. (First Class Honors) and M.Sc. from the National University of Singapore in 1989 and 1991 respectively, followed by a Dr.Eng.Sc. from the University of Tsukuba in 1993. His academic journey began at NUS (then DISCS) in 1985, where he progressed from student to Senior Tutor in 1989, and later returned from Japan as a Lecturer in 1993. Dr. Wong's research focuses on systems and networking, with special emphasis on hardware-software co-optimization. His current research interests include approximate computing , neuromorphic computing , and hardware acceleration for deep learning. His work spans computer architecture , embedded systems , compilers and runtime systems , and programming languages . He has made significant contributions to optimizing software for novel hardware including FPGAs, GPUs, and non-volatile memory technologies. His recent publications (2023-2025) demonstrate a strong focus on energy-efficient AI computing, with particular emphasis on spiking neural networks, large language model acceleration, and FPGA-based solutions for graph processing and machine learning workloads. His research shows a clear trajectory toward green AI through hardware-software co-design that minimizes energy consumption while maintaining computational effectiveness. Dr. Wong is a Member of ACM and a Senior Member of IEEE. His paper "Exploiting half precision arithmetic in Nvidia GPUs" was a Best Paper Finalist at the IEEE High Performance Extreme Computing Conference (HPEC 2017). As Deputy Head of the Department of Computer Science at NUS, Dr. Wong plays a key leadership role in academic administration while maintaining an active research program. His work has been supported by numerous research grants, though specific details are not provided in the available information. Dr. Wong leads research in the Systems & Networking area at NUS, with particular focus on the Hardware-Software Interface Laboratory. His team explores innovative approaches to bridge the gap between theoretical computer science and practical hardware implementation, with applications spanning from edge computing to large-scale data centers.

Chenchen Liuمشاهده پروفایل

استادیار

• High-performance computing for machine learning
• Brain-inspired computing
• Hardware-software co-design
• +۴ مورد دیگر

Dr. Chenchen Liu is an Assistant Professor of Computer Science and Electrical Engineering at the University of Maryland, Baltimore County (UMBC). She is affiliated with the Computing Compass Laboratory and holds a Hans Fischer Fellowship at the Technical University of Munich Institute for Advanced Study (TUM-IAS) under the focus group Enabling Neuromorphic Computing for Multi-Tenant AI. Her work bridges hardware-software co-design with neuromorphic computing. Ph.D., Electrical and Computer Engineering, University of Pittsburgh (2017) M.S., Electrical and Computer Engineering, Peking University (2013) Her research focuses on high-performance computing for machine learning through novel computer architecture and system designs, brain-inspired computing, machine learning security, non-volatile memory, and VLSI design. Key areas include: Neuromorphic hardware resilience and optimization Memristor-based neural network architectures Runtime scheduling for multi-tenant AI Security in neuromorphic computing Energy-efficient memory systems Recent publications explore memristor defect tolerance, ReRAM-based CNN training efficiency, and spiking network quantization. The work emphasizes hardware-software co-design for AI acceleration. NSF Career Award (2023) Best Poster Award, Machine Learning and Systems Conference (2022) Best Paper Award, IEEE Symposium on VLSI (2014) She contributes to academic service as TPC Chair/Track Chair for DAC, GLVLSI, Cloud Summit conferences and serves as Associate Editor for IEEE Transactions on Circuits and Systems (TCAS-1) and Neurocomputing journal.

• Chaos theory
• Compressed sensing
• Electromagnetic interference
• +۱۴ مورد دیگر

Fabio Pareschi is an Associate Professor at the Department of Electronics and Telecommunications (DET), Politecnico di Torino, where he conducts research in circuit architectures, embedded systems, and signal processing with applications in security, AI, and power electronics. He is affiliated with the VLSILAB research group and leads multiple high-impact research projects. Research Interests: Chaos theory and true random number generation for cryptographic applications Compressed sensing for secure and efficient signal acquisition EMI reduction techniques in DC-DC power converters Tiny machine learning and low-power embedded systems Circuit design for IoT and biomedical applications The recent articles highlight a strong trend in integrating compressed sensing with encryption, leveraging chaos-based randomness for security, and optimizing power electronics for EMI reduction. His work bridges theoretical foundations with practical hardware implementations in microelectronics and embedded systems. Scientific Awards: Best Student Paper Award (IEEE, 2005) Best Paper Award (IEEE, 2005) IEEE PRIME Gold Leaf Certificate (2019) BioCAS Transactions Best Paper Award (2019) Best Student Paper Award at EMCCompo (IEEE, 2019) Advising and Grants: He supervises multiple PhD students in the Electrical, Electronics, and Communications Engineering program. He is the Scientific Director of the CESOIA project (Non-EU International Research, 2025–2028) on low-complexity AI models, and leads the ECS4DRES project (EU-funded, 2024–2027) on resilient energy systems. He also heads a commercial research project on high-performance DC-DC converters (2022–2025). His editorial roles include Associate Editor for IEEE Transactions on Circuits and Systems and guest editorships in multiple IEEE journals. Labs and Teams: He is a key member of the VLSILAB Group (DET), which focuses on VLSI systems, embedded signal processing, and secure hardware design.

• Image Compression
• Machine Learning
• Visual Media Processing
• +۷ مورد دیگر

Jona Ballé is an Associate Professor in the Electrical and Computer Engineering department at New York University's Tandon School of Engineering. His research focuses on developing efficient representations of visual media through machine learning and end-to-end optimization techniques. Dr. Ballé's research interests center on visual media compression, spanning still images, video, augmented reality, virtual reality, plenoptic imaging, and holographic imaging. His work bridges information theory, computer vision, and machine learning to develop perceptually optimized compression algorithms. He has made significant contributions to understanding the relationship between human visual perception and image statistics, which has led to improved compression results and ultimately contributed to the JPEG AI standard finalized in 2025. His recent publications demonstrate a strong trend toward Wasserstein distortion metrics, neural compression architectures, and rate-distortion optimization. These works span computer vision, information theory, and signal processing domains, with applications in both traditional and emerging visual media formats. His research shows consistent innovation in developing perceptually relevant metrics that balance fidelity and realism in compressed media. Contributed to JPEG AI standard (2025) Co-organizer of Challenge on Learned Image Compression (CLIC) since 2018 Program committee member of Data Compression Conference (DCC) since 2022 Reviewer for top-tier publications including NeurIPS, ICLR, ICML, and IEEE Transactions journals Dr. Ballé has advised numerous graduate students who have co-authored significant publications with him, particularly in the areas of neural compression and perceptual metrics. His research has been supported by institutions including the Simons Foundation. He maintains active collaborations across academia and industry, with his work at Google (2017-2024) directly informing his current academic research. His laboratory focuses on developing open-source implementations of advanced compression techniques, with notable GitHub repositories including Wasserstein Distortion implementation in PyTorch and CoDeX (Learned data compression in JAX), demonstrating his commitment to reproducible research and community engagement.

Sotirios Xydisمشاهده پروفایل

استادیار

• Hardware/Software Co-design
• High Level Synthesis
• Hardware Accelerators
• +۷ مورد دیگر

Sotirios Xydis is an Assistant Professor in the Division of Computer Science at the School of Electrical and Computer Engineering, National Technical University of Athens (NTUA), with prior faculty appointment at Harokopion University of Athens (2020-2023). He maintains ongoing collaboration with the Institute of Communication and Computer Systems (ICCS) since 2014 and previously served as an engineer at HEDNO (2015-2018) and postdoctoral researcher at Politecnico di Milano (2011-2013). His academic credentials include: BSc in Electrical and Computer Engineering, NTUA (2005) MSc in Techno-Economic Systems, NTUA (2011) PhD in Electrical and Computer Engineering, NTUA (2011) Dr. Xydis specializes in hardware/software co-design , energy-efficient hardware acceleration , and memory management for embedded and cloud-edge systems. His research bridges low-power circuit design , heterogeneous architecture optimization , and resource management frameworks , with particular emphasis on AI workloads and serverless infrastructures. Current projects target Edge AI accelerators (CONVOLVE), disaggregated memory systems, and LLM inference optimization through hardware-aware algorithms. Analysis of his 2023-2025 publications reveals three dominant trends: (1) Energy-efficient hardware accelerators for Edge AI using approximate computing techniques, (2) Memory/resource management innovations for disaggregated serverless environments, and (3) GPU/FPGA optimization for LLM inference through dynamic frequency scaling and predictive throttling. These works consistently address the power-performance tradeoffs in heterogeneous computing systems. His scientific recognition includes: Best Paper Award, IEEE/NASA/ESA AHS (2007) Best Paper Award, ACM PARMA (2013) Best Paper Award, ACM Computing Frontiers (2020) Hipeac Award at DAC (2019, 2020) Dr. Xydis has secured over 15 European/national research grants as Principal Investigator and Technical Coordinator, focusing on hardware acceleration frameworks and energy-efficient computing. His advising encompasses graduate research in hardware design and optimization, though specific student names aren't publicly listed. Current projects include CONVOLVE for Edge AI and CollectiveHLS for collaborative hardware synthesis. He is a core member of NTUA's Microelectronics Laboratory (Microlab) and collaborates with ICCS on hardware acceleration projects. His team develops frameworks like CollectiveHLS and throttLL'eM, with active participation in DATE, DAC, and ISCA conference communities.

Park Ki-hoمشاهده پروفایل

دانشیار

• Computer Architecture
• Embedded System Design
• IoT System Design
• +۴ مورد دیگر

Dr. Park Ki-ho is an Associate Professor at the Department of Computer Engineering, Sejong University. His research focuses on computer architecture, embedded systems, IoT systems, and low-power design methodologies. Academic Background: PhD in Computer Science from Yonsei University Professional Experience: Senior Engineer at Samsung Electronics, Post-Doctoral Research Associate at University of Utah Research Interests: Develops innovative solutions for sensor hub design , memory systems , and machine learning hardware acceleration . Key areas include: Non-Volatile Memory (NVM) management 3D Integrated Circuit memory bandwidth optimization Intelligent Edge Device architectures Hybrid Cache Architectures Model Compression Techniques On-Device AI Processing Recent Publications demonstrate expertise in in-memory acceleration , sparse matrix representation , and large language model inference . His work bridges theoretical advancements with practical implementations for IoT and AI applications.

Farinaz Koushanfarمشاهده پروفایل

استاد

• Hardware Security
• Integrated Circuit Security
• Physical Unclonable Functions
• +۵ مورد دیگر

Farinaz Koushanfar is a Professor in the Electrical Engineering and Computer Science department at the University of Michigan's College of Engineering. With an impressive h-index of 65 and over 27,000 citations, she has established herself as a leading researcher in hardware security and privacy-preserving computing. Her research interests span hardware security, integrated circuit protection, physical unclonable functions, hardware trojans, logic locking, and privacy-preserving machine learning. Koushanfar's work addresses critical security challenges throughout the semiconductor supply chain, developing innovative solutions for IP protection, anti-counterfeiting, and secure hardware design. Analysis of her recent publications reveals a strong focus on the intersection of hardware security and machine learning, particularly in federated learning security and privacy-preserving deep neural network inference. Her research shows a clear trajectory from foundational hardware security mechanisms toward more complex systems-level security challenges in emerging computing paradigms. Throughout her career, Koushanfar has made significant contributions to both theoretical frameworks and practical implementations in hardware security, with numerous highly influential publications that have shaped the field.

• Machine Learning
• AI Hardware
• Reliability Analysis
• +۴ مورد دیگر

Rodion Novkin is a researcher at the Chair of AI Processor Design (AI-Pro) at Technical University of Munich (TUM). His work bridges machine learning with semiconductor reliability and hardware design, focusing on emerging technologies like neuromorphic computing and RISC-V for AI. Research interests include: Machine Learning for electronic reliability analysis Quantization-aware training techniques for neural networks FeFET/FinFET device degradation modeling ML-driven TCAD (Technology CAD) solutions Quantum computing hardware challenges Approximate computing for edge AI 2023 publications highlight trends in applying ML to semiconductor reliability, graph neural network optimization, and FeFET device modeling. His work spans from device physics to system-level AI implementations. Contact: rodion.novkin@tum.de

Wei Huمشاهده پروفایل

استادیار

• Deep Learning Theory
• Machine Learning
• Neural Networks
• +۲ مورد دیگر

Wei Hu is an Assistant Professor in the Department of Computer Science and Engineering at the University of Michigan's College of Engineering. His research focuses on uncovering the theoretical and scientific foundations of deep learning, aiming to open the black box of neural networks through a combination of theoretical and empirical approaches. Dr. Hu received his PhD in Computer Science from Princeton University, where he was advised by Sanjeev Arora. Prior to his PhD, he completed his undergraduate studies at Tsinghua University as a member of the prestigious Yao Class. He also served as a FODSI postdoc at UC Berkeley before joining the University of Michigan faculty. His research interests center around understanding the fundamental mechanisms of deep learning, particularly focusing on training dynamics, generalization properties, and the theoretical underpinnings of neural networks. His work spans both clean, controlled problems and complex real-world models, with recent emphasis on transformer architectures, grokking phenomena, and the implicit biases in neural network training. Analysis of his recent publications reveals a strong focus on theoretical deep learning with particular attention to transformer models, grokking phenomena, and generalization theory. His work bridges the gap between theoretical understanding and practical deep learning applications, with significant contributions to understanding abrupt learning transitions, representation learning, and the dynamics of neural network training. AAAI New Faculty Highlights, 2024 Google Research Scholar Award, 2023 Siebel Scholar, 2021 Best paper award at ICML Workshop on Modern Trends in Nonconvex Optimization for Machine Learning, 2018 Gordon Y.S. Wu Fellowship, 2016 Gold medal (1st place), The 27th Chinese Mathematical Olympiad, 2012 Dr. Hu currently advises three PhD students: Pulkit Gopalani, Zhiwei Xu (co-advised with Yixin Wang), and Yongyi Yang. His research group has received substantial funding through awards including the Google Research Scholar Award. He teaches courses including Introduction to Machine Learning (EECS 445) and specialized topics in machine learning theory and large language models (EECS 598/CSE 598). His research group maintains an active presence in top machine learning conferences, with publications appearing regularly in venues such as NeurIPS, ICML, ICLR, and others. The group's work has gained significant recognition in the theoretical machine learning community for its rigorous approach to understanding deep learning phenomena.