Professor Daniel P. Robinson holds the position of Professor and MS Program Director in the Department of Industrial and Systems Engineering at Lehigh University. Previously, he served as a Postdoctoral Researcher at the University of Oxford and Northwestern University, and as an Assistant Professor at Johns Hopkins University. His research focuses on computational optimization and its applications in data science, machine learning, and computer vision, with a particular emphasis on healthcare and algorithm design. Education: Ph.D. in Mathematics from the University of California, San Diego; postdoctoral training at Oxford University and Northwestern University. Research Interests: Dr. Robinson’s work bridges mathematical optimization and data science, emphasizing algorithm design for continuous optimization problems. His areas include computational optimization, machine learning, data science, and computer vision applications. He has contributed to fair machine learning frameworks, stochastic optimization algorithms, and neural network compression techniques. His publications span top-tier journals and conferences such as Mathematical Programming, SIAM Journal on Optimization, and ICML. Notable grants include NSF funding for optimization research. He co-founded Johns Hopkins’ Mathematical Institute for Data Science (MINDS) and helped establish the JHU Master of Science in Data Science program. Scientific Awards: Twice recipient of the Professor Joel Dean Award for Excellence in Teaching. Advising & Grants: As MS Program Director, he oversees academic programs. His grants include over $1M from the Office of Naval Research and NSF support. He collaborates on projects like scalable subspace clustering and privacy-preserving machine learning. Labs/Teams: Leadership roles in Lehigh ISE’s optimization programs, fostering interdisciplinary research in data science and optimization.
Douglas M. Blough is a Professor at the Georgia Institute of Technology's School of Electrical and Computer Engineering, where he has served since 1999. He previously held faculty positions at the University of California at Irvine from 1988 to 1999. Dr. Blough directs the Critical Networking Laboratory and has served as the School's associate chair for faculty development since January 2018, including a five-month term as Interim Steve W. Chaddick School Chair in 2021. Dr. Blough's research focuses on wireless networks, distributed computer systems, and computer systems security. His specific interests include healthcare security, mobile and wireless communications, telecommunications, and computer systems and software. He has led 37 federally-funded or industry-sponsored research projects with over $8 million in funding, including current NSF grants for next-generation wireless networks exploring design challenges for networks operating in the millimeter-wave bands. His recent scholarly work demonstrates a strong emphasis on millimeter-wave communications, intelligent reflecting surfaces, and next-generation wireless LAN technologies. His publications reveal a progression from foundational work in dependable computing systems to cutting-edge research in wireless networking, with a particular focus on mmWave technology and intelligent surfaces in recent years. His research group has produced numerous award-winning papers, including multiple Best Paper Awards in 2021-2022. Professional Distinctions: Best Paper Award, IEEE International Symposium on Local and Metropolitan Area Networks, 2022 Best Paper Award, IEEE Consumer Communications and Networking Conference, 2021 Associate Editor, IEEE Transactions on Wireless Communications (2020-present) Associate Editor, IEEE Transactions on Cloud Computing (2020-present) Japan Society for the Promotion of Science (JSPS) Faculty Fellow, 1996 NASA/ASEE Faculty Fellow, 1993 Dr. Blough has advised numerous PhD students who now hold positions at leading technology companies including Microsoft, Google, Amazon, Intel, and Huawei. His research has resulted in over 160 archival publications and 10 patents related to wireless communications, bioinformatics, verifiable health records, and identity management. He has held significant leadership roles within his department, including chairing technical interest groups and serving on key committees for faculty development and honors.
Martin Trapp is an Academy Postdoctoral Researcher in the Department of Computer Science at Aalto University, specializing in probabilistic machine learning. He is affiliated with Professor Arno Solin's research group, focusing on advancing tractable probabilistic models for real-world applications. His research centers on Probabilistic Circuits , Probabilistic Programming , and Bayesian Nonparametrics , with emphasis on hardware-efficient implementations for edge devices and multimodal systems. Key interests include uncertainty quantification in deep learning, neurosymbolic AI integration, and medical imaging applications. His work bridges theoretical foundations with practical deployment constraints, particularly in resource-limited environments. Analysis of his 15 most recent publications (2022-2025) reveals three dominant trends: (1) hardware-aware probabilistic inference for TinyML applications, (2) scalable Bayesian methods using bitstring representations and probabilistic programming, and (3) multimodal robustness in vision-language systems and medical imaging. His contributions span from theoretical circuit representations to real-world implementations in mammography analysis and vision-language models. Trapp secured a HIIT short-term project grant (November 2022) for "Positive Semi-Definite Circuits" under the Department of Computer Science. No formal advising relationships are documented in available sources. He actively collaborates with researchers including Arno Solin, Rui Li, and Marcus Klasson across institutions like Aalto University and the Helsinki Institute for Information Technology. As a core member of Aalto's Probabilistic Machine Learning group, he contributes to advancing probabilistic AI methodologies with applications in healthcare, edge computing, and multimodal reasoning. His current work emphasizes deployable probabilistic systems that maintain rigorous uncertainty quantification while meeting hardware constraints.
Krishna Teja Chitty-Venkata is a Postdoctoral Researcher at the Argonne Leadership Computing Facility (ALCF), Argonne National Laboratory, USA, where he works in the AI/ML team (formerly Data Science group). His research lies at the intersection of systems and machine learning, focusing on optimizing neural network training, finetuning, and inference on general-purpose and AI-specific hardware platforms. He is actively involved in AI for science applications and high-performance computing for AI (HPC for AI). Education: PhD in Computer Engineering, Iowa State University, 2017–2023 Bachelor of Engineering in Electronics and Communication Engineering, University College of Engineering, Osmania University, Hyderabad, India, 2013–2017 Research Interests: Krishna's research spans hardware-aware inference optimization of deep neural networks, enhancing training and finetuning of large language models (LLMs) and vision-language models (VLMs), neural architecture search (AutoML), pruning and quantization techniques, performance modeling, and AI for science. He is particularly interested in efficient adaptation methods such as LoRA-NAS integration, structured pruning (e.g., WActiGrad), and KV cache optimization (e.g., Paged Compression). Publication Trends: His recent work emphasizes benchmarking and optimization of LLMs on diverse AI accelerators (e.g., LLM-Inference-Bench), developing scalable frameworks for CNN and ViT evaluation (ConVision Benchmark), and advancing structured pruning and mixed-precision search methods. His publications span high-impact journals and conferences in computer science, AI, and systems, reflecting a strong focus on practical, hardware-aware solutions for deep learning efficiency. Scientific Contributions: Developed LLM-Inference-Bench for evaluating LLM performance across hardware and frameworks. Created ConVision Benchmark for standardized evaluation of CNNs and Vision Transformers. Proposed WActiGrad, a structured pruning method for efficient LLM finetuning and inference. Introduced Paged Compression for efficient KV cache management in vLLM. Designed LangVision-LoRA-NAS for optimizing VLMs via NAS-integrated adapters. Professional Experience and Advising: Krishna has been mentored by Prof. Arun K. Somani (Iowa State) and supervisors Murali Emani and Venkatram Vishwanath at Argonne. He has interned at AMD, Intel, and Argonne, contributing to deep learning optimization projects. While no formal students are listed, he has co-authored multiple papers with researchers and students, indicating collaborative advising. He has no publicly listed grants, but his work at Argonne is likely supported by institutional and DOE funding. Labs and Teams: He is part of the AI/ML team within the Argonne Leadership Computing Facility, a premier HPC and AI research division. His work involves close collaboration with teams developing AI accelerators and scientific applications, positioning him at the forefront of AI for science initiatives.
Mohammad Mahdi Khalili is an Assistant Professor in the Department of Computer Science and Engineering at The Ohio State University's College of Engineering. He also serves as a part-time Research Scientist at Yahoo! Research, focusing on theoretical and applied machine learning with emphasis on robustness, interpretability, and model compression for large-scale systems including LLMs. Dr. Khalili earned his Ph.D. in Electrical Engineering and Computer Science and MSc in Applied Mathematics from the University of Michigan, Ann Arbor. Prior to OSU, he was a research scientist at Yahoo Research and a postdoctoral researcher at UC Berkeley. His research spans mechanistic interpretability of foundation models , privacy-aware model compression , and fairness in sequential decision-making . Current projects include counterfactual reasoning for fair ML, physiological signal analysis for worker health monitoring, and corruption analysis in model mechanisms. His work bridges theoretical guarantees with practical healthcare and security applications. Recent publications reveal strong focus on model compression techniques (block-wise sparsity, quantization) and interpretability methods for LLMs, with growing emphasis on physiological signal processing applications. The 2024-2025 papers show increasing integration of healthcare domains like ECG analysis and construction worker monitoring. Dr. Khalili currently advises four PhD students: Zhiqun Zuo: Counterfactual Reasoning Zhongteng Cai: Privacy-Aware Model Compression (UAI travel grant recipient) Ding Zhu: Trustworthy Model Compression & Time Series Analysis Vishnu Chhabra: Mechanistic Interpretability His research is supported by two NSF grants (health monitoring systems and dynamic environment robustness), a Translational Data Analytics Institute grant for medical AI, and a College of Engineering grant for large-scale systems. The lab recently acquired a dedicated GPU server for intensive computations. He actively contributes to the ML community through invited talks (Midwest Machine Learning Symposium) and publications in top venues including NeurIPS, ICML, and UAI.
Minxuan Zhou is an Assistant Professor of Computer Science at Illinois Institute of Technology. His research focuses on systems, high-performance computing, and parallel computing with an emphasis on processing-in-memory (PIM) acceleration, fully homomorphic encryption (FHE), and hyperdimensional computing. He holds a Ph.D. and M.S. in Computer Science from the University of California San Diego, and a B.S. in Computer Science and Technology from Beihang University. His work spans hardware-software co-design, cryptographic acceleration, and energy-efficient computing systems. Research Interests Processing-in-Memory (PIM) architectures for accelerating machine learning and graph processing Hardware acceleration for secure computation (FHE) Hyperdimensional computing frameworks for edge AI Thermal-aware design and memory optimization in 3D systems Recent Research Trends Recent publications emphasize co-optimization techniques for PIM architectures, FHE hardware acceleration, and privacy-preserving machine learning. His work often bridges theoretical algorithm design with practical hardware implementations using novel memory technologies like ReRAM and 3D-stacked memory. Grants & Labs Engaged in cutting-edge research through collaborations on projects involving PIM accelerators and encrypted computation systems. His lab focuses on developing full-stack solutions for next-generation computing architectures.
Jeremy Singer is a Reader in Programming Language Implementation at the School of Computing Science, University of Glasgow. He specializes in systems software, compilers, garbage collection, and secure runtime environments. His research focuses on advancing memory management techniques, many-core parallelism, and edge computing. Singer holds a PhD from the University of Cambridge (2006) in Static Program Analysis based on Virtual Register Renaming. He is a Senior Member of the ACM and a Fellow of the BCS. His academic roles include supervising PhD students in areas such as quantum memory management, federated graph neural networks, and secure memory systems. He has led multiple EPSRC-funded projects, including M4Secure (2023-2026), Capable VMs (2020-2024), and FRuIT (2017-2019). He teaches courses like COMPSCI1016 (Computational Thinking) and COMPSCI4021 (Functional Programming in Haskell). Singer’s research spans compiler design, runtime systems, and security. Notable contributions include work on SSA-based compiler techniques, Raspberry Pi cluster systems, and secure microPython implementations. He has authored over 80 publications and co-developed MOOCs on functional programming and data science. His awards include Fellow of the BCS and Senior ACM Membership. Current research interests include secure memory management, compiler optimizations for heterogeneous architectures, and edge computing security.
Prof. Bongjin Kim is an Associate Professor in the School of Electrical Engineering at KAIST. Previously, he held a position as Assistant Professor at UCSB. His research focuses on secure hardware design, machine learning, and alternative computing architectures, including Ising machines and processing-in-memory systems. He leads the Kim Circuit Research Lab, which designs novel VLSI circuits for AI, robotics, and optimization problems. Education: PhD, University of Minnesota (ECE); MS, Pohang University of Science and Technology (ECE). He has advised over 20 graduate and undergraduate students, with notable advisees including Dr. Jooyoung Bae (PhD 2025) and Dr. Yihao Wu (PhD 2025). His work has been recognized with awards such as the NSF CAREER Award (2023) and the NRF Outstanding Young Scientist Grant (2025). Recent research includes developing a 28nm Ising machine for combinatorial optimization (A-SSCC 2024), a scalable bit-serial accelerator for PDEs (TCAS-I 2024), and a reconfigurable compute-in-memory macro (JSSC 2024). He serves on technical committees for ISSCC, A-SSCC, and ESSERC, and chairs sessions at ESSERC 2025 and A-SSCC 2025. Lab activities include the Basic Research Lab (NRF-funded) for Ising Foundation Model development and the C2 research project on ML ASIC accelerators. His group collaborates with institutions like SLAC, IME (A*STAR), and KAIST, fabricating over 30 test chips using 28nm/65nm processes.
Dr. Ammar Belatreche is a Senior Lecturer in Computer Science and Programme Leader for the MSc Advanced Computer Science at Northumbria University's Department of Computer and Information Sciences. He joined Northumbria University in May 2016 after previous positions as a Research Associate and Lecturer at Ulster University. He is an active member of the Computational Intelligence and Visual Computing (CIVC) research group. Dr. Belatreche earned his PhD in Computer Science from Ulster University in 2007. His professional qualifications include: Member of the Association of Computing Machinery (ACM) since 2012 Fellow of the Higher Education Academy (FHEA) since 2010 Member of the Institute of Electrical & Electronic Engineers (IEEE) since 2009 His research focuses on bio-inspired intelligent systems, machine learning, spiking neural networks, face detection and recognition, structured and unstructured data analytics, capital markets engineering, and image processing. Dr. Belatreche has extensive experience across academic and R&D in these areas, leading numerous research and consultancy projects. His recent work demonstrates a strong emphasis on neuromorphic computing, particularly spiking neural networks and their applications in computer vision, financial analysis, and biometrics. Analysis of his recent publications shows a clear trend toward advancing spiking neural network architectures, with particular focus on quantization, pruning, and binary implementations to improve efficiency. His research spans multiple domains including computer vision (face recognition, palm-vein recognition), financial technology (stock price manipulation detection), and neuromorphic engineering. Many of his recent papers (2024-2025) appear in top-tier conferences like ICLR and journals like IEEE Transactions on Neural Networks and Learning Systems. Dr. Belatreche has received professional recognition including: Fellowship with the Higher Education Academy (FHEA) Role as Associate Editor for the journal Neurocomputing He has successfully supervised or co-supervised 8 PhD students to completion and serves as a Program Committee Member and reviewer for numerous international conferences and journals. As Programme Leader for the MSc Advanced Computer Science, he plays a significant role in shaping postgraduate education in computer science at Northumbria University. His research group work bridges theoretical advances in neural computation with practical applications across multiple domains. Based in CIS 305 at Northumbria University's Newcastle campus, Dr. Belatreche continues to advance research in neuromorphic computing and its applications while contributing to academic leadership through his programme leadership role.
Dr. Chongyan Gu is a Senior Lecturer in the School of Electronics, Electrical Engineering and Computer Science at Queen’s University Belfast, part of the Faculty of Engineering and Physical Sciences. Her research focuses on hardware security, particularly Physical Unclonable Functions (PUFs), approximate computing vulnerabilities, and IoT device security. She leads the EPSRC New Investigator Award-funded project on Hardware Security for Approximate Computing and has secured industry collaborations with LG-CNS and defense companies. Dr. Gu has received notable awards including the INVENT2015 Overall Winner and Pramod Subramanyan Presentation Award. Her research has been commercialized, such as licensing PUF technology for EV charging systems and defense applications. She collaborates internationally through EU projects with Fraunhofer and ETRI. Dr. Gu serves as an IEEE Senior Member, Guest Editor for IEEE TCAS-I, and editorial roles for conferences like IEEE ISCAS and AsianHOST. She has delivered tutorials at ASP-DAC and HiPEAC, emphasizing practical PUF design and hardware security challenges. Key technical contributions include PUF-based authentication protocols, machine learning-resistant security solutions, and vulnerability analysis in approximate computing. Her work addresses emerging threats like Rowhammer attacks and hardware Trojans, leveraging graph attention networks for detection. Recent publications highlight advancements in RRAM-based PUFs, FPGA implementations, and defense mechanisms for modern DRAM systems.
Masoud Daneshtalab is a Professor at Mälardalen University, leading the Heterogeneous System research group (HERO). He previously held roles as a European Marie Curie Fellow at KTH Royal Institute of Technology (2014) and as a university lecturer and group leader at the University of Turku, Finland (2012-2014). His research focuses on interconnection networks, hardware/software co-design, deep learning acceleration, and evolutionary optimization. He specializes in fault-tolerant DNN accelerators, time-sensitive networking (TSN), and embedded systems. His work bridges theoretical advancements with practical implementations, emphasizing reliability and efficiency in edge computing and AI applications. Research interests include: Network-on-Chip (NoC) architectures and congestion prediction Fault resilience in deep neural networks (DNNs) Optimization of federated learning and homomorphic encryption for edge AI Integration of TSN with 5G and automotive systems Hardware acceleration techniques for computational efficiency Recent publications emphasize advancements in robust AI architectures, fault tolerance mechanisms, and TSN-based communication protocols. His work often addresses practical challenges in deploying machine learning models on resource-constrained devices. He actively contributes to interdisciplinary projects in autonomous systems, healthcare monitoring via FMCW radar, and neural architecture search for embedded applications. Labs/Teams: Leads the HERO group at Mälardalen University, focusing on heterogeneous computing systems and real-time embedded systems.
Dr. Chang Y Choo is a Professor of Electrical Engineering at San José State University, where he also serves as Director of the AI/ML FPGA/DSP Systems Laboratory. His academic career spans over three decades, with previous positions at Worcester Polytechnic Institute and industry experience at Altera Corp. (now Intel). Dr. Choo maintains an active research program focusing on hardware acceleration for AI and signal processing applications, with particular emphasis on FPGA-based implementations for real-world systems. Dr. Choo's educational background includes: Ph.D. in Computer and Systems Engineering, Rensselaer Polytechnic Institute (1986) M.S. in Operations Research and Statistics, Rensselaer Polytechnic Institute (1982) B.S./M.S. in Engineering, Seoul National University, Korea Dr. Choo's research interests center on the intersection of hardware design and artificial intelligence. His work focuses on implementing computer vision, deep learning, and digital signal processing algorithms on specialized hardware platforms including FPGAs, GPUs, and custom ASICs. Current projects include developing real-time illumination/view-independent object recognition systems for autonomous vehicles, wideband acoustic echo cancellation for wearable technology, and FPGA-based accelerators for medical imaging applications. His research bridges theoretical algorithm development with practical hardware implementation constraints. Analysis of Dr. Choo's recent publications reveals a clear trajectory toward increasingly sophisticated hardware-accelerated AI systems. His work has evolved from foundational research in digital signal processing and image compression to cutting-edge applications of deep learning on specialized hardware. Recent publications demonstrate expertise in implementing CNN architectures on FPGAs, developing metabolic syndrome prediction models, and creating food object detection systems using transformer models. This progression reflects the broader field's shift toward hardware-aware AI development. Dr. Choo's significant scientific contributions include multiple patents that have advanced the state of the art in several domains: U.S. Patent No. 9,025,763 (2015): 'Apparatus and Method for cancelling wideband acoustic echo' U.S. Patent Nos. 7,058,675 (2006) and 7,124,161 (2006): 'Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices' U.S. Patent Nos. 5,943,096 (1999) and 6,621,864 (2003): 'Motion vector based frame insertion process' U.S. Patent Nos. 5,832,131 (1998) and 5,991,455 (1999): 'Hashing-based vector quantization' U.S. Patent No. 5,587,710 (1997): 'Syntax based arithmetic coder and decoder' Throughout his career, Dr. Choo has been actively involved in both academic and industry collaborations. He has served as a technical consultant for numerous Silicon Valley companies including National Semiconductor (now Texas Instruments), Philips Semiconductor, Skybox Imaging (acquired by Google), Novariant (now AgJunction), and Ricoh Innovations. His industry experience informs his teaching approach, which emphasizes practical implementation considerations alongside theoretical foundations. Dr. Choo has also served as an expert witness in intellectual property court cases involving audio and video compression algorithms and FPGA hardware. Dr. Choo directs the FPGA/DSP AI/DL Laboratory at San José State University, which focuses on developing hardware-accelerated solutions for real-time AI applications. The lab maintains strong connections with Silicon Valley technology companies and provides students with hands-on experience in cutting-edge hardware design methodologies. Current research directions include autonomous vehicle navigation systems, medical imaging applications, and edge AI deployment strategies.
Kazushi Kawamura is an Assistant Professor at the Tokyo Institute of Technology 's AI Computing Research Unit , with prior roles at Waseda University and the Institute of Science Tokyo. His academic journey began at Waseda University, where he earned a Dr. Eng in 2016. 2025.04 - Now: Assistant Professor, School of Fundamental Science and Engineering, Tokyo Tech 2024.10 - 2025.03: Assistant Professor, School of Fundamental Science and Engineering, Waseda 2020.04 - 2025.03: Specially Appointed Assistant Professor, Institute of Integrated Research, Institute of Science Tokyo His research spans combinatorial optimization , annealing processors , Ising machines , and FPGA-based computing systems . He has contributed extensively to LSI design methodology and high-level synthesis . Key publication trends include neural network compression , parallel annealing algorithms , edge AI inference , and sparse matrix operations on FPGAs. His work often integrates theoretical optimization with practical hardware implementations . 2023 CS Achievement Award 2016 ISOCC Best Paper Multiple Algorithm Design Contest Prizes (2014-2019) IPSJ SLDM Outstanding Student Awards Kawamura teaches courses like Physical Electronics Laboratory and Machine Learning at Waseda, with recent projects such as Amorphica (metamorphic annealer) and Pianissimo (sub-mW DNN accelerator). He serves on committees for IEEE , IPSJ , and IEICE , focusing on system design and circuit optimization.
Nagarajan Kandasamy is a Professor and Interim Department Head in the Department of Electrical and Computer Engineering at Drexel University. His research focuses on computer engineering, with expertise in neuromorphic computing, embedded systems, fault-tolerant architectures, and distributed systems. Prior to Drexel, he worked as a research scientist at Vanderbilt University's Institute for Software Integrated Systems. PhD, University of Michigan (2003) MS, University of Connecticut BE, Guindy Engineering College, Anna University, Chennai, India His research interests include neuromorphic computing, spiking neural networks, and reliable system design. He has contributed to fields like deformable image registration, self-testing hardware, and wireless security frameworks. Kandasamy's publications emphasize neuromorphic architectures, medical imaging algorithms, and secure communication protocols. His work often intersects hardware-software co-design and machine learning applications. National Science Foundation Early Faculty (CAREER) Award (2007) Best Paper Award, IEEE International Conference on Autonomic Computing (2006) He collaborates across disciplines in neuromorphic engineering, with grants from NSF and industry partners. His team develops tools for radiation oncology, low-power AI systems, and FPGA-based security protocols.
Adnan Siraj Rakin is an Assistant Professor at Binghamton University's School of Computing. He holds a PhD and MS in Computer Engineering from Arizona State University (2022 and 2021) and a BS in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (2016). His research focuses on AI security, including adversarial attacks on deep learning systems, model stealing, and hardware vulnerabilities. Notable contributions include defenses against bit-flip attacks, weight duplication frameworks, and RowHammer exploits. Research Interests: Adversarial Attacks (Input/Weight/Model Stealing) Deep Learning Security Hardware Vulnerabilities (e.g., FPGA/DRAM) Robust Neural Network Design Publications highlight advancements in detecting and mitigating adversarial perturbations, with work featured in CVPR, ICCV, and IEEE Security & Privacy. His recent efforts address LLM vulnerabilities and edge computing efficiency. He received the 2022-2023 Educator of the Year award from Binghamton's CS department. Current projects include developing full-stack obfuscation frameworks, secure domain adaptation, and exploring adversarial impacts on robotics systems.
