جستجوی استاد راهنمای دانشگاهی

Brandon M. Luciaمشاهده پروفایل

استاد

• Computer Architecture
• Computer Systems
• Programming Languages
• +۷ مورد دیگر

Brandon M. Lucia is the Kavčić-Moura Professor of Electrical and Computer Engineering at Carnegie Mellon University and CEO/co-founder of Efficient Computer Company. He leads the Abstract research group and focuses his work on the intersection of computer architecture, systems, and programming languages. Education: Ph.D. in Computer Science and Engineering, University of Washington (2013) — advised by Luis Ceze Research Focus: Brandon's research is broadly centered on intermittent computing , edge computing , and energy-efficient architectures . Two major thrusts define his current work: Intermittent Computing: Making battery-free, energy-harvesting devices programmable and reliable despite frequent power failures. Applications include medical implants, space systems, and large-scale sensing. Orbital Edge Computing: Designing nanosatellite constellations that perform on-orbit data processing, enabling low-latency, high-resolution sensing in space-constrained environments. Scientific Awards: NSF CAREER Award (2017) IEEE TCCA Young Computer Architect Award (2019) Sloan Foundation Fellowship (2021) ASPLOS 2020 Best Paper Award OOPSLA 2015 Distinguished Paper & Artifact Awards IEEE Micro Top Picks (2016, 2018 Honorable Mention) Advising & Grants: Brandon actively advises a strong cohort of Ph.D. students including Zhuo Cheng, Bradley Denby, Souradip Ghosh, Harsh Desai, Kiwan Maeng, Emily Ruppel, and others. His group is funded by the NSF (CAREER and SHF grants), the Sloan Foundation, and industry partnerships. Labs & Teams: He directs the Abstract research group at CMU ECE, which hosts interdisciplinary projects spanning hardware design, compiler construction, and system software for ultra-low-power and space-borne computing platforms.

Hyesoon Kimمشاهده پروفایل

استاد

• Computer Architecture
• GPU
• Compilers and Runtime Systems
• +۳ مورد دیگر

Hyesoon Kim is a Professor at the Georgia Institute of Technology , affiliated with the College of Computing and leading the HPArch research group . She co-directs the Center for Research into Novel Computing Hierarchies (CRNCH) . Her research focuses on Computer Architecture , GPU , Compilers and Runtime Systems , and Hardware Security , particularly for heterogeneous systems. Contact : hyesoon@cc.gatech.edu Location : 266 Ferst Drive, KACB 2344, Atlanta, GA Research Trends Her recent work spans RISC-V extensions for security, CUDA optimization on softcore GPUs, memory safety techniques, and energy-efficient deep learning architectures. Articles emphasize heterogeneous computing , GPU performance scaling, and IoT -oriented neural network methods. Open Source Projects She leads development of Macsim (heterogeneous architecture simulator) and Vortex (open-source GPU platform).

Priyanka Rainaمشاهده پروفایل

استادیار

• Domain-Specific Architectures
• Hardware/Software Co-design
• Energy-Efficient Computing
• +۳ مورد دیگر

Priyanka Raina is an Assistant Professor of Electrical Engineering at Stanford University, with a courtesy appointment in Computer Science. She leads the Stanford Accelerate research group, focusing on domain-specific hardware architectures and agile hardware-software co-design. Her work emphasizes high-performance, energy-efficient accelerators for emerging technologies. Education: B.Tech. from IIT Delhi (2011), M.S. and Ph.D. from MIT (2013/2018). Postdoctoral experience includes NVIDIA Research (2018) and Amazon Visiting Academic (2023–present). Awards include the Sloan Research Fellowship (2024), NSF CAREER Award (2023), and Terman Faculty Fellowship (2018). Research Interests: Domain-specific architectures, near-memory computing, design productivity, and machine learning acceleration. Her group develops frameworks like AHA (Agile Hardware) for efficient accelerator design and compilers. Awards: Over 10 major awards, including best paper recognitions at VLSI, MICRO, and JSSC. Active roles as Associate Editor for IEEE JSSC and Program Chair for IEEE Hot Chips (2020). Advising & Teaching: Supervises multiple PhD and MS students in hardware design, CGRAs, and ML accelerators. Teaches VLSI design courses (EE271/272/372) and oversees independent studies in embedded systems and chip design. Labs & Collaborations: Affiliated with Stanford PORTAL Center, AHA Center, and SystemX Alliance. Projects include MINOTAUR (edge AI accelerator), Amber (CGRA-based SoC), and EMBER (RRAM macros).

Vijay Raghunathanمشاهده پروفایل

استاد

• Embedded Systems
• Internet of Things (IoT)
• Wearable and Implantable Electronics
• +۴ مورد دیگر

Vijay Raghunathan is a Professor in the Department of Electrical and Computer Engineering at Purdue University's College of Engineering. His work focuses on hardware and software architectures for embedded systems, wireless sensors for IoT, and wearable/implantable electronics with emphasis on low power design, energy harvesting, emerging memory technologies, and secure system design. Academic Rank: Professor Department: Electrical and Computer Engineering University: Purdue University Research Focus: Energy-efficient embedded systems, IoT, wearable devices His research explores low power design at both board-level and system-on-chip scales, micro-scale energy harvesting , and reliable/secure system design for medical devices. Recent work focuses on Processing-in-Sensor/Memory for battery-free AIoT devices, state space models for neural processing units, and security coprocessor integration in autonomous systems. Analysis of his publications reveals trends in energy-efficient neural network acceleration , approximate computing for edge inference , and compute-in-memory architectures . Key subfields include collaborative edge-cloud partitioning , sparse DNN accelerators , and security frameworks for medical devices. Vijay's work also addresses energy-accuracy tradeoffs in multimodal cognitive systems and intermittent computing using non-volatile memory technologies. His contributions span from microcontroller energy management to security protocols for implantable electronics.

Nate Fosterمشاهده پروفایل

استاد

• Programming Languages
• Networking
• Databases
• +۵ مورد دیگر

Nate Foster is a Professor of Computer Science at Cornell University and currently serves as the Associate Dean for Research in the Ann S. Bowers College of Computing and Information Science. He is also a Visiting Researcher at Jane Street and served as a Visiting Professor at École Polytechnique Fédérale de Lausanne during the 2023-24 academic year. His research uses ideas from programming languages to solve problems in networking, databases, and security. BA in Computer Science, Williams College (2001) MPhil in History and Philosophy of Science, University of Cambridge (2008, all work completed in 2003) PhD in Computer and Information Science, University of Pennsylvania (2009) Foster's research focuses on developing languages and tools that make it easy for programmers to build secure and reliable systems. His current work centers on the design and implementation of languages and tools for programmable networks, particularly using the P4 language. His past work includes bidirectional languages (also known as 'lenses'), database query languages, data provenance, type systems, mechanized proof, and formal semantics. His research group at Cornell has made significant contributions to network verification, software-defined networking, and formal foundations for programmable data planes. Analysis of Foster's recent publications reveals a strong focus on network verification and programming language foundations for networking. His work consistently applies formal methods to practical networking problems, with a particular emphasis on the NetKAT and P4 languages. Over the past five years, his research has evolved toward more complex network verification techniques, including infinite state verification, active learning of network models, and dependently-typed approaches to network programming. His work bridges theoretical computer science with practical networking systems, making formal methods accessible to network engineers. ACM Fellow (2025) ACM SIGPLAN Robin Milner Award (2023) ACM SIGCOMM Rising Star Award (2018) NSF CAREER Award (2013) Alfred P. Sloan Fellowship (2012) Multiple distinguished paper awards across top conferences including POPL, PLDI, and SIGCOMM Foster has advised numerous PhD and Master's students who have gone on to prominent positions in both industry and academia, with many continuing work in programming languages and networking. He has led multiple significant research grants including an NSF CAREER Award and has been involved in the P4 Language Consortium, serving as Chair of the P4 Language Governing Board. His work has been supported by various organizations including NSF, DARPA, and industry partners like Intel and Jane Street. Foster is also active in the programming languages research community, serving on numerous program committees and as Vice Chair of DARPA's Information Science and Technology (ISAT) study group. Foster leads a vibrant research group at Cornell focused on programming languages for networks, with collaborators from academia and industry. His group has developed several influential tools and frameworks including NetKAT, Petr4, and KATch. They maintain strong connections with the P4 community and work closely with industry partners to ensure their research has practical impact on real-world networking systems.

Rakesh Kumarمشاهده پروفایل

استاد

• Computer Architecture
• System-Level Design Automation
• Low Power Computing
• +۳ مورد دیگر

Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.

Andrew Childsمشاهده پروفایل

استاد

• Quantum Algorithms
• Quantum Information Processing
• Quantum Simulation
• +۲ مورد دیگر

Andrew Childs is a Professor at the University of Maryland, affiliated with the Department of Computer Science and the Institute for Advanced Computer Studies (UMIACS). He serves as Director of the NSF Quantum Leap Challenge Institute for Robust Quantum Simulation (RQS) and is a Fellow at the Joint Center for Quantum Information and Computer Science (QuICS). His research focuses on quantum algorithms for simulating physical systems, algebraic problems, and quantum walk protocols, with applications in quantum computing and computational complexity. University of Maryland Institute for Advanced Computer Studies (UMIACS) Joint Center for Quantum Information and Computer Science (QuICS) NSF Quantum Leap Challenge Institute for Robust Quantum Simulation Childs' research spans quantum simulation, quantum Fourier transform, phase estimation, and Hamiltonian dynamics. He has developed techniques to reduce quantum computational resources for simulating quantum systems and explored limitations of quantum computers through hidden subgroup problems and non-unitary dynamics. His publications cover diverse areas including quantum walk optimization, Hamiltonian simulation methods, and applications to cryptography and condensed matter physics. Recent works address spatial search algorithms, product formulas for commutators, and quantum routing protocols. As an educator, Childs has taught courses on quantum algorithms and information processing at both the University of Maryland and University of Waterloo, with lecture notes and materials spanning multiple years. Contact: amchilds@umd.edu | Office: ATL 3359 | Affiliated with University of Maryland's quantum research institutes.

Dana Andersonمشاهده پروفایل

استاد

• Quantum Computing
• Ultracold Atoms
• Atomtronics
• +۳ مورد دیگر

Dana Anderson is a Professor of Physics and JILA Fellow at the University of Colorado Boulder. He holds dual affiliations with the Department of Physics and JILA, a joint institute between the University of Colorado Boulder and the National Institute of Standards and Technology (NIST). His research focuses on ultracold atoms, quantum computing, and atomtronics, with applications in quantum sensing and space-based experiments. He currently serves as Chief Strategy Officer (CSO) of Infleqtion (formerly ColdQuanta), a quantum technology company he co-founded. Anderson is a principal investigator in the Quantum Pathways Institute, a NASA-funded initiative to develop quantum-based Earth-sensing technologies. He collaborates with institutions like NIST, JPL, and ColdQuanta on projects such as the Cold Atom Laboratory (CAL) for space-based ultracold atom research. His work has been recognized by TIME Magazine and led to significant grants, including a $15M NASA award for quantum space research. Research interests include atomtronics (hybrid atom-electronics systems), neutral atom quantum computing, and ultracold atom gyroscopes. His group develops novel atom chip technologies, such as window atom chips enabling high-resolution imaging, and explores applications like matterwave transistors and quantum inertial sensors. Current projects include shaken lattice interferometry for navigation and Rydberg atom-based microwave sensors. Anderson has pioneered concepts like the matterwave transistor oscillator and contributed to the first neutral atom quantum computing arrays. His work bridges fundamental physics and applied technologies, with a focus on translating quantum phenomena into practical devices. He actively mentors students and postdocs in experimental atomic physics and quantum engineering.

• Computer Networks
• Network Security
• Machine Learning in Networking
• +۳ مورد دیگر

Mariano Scazzariello is a Lecturer at KTH Royal Institute of Technology, Sweden, affiliated with the School of Electrical Engineering and Computer Science and the Department of Network and Systems Engineering. He teaches the course 'Network Systems with Edge or Cloud Datacenters (IK2227)'. His research focuses on advanced networking topics including machine learning in networks, high-speed packet processing, network emulation, and software-defined networking innovations. His work spans contributions to network emulation tools like Kathará and Megalos, stateful packet processing at terabit scales, and leveraging large language models (LLMs) for network configuration and vulnerability detection. Recent research emphasizes low-latency protocols (e.g., SRv6/DetNet integration) and GPU-centric networking on commodity hardware. Mariano’s publications (2020–2025) highlight expertise in network function virtualization, ASIC-based switching, and optimizing network configurations through AI-driven approaches. He has pioneered frameworks for evaluating routing protocols and virtualizing large network scenarios at scale.

James C. Hoeمشاهده پروفایل

استاد

• Computer Architecture
• Reconfigurable Computing
• High-Level Hardware Design and Synthesis
• +۴ مورد دیگر

James C. Hoe is Professor of Electrical and Computer Engineering at Carnegie Mellon University (College of Engineering). He is on sabbatical at MangoBoost and directs research in computer architecture, reconfigurable computing, and high-level hardware design. Education Ph.D., Electrical Engineering and Computer Science, MIT (2000) M.S., Electrical Engineering and Computer Science, MIT (1994) B.S., Electrical Engineering and Computer Science, UC Berkeley (1992) Research Interests Professor Hoe’s work spans computer architecture , reconfigurable computing , FPGA architectures , and high-level hardware synthesis . His group created the CoRAM abstraction for virtualized FPGA computing and leads efforts in power-efficient accelerators, in-network computing, and security-oriented FPGA systems. Scientific Awards IEEE Fellow (2013) Intel Outstanding Researcher Award (2021) Research Funding & Projects Intel / VMware Crossroads 3D-FPGA Academic Research Center – co-leading exploration of FPGA roles in future datacenters. DARPA BRASS program ($2.7 M, 4 years) – ensuring long-lived software systems remain robust to resource changes. Pigasus open-source IDS – world’s fastest FPGA-accelerated intrusion-detection system (100 Gb/s on one server). Labs & Teams He heads activities within the Computer Architecture Lab at Carnegie Mellon (CALCM) , supervising graduate researchers on CoRAM++, SPIRAL autotuning, and FPGA overlays for stream processing.

• Reconfigurable Computing
• FPGA Architectures
• Computer Security
• +۶ مورد دیگر

André DeHon is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering at the University of Pennsylvania, affiliated with Electrical and Systems Engineering (ESE) and Computer and Information Science (CIS). He chairs the Computer Engineering (CMPE) program and directs the CyberSavvy Security Center. His research focuses on reconfigurable computing, FPGA architectures, computer security, and energy-efficient hardware design. He holds a Ph.D. and M.S. from MIT and a B.S. from MIT's Lincoln School. Research interests include reconfigurable computing, FPGA interconnect, hardware security, and fault-tolerant systems. Notable achievements include the SEVER & PROTECT DARPA award and IEEE/ACM Fellowships. Recent work addresses fast FPGA compilation (HiPR, PLD), security through compartmentalization (μSCOPE, SCALPEL), and partial reconfiguration techniques. Teaching includes courses on hardware security, system-on-chip architecture, and digital audio basics. Over 200 publications span FPGA design, network-on-chip optimization, and molecular-scale computing. His labs (Implementation of Computation Group) explore physical implementation of computations through hardware-software co-design.

Andre DeHonمشاهده پروفایل

استاد

• Reconfigurable Computing
• FPGA Architecture
• Interconnect Design
• +۶ مورد دیگر

André DeHon is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering at the University of Pennsylvania, with affiliations in the Electrical and Systems Engineering (ESE) and Computer and Information Science (CIS) departments. He founded the Penn Computer Engineering (CMPE) program and directs the DARPA-sponsored CyberSavvy Security Center. His research spans reconfigurable computing, FPGA architecture, interconnect design, hardware security, and energy efficiency, with a focus on adapting to fabrication imperfections and runtime variability. His work explores programmable substrates (e.g., CMOS VLSI, molecular electronics) and algorithmic mappings to create resilient, efficient systems. Current projects include runtime feedback mechanisms (REFINE), partial reconfiguration (ExHiPR), and security frameworks like SCALPEL and μSCOPE. Recent publications highlight advancements in FPGA compilation (PLD, HiPR), security (SCALPEL, μSCOPE), and interconnect optimization (Asymmetry in NoC). These studies intersect computer architecture, security, and embedded systems. Scientific awards and recognitions: 2023 IEEE Fellow 2020 IEEE Mary Kenneth Keller Teaching Award 2018 ACM Fellow TCFPGA Hall of Fame (2019) Best Paper at ICFPT 2015 Academic leadership: He chairs the ACM/SIGDA Technical Committee on FPGAs and Reconfigurable Computing, previously held faculty roles at Caltech (1999–2006), and was a postdoc at UC Berkeley (1996–1999). Education includes MIT SB (1990), SM (1993), and PhD (1996) in Electrical Engineering and Computer Science.

• Tangible computing
• Human-Computer Interaction (HCI)
• Accessible interfaces
• +۳ مورد دیگر

Andrés Cuervo-Rubio is a Part-time Lecturer at Parsons School of Design, The New School. They are an interdisciplinary artist, programmer, and HCI researcher based in Brooklyn. As a co-founder of Folk Computer, a research consultancy focused on tangible computing hardware/software and programming languages, they explore accessible interfaces and paper-based interaction systems. They advise the W3C Immersive Web Working Group (WebAR/VR/XR APIs) and have spoken at global JavaScript conferences since 2017. Education: BA in Computer Science, Oberlin College (2017) BA in Creative Writing, Oberlin College (2017) Research Interests: Focuses on material-based interaction design, bridging physical/digital systems through accessible technologies. Current work emphasizes tangible computing interfaces and inclusive design practices. Active in developing educational frameworks for dynamic content creation in design curricula. Teaching: Recently taught Core 1: Interaction (PUCD 2035) and Core 2: Interaction Studio (PUCD 2125). Upcoming courses include CD Foundations: Interaction (PSAM 1028) in Fall 2025 and CD Studio: Dynamic Content (PSAM 2090) in Spring 2026. Professional Engagement: Serves as technical advisor for immersive web standards and collaborates with industry on accessible XR solutions. Co-leads workshops on physical computing pedagogy.

Josie Hughesمشاهده پروفایل

استادیار

• Soft Robotics
• Robot Design
• Fabrication
• +۴ مورد دیگر

Josie Hughes is a Tenure Track Assistant Professor at the Swiss Federal Institute of Technology Lausanne (EPFL) within the School of Engineering's Institute of Mechanical Engineering. She leads the Computer Robot Design and Fabrication Laboratory (CREATE Lab) and serves on the doctoral program committee for Robotics, Control and Intelligent Systems. Her roles include teaching courses in product development, engineering design, and data-driven manufacturing methods while maintaining active research and student supervision. Her research centers on soft robotics with emphasis on adaptive design, fabrication techniques, and real-world applications. Key areas include agricultural robotics (exemplified by the GraspBerry raspberry harvester), biomimetic materials like self-healing e-skins, and developmental robotics (BabyBot project). She pioneers approaches integrating morphological computation, variable stiffness mechanisms, and machine learning for robotic control, while championing open-source principles and diversity in robotics through accessible educational initiatives like balloon robot kits. Analysis of her recent publications reveals dominant trends in soft robotics adaptability, particularly in variable-stiffness structures, sensor integration, and task-specific optimization. Her work bridges fundamental material science with practical applications in agriculture, food science, and human-robot interaction, frequently employing computational methods like Bayesian optimization and neural networks for design and control. Scientific awards: No specific awards were mentioned in the source materials. Dr. Hughes actively supervises 16 doctoral students across diverse projects including soft grippers for agriculture, biomimetic locomotion, and robotic manipulation systems. Her advising portfolio shows strong alignment with her research themes, with current students working on topics like modular soft arms, agricultural automation, and developmental robotics. While grant details weren't specified, her high publication volume indicates robust research funding. The CREATE Lab under her leadership focuses on holistic co-design of hardware and software for soft robotic systems, with notable projects including the GraspBerry agricultural harvester and BabyBot developmental platform. The lab emphasizes open-source development and educational outreach, maintaining strong industry and academic collaborations while pushing boundaries in reconfigurable robotics and human-centered applications.

• Reconfigurable Computing
• Field-Programmable Gate Arrays (FPGA)
• High-Level Synthesis
• +۳ مورد دیگر

Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.