Prof. Srdjan Capkun is a Full Professor in the Department of Computer Science at ETH Zurich and Director of the Zurich Information Security and Privacy Center (ZISC). He holds a Dipl.Ing. from the University of Split (1998) and a Ph.D. from EPFL (2004). His research focuses on system and network security, including wireless security (e.g., secure positioning), trusted computing, blockchain technologies, and privacy-preserving systems. He co-founded 3db Access (acquired by Infineon) and Sound-Proof, addressing secure distance measurement and authentication. Notable achievements include an ERC Consolidator Grant (2016), ACM Fellowship, and IEEE Fellowship. Education: Dipl.Ing., Electrical Engineering / Computer Science, University of Split, 1998 Ph.D., Communication Systems, EPFL, 2004 Research Interests: Wireless security (e.g., UWB, GNSS, cellular) Trusted execution environments (TEEs) Blockchain and cryptocurrency systems Privacy-preserving technologies Awards & Grants: ERC Consolidator Grant (2016) ACM Fellow and IEEE Fellow Leadership of ZISC Advising & Labs: Leads the System Security Group at ETH Zurich Guided postdoctoral researchers and graduate students in security and privacy Companies: 3db Access (secure distance measurement) Futurae (online authentication)
Prof. Dr. Timothy Roscoe is a Full Professor in the Department of Computer Science at ETH Zurich. His research focuses on operating systems, networking, and distributed systems. He was inducted as an ACM Fellow in 2014 for contributions to these fields. Previously, he worked at Intel Research Berkeley, UC Berkeley (Adjunct Professor), and Sprint Labs. His work includes foundational contributions to systems like PlanetLab, P2 Declarative Networking, and the Nemesis OS. Roscoe holds a PhD from the University of Cambridge and has led projects in cloud computing, wide-area network measurement, and secure systems design. His current research emphasizes hardware-software co-design, formal verification of systems, and scalable memory architectures. Education: PhD in Computer Science, University of Cambridge (1995) Key Roles: Principal Researcher at Intel Berkeley Lab, Visiting Researcher at National ICT Australia Research Highlights: Contributions to distributed systems (PlanetLab), declarative networking (P2), and secure microkernels (seL4 integration). Current projects address challenges in disaggregated memory systems, coherent interconnects, and trustworthy embedded systems. Awards: ACM Fellow (2014), numerous grants and industry collaborations. Labs/Teams: Systems Group at ETH Zurich, focusing on OS design, hardware architectures, and formal methods.
Kaveh Razavi is an Assistant Professor at ETH Zurich in the Department of Information Technology and Electrical Engineering, supervising the Computer Security Group. He is also affiliated with the Department of Computer Science. Research focuses on commodity hardware and operating systems security Teaching: Computer Engineering (BSc 2022–2025), Hardware Security (MSc 2016–2025), Advanced Operating Systems (MSc 2016–2019) Research Interests: Razavi's work bridges computer systems and security, emphasizing microarchitectural vulnerabilities, hardware exploitation, and security verification. His group develops tools for analyzing hardware-software interactions and mitigating memory attacks like Rowhammer. Scientific Awards: Distinguished/Best Paper Awards at IEEE S&P, USENIX Security, MICRO Five Pwnies Awards for innovative research Dutch Veni Grant, ERC Starting Grant Jochen Liedtke Young Researcher Award Golden Owl Teaching Award (2022) ETH Medal, Intel Bounty Reward, BlackHat USA Recognition
Giacomo Indiveri is a dual Professor at the Faculty of Science of the University of Zurich and the Department of Information Technology and Electrical Engineering of ETH Zurich . He serves as the Director of the Institute of Neuroinformatics at both institutions. Indiveri holds an M.Sc. in Electrical Engineering (1992) from the University of Genoa and a Ph.D. in Computer Science (2004) from the same university. Primary Affiliation: University of Zurich (Faculty of Science, Institute of Neuroinformatics) Secondary Affiliation: ETH Zurich (Department of Information Technology and Electrical Engineering) Indiveri's research bridges neuroscience , computer science , and machine learning to develop neuromorphic cognitive systems . His work focuses on spike-based learning , recurrent neural networks , and analog/digital circuit design for real-time sensory-motor systems . He integrates emerging memory technologies into fault-tolerant event-based architectures, enabling brain-inspired computing paradigms in applications like robotics and medical monitoring. His recent publications emphasize neuromorphic hardware for epileptic seizure detection , spiking neural networks in robotic painting , and scalable processors with on-chip learning . These works explore biologically plausible neurons , delay lines , and memory arrays for temporal processing, with applications in healthcare , edge computing , and adaptive control . Scientific Awards & Recognitions: 2021 IEEE Biomedical Circuits and Systems Best Paper Award Senior Member of IEEE Society ERC Fellow with three European Research Council grants Indiveri's group at the Institute of Neuroinformatics develops event-based systems for real-world validation of brain-inspired computing. His work includes multi-core processors , feedback optimizers , and dynamic routing architectures , supported by grants for advancing neuromorphic technologies .
Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.
Jean-Claude Besse is a Lecturer in the Department of Physics at ETH Zürich, specializing in superconducting circuits and quantum optics. His research focuses on quantum computing, microwave photonics, and artificial atoms. Research Interests: Besse works on the fabrication of superconducting circuits, modular quantum computing processors, and microwave quantum optics using artificial atoms. His work includes single-photon detection, parity measurements, entanglement stabilization, and quantum networking. He has developed technologies like high-fidelity multiplexed readout and tunable ZZ gates. Key Contributions: Besse led breakthroughs in non-destructive single-photon detection, deterministic remote entanglement, and loophole-free Bell inequality violations. His research enables error-corrected quantum communication protocols and scalable microwave quantum systems. Publications Trends: Recent articles emphasize modular quantum architectures, entanglement stabilization, and microwave photon engineering. Topics include cluster state generation, defect mode mitigation, and reinforcement learning for quantum feedback systems. Labs & Teams: Affiliated with the Laboratorium für Festkörperphysik at ETH Zürich, Besse contributes to advancing superconducting quantum technologies and microwave quantum optics.
Andras Kis is a Full Professor at the École Polytechnique Fédérale de Lausanne (EPFL), affiliated with the School of Engineering (STI) across multiple institutes including the Institute of Electrical Engineering (IEL), Institute of Materials Science (IMX), and teaching programs in Electrical Engineering (SEL-ENS). He leads the Laboratory of Nanoscale Electronics and Structures (LANES) and serves on the PhD program committee for Microsystems and Microelectronics. PhD, EPFL (2003) MS, Physics, University of Zagreb (1999) Baccalaureate, MIOC High School Research Focus: Pioneering work on 2D materials for electronic and optoelectronic devices, particularly transition metal dichalcogenides like MoS2 and PtSe2. His research spans: Transistor design with atomically thin semiconductors Excitonic devices and valleytronics Nanofluidics and ionic logic Optical properties of 2D heterostructures Scalable fabrication of 2D materials Defect engineering and doping techniques Scientific Impact: Based on analysis of 15 most recent publications, his work focuses on advancing 2D materials for next-generation electronics through innovations in: Van der Waals heterostructures Thermoelectric and optoelectronic applications Nanofabrication techniques Spintronic and quantum transport phenomena Memristive and neuromorphic devices Characterization of electronic and optical properties Awards & Recognition: Fellow of the Institute of Electrical and Electronics Engineers (IEEE) Lotfi A. Zadeh Award for Emerging Technologies (2024) Highly Cited Researcher (Clarivate Analytics) Teaching & Academic Leadership: Currently teaching courses including Lab in Nanoelectronics , Physical Models for Micro and Nanosystems , and Semiconductor Devices II . He has supervised over 20 PhD students in his research group at EPFL. Laboratory & Collaborations: Directs the Laboratory of Nanoscale Electronics and Structures (LANES) which focuses on fundamental and applied research in 2D materials and nanoelectronic devices. His work bridges materials science, condensed matter physics, and microelectronics engineering.
Mirjana Stojilovic is a Researcher at École Polytechnique Fédérale de Lausanne (EPFL) in the School of Computer and Communication Sciences (IC), specifically within the Institute of Computer Engineering (IINFCOM) and the Parallel Systems Architecture Laboratory (PARSA). She also serves as a Lecturer in the SSC - Teaching department at EPFL. Her office is located at INJ 235, Station 14, 1015 Lausanne, Switzerland. Mirjana Stojilović received her Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. Her academic journey includes collaborating with the Processor Architecture Laboratory at EPFL as a Guest Researcher from 2010 to 2013, working at the University of Applied Sciences Western Switzerland as a senior researcher from 2013 to 2016, and joining the Parallel Systems Architecture Lab at EPFL in October 2016. Dr. Stojilovic's research spans field-programmable technology, electronic design automation (EDA), and electrical-level attacks and countermeasures for reconfigurable hardware. Her work bridges the gap between hardware design and security, with a particular focus on vulnerability analysis and protection mechanisms for FPGA-based systems in cloud environments. She has made significant contributions to understanding side-channel attacks, fault injection techniques, and secure multi-tenancy solutions for shared hardware resources. Her extensive publication record reveals a clear research trajectory from traditional FPGA design and EDA topics toward increasingly security-focused investigations. Recent work demonstrates deep expertise in power analysis attacks, hardware trojans, and countermeasures for cloud-based FPGA systems, reflecting the growing importance of hardware security in distributed computing environments. Scientific Awards and Recognitions: Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016) Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016) Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012) EPFL School of Computer and Communication Sciences (IC) Teaching Award (2015) Nominated for Best Paper Award at the International Conference on Field-Programmable Technology (FPT) (2020) Dr. Stojilovic has advised numerous PhD students including Coulon Louis, Pirayadi Rouzbeh, and Shrivastava Shashwat, along with past EPFL PhD students Glamocanin Ognjen and Mahmoud Dina. She has supervised dozens of semester and diploma projects focusing on hardware security, FPGAs, design automation, side-channel attacks, and cloud computing. Her service to the academic community includes serving on program committees for FPGA, FCCM, FPL, and DATE conferences, reviewing for multiple IEEE and ACM journals, and acting as associate editor for IEEE ESL and ACM TRETS. As a member of the Parallel Systems Architecture Laboratory at EPFL, Dr. Stojilovic leads research projects investigating security aspects of reconfigurable hardware systems. Her team works at the intersection of computer architecture, electronic design automation, and hardware security, with particular emphasis on vulnerabilities and protections for shared FPGA resources in cloud environments.
Dr. Ivan Puddu is a Researcher affiliated with the Institute for Information Security at ETH Zürich. His work focuses on advancing cybersecurity, particularly in the realms of Trusted Execution Environments (TEEs), hardware security, and privacy-preserving technologies. He explores vulnerabilities in modern computing systems, including attacks on enclave-based security mechanisms and side-channel exploits. His research also addresses distributed systems, blockchain, and FPGA-accelerated architectures, aiming to enhance system sovereignty and data integrity. Notable contributions include studies on code confidentiality in TEEs, disaggregated memory systems, and mitigating security threats in low-power networks.
Dr. Alessandro Ottaviano is a Researcher affiliated with the Department of Digital Integrated Circuits and Systems at ETH Zürich. His work focuses on advanced computer architecture and embedded systems, particularly in the domains of RISC-V processors, real-time systems, and heterogeneous computing. He contributes to the design of time-predictable virtual memory solutions, mixed-criticality systems, and energy-efficient hardware-software interfaces. Key research areas include modular processor architectures, hardware monitoring for safety-critical applications, and power management in high-performance computing (HPC) systems. His recent projects involve developing controllers for 2.5D systems-in-package and creating open-source networking solutions for mixed-criticality environments. Ottaviano’s work often emphasizes open-source hardware design and scalable system-level approaches to address challenges in autonomous systems and edge computing. He collaborates on advancements in interrupt handling for virtualized systems, peripheral event linking for IoT devices, and FPGA-based thermal emulation for many-core processors. His research bridges theoretical computer architecture principles with practical implementations in embedded and real-time systems.
Kyojin Choo is a Tenure Track Assistant Professor at the Swiss Federal Institute of Technology Lausanne (EPFL) in the School of Engineering , affiliated with the Mixed-Signal Integrated Circuits Lab (MSIC-LAB). He also holds teaching roles in Microengineering and Electrical and Electronics Engineering at EPFL. B.S. and M.S. in Electrical Engineering from Seoul National University (2007, 2009) Ph.D. in Electrical Engineering from the University of Michigan (2018) His research focuses on charge-domain analog/mixed-signal circuits , low-power sensor interfaces , and compact ADCs for IoT, wearables, and millimeter-scale systems. He has pioneered charge-injection cell techniques for energy-efficient circuits in energy management, sensor front-ends, and communication. His work emphasizes reducing power consumption to nanowatt levels while enabling ultra-compact designs. His recent publications highlight advancements in compact SAR ADCs , low-power MEMS accelerometers , millimeter-scale imaging systems , and ultra-low-power timing generators . His research integrates charge-domain circuit design with sensor interface optimization , energy harvesting , and high-speed link architectures . He holds over 20 US patents and has taught courses in Microengineering and Electrical Engineering at EPFL. His group (MSIC-LAB) addresses challenges in battery-free sensor design, power-constrained system scaling, and commercialization of wearables with unconventional form factors.
David Atienza is a Professor in the Department of Electrical Engineering at the School of Engineering, Swiss Federal Institute of Technology in Lausanne (EPFL), renowned for pioneering embedded systems education and research in ultra-low power computing. His innovative teaching methods, including using Nintendo DS consoles and smartphones to teach embedded systems, earned him the 2015 EPFL Teaching Award in Electrical Engineering. His research focuses on Embedded Systems , Edge AI , and Wearable Healthcare , with breakthroughs in energy-efficient hardware-software co-design for biomedical applications. Key contributions include open-source platforms like X-HEEP and HEEPocrates for ultra-low power edge computing, and frameworks like SzCORE for seizure detection benchmarking. His work bridges computer architecture with real-world healthcare challenges, emphasizing privacy-preserving algorithms and sustainable computing. Recent publications (2023-2025) reveal a dominant trend toward biomedical edge AI and sustainable computing , with 70% of articles targeting healthcare wearables (seizure detection, cough monitoring) and 30% addressing energy efficiency in data centers and edge devices. His research consistently integrates open-hardware principles (RISC-V) with novel algorithm-hardware co-design. Awards include: 2015 EPFL Teaching Award in Electrical Engineering section While specific advising details are unreported, his extensive publication record and leadership in multi-partner projects like Sustainable Textile Electronics (STELEC) indicate active graduate supervision and significant research funding. His group develops open-source hardware frameworks used globally in academia and industry. He leads the Embedded Systems Laboratory at EPFL, driving projects in ultra-low power RISC-V architectures, biomedical wearables, and sustainable computing. Current initiatives include carbon-aware data center frameworks and multi-modal health monitoring systems deployable on commercial wearables.
Pejman Lotfi-Kamran is an Associate Professor at the School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, where he also serves as the head of the school and director of Turin Cloud Services. His research focuses on computer architecture, systems, approximate computing, and cloud computing, with an emphasis on performance and energy efficiency for big-data applications. His educational background includes: Ph.D. in Computer Science, EPFL (2013) M.Sc. in Electrical and Computer Engineering, University of Tehran (2005) B.Sc. in Electrical and Computer Engineering, University of Tehran (2002) Lotfi-Kamran's research spans computer architecture innovations, including data and instruction prefetching, networks-on-chip, coherence protocols, and many-core processor design. He has pioneered work on scale-out processors, neural acceleration for GPUs, and approximate computing frameworks. His publications appear in top venues such as ISCA, HPCA, MICRO, and IEEE/ACM journals. His recent articles reflect a strong trend in improving system performance through intelligent prefetching, efficient NoC designs, and energy-aware architectures. Key themes include reducing frontend bottlenecks, optimizing cache behavior, and enhancing data delivery in large-scale systems. His work often combines cross-stack insights with hardware-software co-design for real-world impact. Scientific awards and recognitions include: 2017 CADS Best Paper Award 2016 Young Faculty Award from Iran's National Elites Foundation 2012-2013 Intel Ph.D. Fellowship 2012 and 2011 HiPEAC Paper Awards 2011 HPCA Best Student Paper Finalist Multiple academic honors from University of Tehran He has advised several graduate students including Paria Darbani, Ali Ansari, Mohammad Bakhshalipour, and Farid Samandi, many of whom have co-authored significant papers. His teaching spans institutions like Sharif University of Technology, Iran University of Science and Technology, and EPFL, covering advanced computer architecture and multiprocessor systems. He has led research projects such as AxBench and CloudSuite on Simics, and contributed to national initiatives like Iran’s National Grid. He is actively involved in tool development and continues to shape research in next-generation computing systems. He leads the Turin Cloud Services initiative at IPM and is deeply engaged in both theoretical and applied aspects of computer systems research, with ongoing work in neural acceleration, approximate computing, and scalable architectures.
Laura Pozzi is a Full Professor at the Faculty of Informatics, Università della Svizzera italiana (USI), Switzerland, since 2015. She previously held positions as Associate Professor (2011–2015) and Assistant Professor (2005–2011) at USI. Prior to joining USI, she was a postdoctoral researcher at EPFL's Processor Architecture Laboratory (2001–2005), a research engineer at STMicroelectronics (2000), and an Industrial Visitor at UC Berkeley (2000). Education: MS and PhD in Computer Engineering from Politecnico di Milano, Italy (1996–2000). Her research focuses on the interaction between compiler and architecture design, particularly in embedded systems , with key areas including approximate computing , coarse-grained reconfigurable arrays (CGRAs) , high-level synthesis (HLS) , and fuzz testing . She has led projects on automated design space exploration, compiler optimizations for reconfigurable architectures, and error estimation in approximate circuits. Recent Publications span topics like SAT-based mapping for CGRAs , grammar-based fuzzing of shell interpreters , and approximate logic synthesis , reflecting her interdisciplinary work bridging hardware/software co-design and software verification. Scientific Awards: Credit Swiss Best Teaching Award IEEE DAC Best Paper Award Leadership Roles: Co-Program Chair, IEEE Symposium on Application Specific Processors (SASP) Editorial Board Member, IEEE Design and Test Students: Current: Rodrigo Otoni (Postdoc), Morteza Rezaalipour (PhD), Riccardo Felici (PhD), Cristian Tirelli (PhD) Alumni: Ilaria Scarabottolo (PhD/Postdoc), Lorenzo Ferretti (PhD/Postdoc), Georgios Zacharopoulos (PhD), Giovanni Ansaloni (PhD/Postdoc), Paolo Bonzini (PhD)
Andrea Guerrieri serves as an Associate Professor at the School of Engineering, University of Applied Sciences and Arts Western Switzerland Valais (HES-SO Valais-Wallis), specializing in reconfigurable computing and electronics design automation. His research has established significant industry impact through tools like DynaRapid and Dynamatic, with technology adopted by major semiconductor companies including MIPS, Intel, and AMD-Xilinx. BSc HES-SO in Industrial Systems - System-on-Chip specialization BSC HES-SO in Computer and Communication Systems - Digital Design specialization MSc HES-SO in Engineering - Embedded Hardware and Firmware specialization Professor Guerrieri's research focuses on reconfigurable computing, electronics design automation (EDA), and security, with particular emphasis on FPGA design, high-level synthesis, and post-quantum cryptography implementations. His work bridges the gap between theoretical computer architecture and practical hardware implementations, with strong applications in space technology and embedded security systems. His recent publications demonstrate increasing focus on energy-efficient implementations for space applications and quantum-resistant cryptographic systems. Analysis of his 15 most recent publications reveals a clear research trajectory toward optimizing FPGA implementations for post-quantum cryptography and space applications. His work consistently addresses the performance bottlenecks in high-level synthesis while maintaining practical applicability for industry partners like NASA, CERN, and major semiconductor companies. The recent surge in best paper awards (three in 2024 alone) reflects growing recognition of his contributions to efficient FPGA compilation techniques and cryptographic implementations. Scientific Awards: Best Paper Award at FPL 2024 Best Paper Award at HPEC 2024 Best Paper Award at ISFPGA 2020 Outstanding Short Paper Award at IEEE HPEC 2024 Outstanding TPC Member Award at DAC 2024 IEEE Senior Member (2021) Multiple Best Paper nominations (FCCM 2022, FPL 2022, HiPEAC 2022) Professor Guerrieri actively participates in international research projects including the DyReCte project (2019-2021) on dynamically reconfigurable cryptoengines for nano-satellites. He currently chairs the Onboard Computing topic for the Swiss consortium CHEESE affiliated with NASA SSERVI and collaborates extensively with industry partners including AMD-Xilinx, NVIDIA, Arm, NASA, and CERN, as well as academic institutions like ETH Zurich and University of Geneva. His current research focuses on developing next-generation EDA tools and reconfigurable computing platforms for both terrestrial and space applications. His laboratory work centers around FPGA-based prototyping and validation, with specialized facilities for space applications testing. Professor Guerrieri leads a research team that includes Andres Upegui, Quentin Berthet, Laurent Gantel, and Gabriel Da Silva Marques, focusing on practical implementations of reconfigurable architectures for security and space applications.
