Associate Professor Joshua San Miguel leads research in computer architecture and systems at the University of Wisconsin-Madison, with an affiliate role in Computer Sciences. His work focuses on energy-efficient computing for IoT devices, microarchitecture innovations, and networks-on-chip. He holds a PhD (2017) and BASc (2012) from the University of Toronto. Education: PhD in Electrical & Computer Engineering, University of Toronto (2017) BASc in Engineering Science (ECE), University of Toronto (2012) Research Interests: Approximate computing for energy harvesting systems Branch prediction and value prediction in processors Cache architectures and networks-on-chip for many-core processors Intermittent computing resilience His recent work emphasizes value-level parallelism (Carat/uSystolic), RTL simulation acceleration (TaroRTL), and personalized neural network inference (CAP’NN). His research has been recognized with the NSF CAREER Award (2021) and multiple IEEE Micro Top Picks. Grants & Advising: Active in supervising advanced independent studies and master’s/dissertation research. Extensive grant funding includes the NSF CAREER Award and the Grainger Faculty Scholarship. Labs & Teams: Leads research groups focused on approximate computing and energy-efficient architectures within the Electrical & Computer Engineering department.
Prof. Dr. rer. nat. Rainer Leupers is a faculty member at RWTH Aachen University, chairing the Department of Software for Systems on Silicon. His research focuses on embedded systems, hardware-software co-design, virtual prototyping, and security in computing-in-memory architectures. He has published extensively on RRAM accelerators, logic locking, and neuromorphic security. Chair of Software for Systems on Silicon Research in hardware security and deep learning accelerators Recent publications on cross-tool virtual frameworks and thermal side-channel attacks His work bridges system-level modeling with practical security implementations, emphasizing reliability and performance in heterogeneous computing environments. Key trends in his 2025-2023 articles include compute-in-memory optimization, neural network inference efficiency, and security vulnerabilities in emerging hardware. Awards and formal recognitions are not explicitly detailed in the provided materials. He has not directly mentioned advising students or research grants in the given text fragments. The chair's contact information includes an office at ICT Cube 1, Electrical Engineering, Aachen, with direct email and website links.
Brandon Lucia is a Full Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University's College of Engineering. He leads the abstract research group focusing on the intersection of computer architecture, systems, and programming languages. His work bridges theoretical foundations with practical implementations in energy-constrained environments. Lucia's research centers on intermittent computing systems and edge computing in extreme environments. His work on energy-harvesting systems has established fundamental principles for batteryless computing, while his orbital edge computing research pioneers computational intelligence for nanosatellite constellations. These research thrusts address critical challenges in reliability, efficiency, and programmability for systems operating under severe power constraints. His publication record shows a clear evolution from foundational work on intermittent computing models to sophisticated applications in space computing and edge intelligence. Recent publications demonstrate increasing integration of dataflow architectures with energy-harvesting constraints, particularly in satellite constellations where computational resources must be managed across distributed, power-constrained platforms operating in extreme environments. NSF CAREER Award (2017) IEEE TCCA Young Computer Architect Award (2019) Sloan Foundation Fellowship (2021) ASPLOS Best Paper Awards (2018, 2020) OOPSLA Distinguished Paper and Artifact Awards (2015) Lucia actively mentors numerous PhD students including Brad Denby, Zhuo Cheng, and Emily Ruppel, many of whom contribute significantly to his research program. His abstract research group maintains strong industry connections while pursuing fundamental advances in computing systems. The group has developed multiple open-source tools including Legerdemain for program analysis and MultiCacheSim for cache coherence simulation. His laboratory work spans from theoretical foundations of intermittent computing to practical implementations in space systems. Current projects include computational nanosatellite constellations, energy-minimal dataflow architectures, and secure edge computing systems that operate reliably despite frequent power failures.
Fan Yao is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Central Florida's College of Engineering and Computer Science. She received her Ph.D. in Computer Engineering from The George Washington University in 2018 and currently leads the Computer Architecture and Systems Research (CASR) lab. Her research focuses on the intersection of computer architecture, security, and machine learning, with particular emphasis on hardware-based security vulnerabilities and defenses. Dr. Yao's research interests span computer architecture, hardware and system security, AI security, energy-efficient computing, and cloud computing. Her work addresses critical security challenges in modern computing systems, particularly focusing on microarchitecture attacks, hardware-based model tampering in deep learning systems, and information leakage threats in emerging non-volatile memory systems. She has developed innovative defense mechanisms against cache timing channels, branch predictor vulnerabilities, and GPU-based side channels. Her recent publications demonstrate a strong focus on AI security (particularly Deep Neural Network vulnerabilities), hardware security (including cache and branch predictor attacks), and secure memory architectures. The research shows an evolution from traditional computer architecture topics toward the security implications of AI hardware and emerging memory technologies, with increasing emphasis on practical attacks and defenses in real-world systems. NSF GW I-Corps Site Grant Award, 2018 Best Dissertation Award, GWU, 2018 The Norris & Betty Hekimian Engineering Endowment Fellowship, GWU, 2017 Top Picks in Hardware and Embedded Security, 2019 NSF CAREER project award, 2024 Dr. Yao currently leads multiple NSF-funded research projects including 'Understanding and Taming Deterministic Model Bit Flip Attacks in Deep Neural Networks' (NSF SaTC, 2020-2023), 'Towards Secure-By-Design Integration of Emerging Non-Volatile Memory in Future System' (NSF CNS, 2020-2023), and 'Architecting Secure-by-Design Memristor-Based Memories' (NSF CNS, 2019-2022). She has successfully mentored numerous PhD students, many of whom appear as first authors on top-tier conference publications, demonstrating her commitment to graduate education and research mentorship. As the leader of the CASR lab, Dr. Yao oversees a vibrant research group focused on building secure-by-design, efficient, and advanced future systems through novel techniques spanning hardware, computer architecture, and systems. The lab actively publishes at top computer architecture and security conferences including ISCA, MICRO, HPCA, IEEE S&P, and USENIX Security, with multiple papers accepted to these venues annually. The group has developed several influential tools and frameworks for security analysis, including proof-of-concept code for BranchSpec exploits that has been widely cited in the hardware security community.
Francesc Moll Echeto is an Associate Professor at the Universitat Politècnica de Catalunya (UPC), affiliated with the Departament d'Enginyeria Electrònica and the Escola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona. He leads the HIPICS research group focused on high-performance integrated circuits and systems design. His expertise spans energy harvesting, low-power electronics, process variability management, and secure circuit design. He coordinates the Doctorat en Enginyeria Electrònica program and has coordinated EU-funded projects like the European Processor Initiative (EPI). Education: M.S. in Physics, Universitat de les Illes Balears, 1991 Ph.D. in Electronic Engineering, Universitat Politècnica de Catalunya, 1995 Research Focus: His work addresses energy-efficient computing, including: - Design of circuits tolerant to manufacturing variability - Energy harvesting from mechanical and RF sources - Secure hardware countermeasures against side-channel attacks - RISC-V architecture implementations in advanced technologies - Edge computing and autonomous sensor systems Grants & Collaborations: Coordinator of R&D projects like 'ARQUITECTURA DE COMPUTADORES DE ALTAS PRESTACIONES' (PID2023-146511NB-I00) Part of the Barcelona Zettascale Lab consortium Collaborations with Barcelona Supercomputing Center and industry partners Awards: HiPEAC Paper Award (2023, 2024) for innovations in vector processing and DNN acceleration Labs/Teams: Leads the HIPICS group and the EFRICS subgroup, collaborating on EU-funded initiatives like the European Processor Initiative. Active in open-source silicon projects (e.g., Sargantana RISC-V processor).
James Tuck is a Professor and Senior Associate Department Head for Undergraduate Affairs in the Department of Electrical and Computer Engineering at NC State University. He holds a BE from Vanderbilt University, and MS and PhD from the University of Illinois at Urbana-Champaign. His research focuses on computer architecture, compiler design, and DNA-based data storage, with notable contributions to chip multiprocessors and speculative execution. He has been recognized with two IEEE Micro Top Picks Paper Awards and the William F. Lane Outstanding Teaching Award. Education: Ph.D. in Computer Science, University of Illinois at Urbana-Champaign (2007) MS in Electrical and Computer Engineering, University of Illinois at Urbana-Champaign (2003) BE in Computer Engineering, Vanderbilt University (1999) Research Interests: Computer Architecture and Systems Compiler Design for Multiprocessors Hardware Support for Speculative Execution Advances in DNA Data Storage Non-Volatile Memory Systems Recent work emphasizes DNA storage scalability and security, including frameworks like FrameD and innovations in nanopore decoding. His articles span hardware optimization, persistent memory security, and biochemical storage solutions. Awards highlight both technical and pedagogical excellence. Advising and Grants: Leadership in Undergraduate Engineering Affairs NSF grants for DNA storage and memory systems Labs/Teams: Member of Undergraduate Affairs Team in NC State ECE Collaborations with Chemical and Biomolecular Engineering
Ashish Venkat is an Associate Professor in the Department of Computer Science at the University of Virginia, part of the School of Engineering and Applied Science. He holds a Ph.D. from UC San Diego and has established himself as a leading researcher in computer architecture, compilers, and computer security. Research Interests: His research focuses on cross-disciplinary hardware and software techniques to build secure, high-performance computing systems. He investigates robust exploit mitigations that maintain energy efficiency and programmability, with a particular emphasis on speculative execution, memory safety, hardware security, and privacy-preserving computing. He also explores the application of machine learning to detect security threats and model execution behavior. Publication Trends: His recent publications (2020–2025) demonstrate a strong focus on hardware-based security, particularly microarchitectural vulnerabilities (e.g., micro-op cache attacks), memory safety via microcode capabilities, and secure accelerators for bioinformatics. There is a consistent trend of publishing in top-tier venues like ISCA, MICRO, IEEE S&P, and USENIX Security, often featuring novel hardware/software co-design solutions. Scientific Awards: NSF CAREER Award (2023) NSF CRII Award (2018) IEEE Micro Top Pick (2019) IEEE Design & Test Top Pick (2020, 2021) HPCA Best Paper Runner-Up (2019) DATE Best Paper Nominee (2023) UVA Research Achievement Award (2023) ISCA Prolific Author of the Decade (2013–2022) Advising and Grants: He actively mentors graduate and undergraduate students, many of whom have pursued advanced degrees or joined leading tech companies. He has secured significant funding as PI or co-PI from NSF, DARPA, SRC, and Intel, including a $4.9M DARPA HERCULES grant and an NSF CAREER award. His projects focus on holistic security solutions, speculative optimization, and privacy-preserving machine learning frameworks. Labs and Teams: He leads a research group focused on secure and efficient computing systems, collaborating with researchers at institutions like UC San Diego, UC Riverside, and UC Irvine, as well as industry partners including Intel and IBM.
Marco Vacca is an Associate Professor in the Department of Electronics and Telecommunications (DET) at Politecnico di Torino and a member of the Interdepartmental Center PIC4SeR - PoliTO Interdepartmental Centre for Service Robotics. His work bridges electronics, nanotechnology, and computing architecture with a focus on innovative solutions to the memory wall problem. His research spans Logic-in-memory computing, Machine learning hardware acceleration, and Nanocomputing with specific emphasis on circuit architectures for probabilistic computing, magnetic devices, hybrid technologies integration, and CAD tools for emerging technologies. Dr. Vacca leads research in RISC-V extensions, hardware accelerators for AI, and autonomous robot systems for agricultural applications through the VLSILAB research group. Recent publications reveal a strong trend toward solving fundamental computing challenges through nanoscale innovations, particularly in memory-centric architectures, molecular field-coupled computing, and novel transistor technologies. His work demonstrates how logic-in-memory approaches can overcome traditional von Neumann limitations while improving energy efficiency for AI workloads. Editorial board member of ELECTRONICS (2021-2023) Program committee member for Design, Automation and Test in Europe Conference (DATE) 2020-2021 Dr. Vacca supervises PhD student Alessandro Varaldi working on 'Hardware AI Accelerators for Automotive Applications' and has led significant research projects including 'Device for Storage and Processing Data and Related Method' (2020-2021) and 'Quantum Computing and Quantum Communication: State of the Art and Applications in the Telco Sector' (2020). His grant portfolio shows strong industry and competitive funding support. As a core member of the VLSILAB research group, Dr. Vacca contributes to advancing VLSI theory and design applications with particular focus on implementing Big Data, Machine Learning, and Neural Networks in specialized hardware architectures that push the boundaries of conventional computing.
Donald Yeung is a Professor and Associate Chair for Undergraduate Education in the Department of Electrical and Computer Engineering at the University of Maryland , with an additional appointment as Affiliate Professor in the Department of Computer Science . His research focuses on Computer Architecture , particularly in memory systems , 3D integration , energy-efficient processors , and parallel processing . He leads projects like Monolithic 3D Integration of CPU and Main Memory and Approximate Computing . Recent work emphasizes ReRAM-based memory architectures , extreme-scale processor design , and micro-fluidic cooling solutions for 3D CPUs. His teaching includes courses like ENE 646: Computer Architecture and ENE 150: Intermediate Programming Concepts . Key achievements include the Best Paper Award at MULTIPROG-2017 and contributions to IEEE Micro and ACM Transactions . His research spans cache optimization , reuse distance analysis , and directory coherence protocols . Current grants include funding for heterogeneous microprocessor parallelism and low-power system design . Advises graduate students Yinuo Wang and Hung-Yu Yeh, and collaborates with teams like the UMIACS Technical Report Group . His lab focuses on memory-centric computing and scalable multicore systems .
Keiji Kimura is a Professor in the Department of Computer Science and Engineering at Waseda University's Faculty of Science and Engineering, School of Fundamental Science and Engineering. He earned his Doctor of Engineering from Waseda University and has held academic positions at the university since 1999, progressing from Research Associate to Assistant Professor (2004-2005), Associate Professor (2005-2012), and Professor (2012-present). He is affiliated with multiple professional organizations including ACM, IEEE Computer Society, The Institute of Electronics, Information and Communication Engineers, and Information Processing Society of Japan. His research focuses on computer architecture, particularly parallel computing systems and compiler technology. Kimura has made significant contributions to the development of the OSCAR (Optimally Scheduled Advanced Multiprocessor) automatic parallelizing compiler framework. His work spans multiple areas including multicore processor architecture, power reduction techniques for embedded systems, non-volatile memory systems, and parallelization methods for heterogeneous architectures. His research interests specifically include Multiprocessor Architecture and Parallelizing Compiler development, with applications in real-time systems and energy-efficient computing. Analysis of his recent publications reveals a strong focus on practical implementations of parallel computing technologies across diverse hardware platforms including RISC-V, ARM, and heterogeneous multicore systems. His work demonstrates a consistent trajectory from theoretical compiler development toward practical applications in embedded systems, security, and non-volatile memory technologies. The publications show increasing emphasis on RISC-V architecture, persistent memory programming, and power-efficient computing solutions. MEXT Award for Science and Technology (Research category), 2014.04 Ministry of Education, Culture, Sports, Science and Technology (MEXT) Kimura has served on numerous prestigious conference program committees including PACT, IPDPS, HPCA, and LCPC. His research has been supported through collaborations with major technology companies and government initiatives such as the METI/NEDO project entitled "Multicore Technology for Realtime Consumer Electronics." His work with the OSCAR compiler framework has demonstrated significant performance improvements and power reductions in real-world applications. He leads research in the APAL laboratory (http://www.apal.cs.waseda.ac.jp/) at Waseda University, focusing on advanced parallel processing technologies. His team works on compiler-directed approaches to solve challenges in heterogeneous multicore architectures, with particular emphasis on making parallel programming more accessible while optimizing for both performance and power efficiency. Current research directions include RISC-V secure boot verification, non-volatile memory systems, and GPU-based persistent memory solutions.
Summary Role & Affiliation: Mahmut Taylan Kandemir is a Professor in the Department of Computer Science and Engineering at Pennsylvania State University. He is a member of the Microsystems Design Lab and has held roles such as Graduate Program Coordinator. His research focuses on optimizing compilers, runtime systems, embedded systems, and storage technologies. Education: B.S. and M.S. from Istanbul Technical University (Computer Engineering), Ph.D. from Syracuse University (Computer Science). Research Interests: Kandemir’s work spans compiler optimization, energy-efficient architectures, non-volatile memory systems, and cloud storage. His research has been funded by NSF, DARPA, and industry partners like Intel and Microsoft. Articles & Contributions: Over 150 journal papers and 650+ conference publications, covering topics like compiler-driven storage efficiency, 3D NAND SSD optimization, and approximate computing frameworks. Awards: NSF Career Award, Penn State Premier Research Award, IEEE Fellow, and multiple best paper awards. His contributions include compiler tools and storage systems for high-performance computing. Advising & Grants: Advised 32 Ph.D. and 20 M.S. students. Active in program committees for conferences like MICRO, ISCA, and HPCA. Current grants focus on cloud resource management and emerging memory technologies. Labs & Collaborations: Leads projects in collaboration with Argonne National Lab, NVIDIA, and Intel. His work bridges academia and industry, addressing challenges in multicore and embedded systems.
Prof. Timo Hönig is a Professor leading the Bochum Operating Systems and System Software (BOSS) Research Group at Ruhr-Universität Bochum (RUB). Previously, he served as an Assistant Professor at Friedrich-Alexander-University Erlangen-Nürnberg (FAU), where he was part of Department of Computer Science 4. His research focuses on Energy-Aware Computing Systems, Operating Systems, and System Software design with applications in embedded and real-time systems. Key research projects include the DFG Collaborative Research Center/TR 89 (Invasive Computing) and the DFG SPP 1914 (Latency- and Resilience-Aware Networking). He has received notable awards such as the SOSP SRC Gold Medal (2019) and the ISORC Best Paper Award (2017). He actively contributes to conferences like ACM EuroSys and USENIX ATC, and has led initiatives like the Albatross runtime system for energy-efficient HPC clusters. Teaching includes courses on Energy-Aware Computing and Operating Systems Technology. His work bridges theoretical system software design with practical applications in energy efficiency and heterogeneous architectures. The BOSS group explores future system software challenges for many-core and NVM-based systems.
Furat Al-Obaidy is a Lecturer in the Department of Electrical and Computer Engineering at the University of Michigan-Dearborn's College of Engineering and Computer Science. His expertise spans machine learning, intelligent systems, VLSI circuits, multi-core systems, FPGA architecture, and deep learning applications. PhD in Electrical & Computer Engineering from Ryerson University (2021) MSc in Electrical & Computer Engineering from Ryerson University (2016) MSc in Control & Instrumentation Engineering from University of Technology, Baghdad (1999) BSc in Control & Systems Engineering from University of Technology, Baghdad (1996) His research focuses on power-aware computing systems, thermal imaging for IC testing, hybrid cache architectures, and AI-driven network optimization. He has published extensively on topics including GPGPU power management, 3D NoC routing, and wireless sensor networks. His recent publications highlight applications of neural networks in cache optimization, FPGA architecture, and thermal imaging for hardware diagnostics. Earlier work includes control system simulations for wind turbines and power factor analysis in electrical circuits. Ryerson Graduate Development Award (2021) Ontario Graduate Scholarship Award (OGS) (2020) Ryerson Graduate Fellowship (2018) Graduate Research Excellence Award (2017) Queen Elizabeth II Graduate Scholarship in Science and Technology (2017)
Zhu Zhichun is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Chicago, College of Engineering. His primary research focuses on computer architecture, performance modeling, and energy-efficient designing of computer systems. Ph.D. in Computer Science from College of William and Mary (2003) B.Sc. in Computer Engineering from Huazhong University of Science and Technology, China (1992) His research interests center around computer architecture , particularly in performance modeling and evaluation , energy-efficiency computer designs , and memory system optimization . He investigates techniques for improving power efficiency, thermal management, and bandwidth utilization in DRAM and PCM memory systems, with a focus on multicore processors and low-power designs. Zhu's publications demonstrate consistent work in memory architecture and power-efficient computing . Key trends include thermal modeling , DRAM optimization , and hybrid memory systems . His collaborations with Zhao Zhang, Jiang Lin, and other researchers highlight interdisciplinary approaches to solving computer architecture challenges.
Ali José Mashtizadeh is an Associate Professor at the Cheriton School of Computer Science, University of Waterloo. His research focuses on operating systems, distributed systems, and storage, with expertise in system reliability, network optimization, and concurrent programming. Education: Ph.D., Computer Science, Stanford University (2017) M.S., Computer Science, Stanford University (2017) M.Eng., Electrical Engineering and Computer Science, MIT (2007) B.S., Electrical Engineering, MIT (2006) His research centers on designing scalable and reliable systems, with recent publications exploring TCP network frameworks, in-memory data persistence, and microsecond-scale scheduling. Key themes include optimizing tail latency, neutralization-based memory reclamation, and fault-tolerant distributed services. His articles consistently demonstrate innovations in low-latency networking, operating system architecture, and cloud infrastructure, with recent emphasis on serverless benchmarks and processor customization. No scientific awards or advising relationships are detailed in the provided materials.
