Massachusetts Institute of TechnologyUnited States
Tomas Palacios is a Professor of Electrical Engineering at the Massachusetts Institute of Technology (MIT) , where he directs the Center for Graphene Devices and 2D Systems and leads the Microsystems Technology Laboratories (MTL). His research focuses on pushing the boundaries of microelectronics through novel semiconductor materials and device architectures, including Gallium Nitride (GaN) and 2D materials like graphene and molybdenum disulfide (MoS2). Professor, MIT Electrical Engineering and Computer Science Director, MIT Center for Graphene Devices and 2D Systems Clarence J. LeBel Professor, MIT Faculty Director, Northeast Microelectronics Internship Program (NMIP) Research Interests span multiple cutting-edge domains: High-frequency electronics (>300 GHz) for 6G and quantum applications High-voltage power devices (600V–10kV) for energy conversion Post-silicon logic devices using 2D materials High-temperature electronics (e.g., Venus rover applications) Distributed neural networks on large-area 2D materials Graphene-based biosensors and chemical detection systems Scientific Contributions include: Double recipient of the IEEE George Smith Award for groundbreaking GaN transistor work Co-invented first MoS2 electronic circuits Developed world’s first Wi-Fi-to-electricity conversion antenna Led MIT’s Microsystems Technology Laboratories since 2021 Advising Philosophy emphasizes cross-layer expertise, with students gaining experience from materials synthesis to system-level prototyping. His lab has incubated startups like Vertical Horizons , focused on GaN power devices for AI and EVs.
Priyanka Raina is an Assistant Professor of Electrical Engineering at Stanford University, with a courtesy appointment in Computer Science. She leads the Stanford Accelerate research group, focusing on domain-specific hardware architectures and agile hardware-software co-design. Her work emphasizes high-performance, energy-efficient accelerators for emerging technologies. Education: B.Tech. from IIT Delhi (2011), M.S. and Ph.D. from MIT (2013/2018). Postdoctoral experience includes NVIDIA Research (2018) and Amazon Visiting Academic (2023–present). Awards include the Sloan Research Fellowship (2024), NSF CAREER Award (2023), and Terman Faculty Fellowship (2018). Research Interests: Domain-specific architectures, near-memory computing, design productivity, and machine learning acceleration. Her group develops frameworks like AHA (Agile Hardware) for efficient accelerator design and compilers. Awards: Over 10 major awards, including best paper recognitions at VLSI, MICRO, and JSSC. Active roles as Associate Editor for IEEE JSSC and Program Chair for IEEE Hot Chips (2020). Advising & Teaching: Supervises multiple PhD and MS students in hardware design, CGRAs, and ML accelerators. Teaches VLSI design courses (EE271/272/372) and oversees independent studies in embedded systems and chip design. Labs & Collaborations: Affiliated with Stanford PORTAL Center, AHA Center, and SystemX Alliance. Projects include MINOTAUR (edge AI accelerator), Amber (CGRA-based SoC), and EMBER (RRAM macros).
Haitong Li is an Assistant Professor in the School of Electrical and Computer Engineering at Purdue University's College of Engineering, joining the faculty in 2022. His research bridges nanoelectronic devices, integrated circuits, and nanotechnology-inspired AI hardware to address critical challenges in energy-efficient artificial intelligence systems. Education: Ph.D. in Electrical Engineering, Stanford University Research Interests: Dr. Li pioneers emerging memory technologies—particularly Resistive RAM (RRAM)—for in-memory computing and neuromorphic systems. His work focuses on 3D monolithic integration of RRAM and gain cell memory with CMOS to enable edge AI, with recent breakthroughs in hardware acceleration for large language models and sustainable computing. Key innovations include carbon footprint prediction for LLMs and zeroth-order fine-tuning techniques. Publication Trends: Dr. Li's 2023-2025 publications reveal a strategic shift toward sustainable AI hardware, emphasizing carbon-aware LLM inference and edge deployment. His research consistently targets data movement reduction through memory-centric architectures, spanning photonic accelerators, neuro-symbolic computing, and heterogeneous 3D integration. Awards: No scientific awards were documented in the provided sources. Advising and Grants: Current advisees and grant funding details were not specified in the available materials. Labs and Teams: Research group composition and laboratory facilities were not described in the source text.
Subhasish Mitra is the William E. Ayer Professor of Electrical Engineering and Computer Science at Stanford University, holding dual appointments in both departments. He leads the Stanford Robust Systems Group and serves on the leadership team of the Microelectronics Commons AI Hardware Hub under the US CHIPS and Science Act. His research spans Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences, with breakthroughs in X-Compact test compression, carbon nanotube computing, and 3D integration. He has held international roles like the Carnot Chair at CEA-LETI and Visiting Professorships globally. Education & Honors: Recipient of over 40 awards including the IEEE Computer Society’s Harry H. Goode Memorial Award, ACM/IEEE’s A. Richard Newton Technical Impact Award, and the Intel Achievement Award. He earned top academic accolades from IIT Kharagpur and Jadavpur University, and is a Fellow of ACM and IEEE. Research Impact: Pioneered first-of-their-kind systems like the carbon nanotube computer and monolithic 3D integration. His work on robust computing techniques like QED validation and X-Compact compression has industry-wide adoption, saving billions in manufacturing costs. Collaborates with industry leaders like Intel, Google, and Samsung. Publications & Grants: Over 400 publications, including award-winning papers in DAC, ISSCC, and IEEE journals. Leads grants from NSF, DoE, and industry partnerships. His lab explores cutting-edge topics like neuromorphic computing, 3D thermal scaffolding, and AI hardware acceleration. Administration & Outreach: Serves as Associate Chair (Faculty Affairs) for Stanford’s Computer Science Department. Recognized by students for mentorship, and frequently invited to global forums like the World Economic Forum and National Academy of Engineering.
Hamed Rahmani is an Assistant Professor of Electrical and Computer Engineering at New York University (NYU Tandon School of Engineering). He is affiliated with NYU WIRELESS and the Center for Advanced Technology in Telecommunications (CATT), leading the Research in Advanced Integrated Systems and Electronics (RAISE) Lab. His research focuses on integrated circuits and systems for biomedical applications, IoT, and 5G/6G communication. Education: Ph.D., Electrical and Computer Engineering, UCLA (2020) M.Sc., Electrical and Computer Engineering, Rice University (2017) B.Sc., Electrical Engineering, Sharif University of Technology (2014) Research Interests: RF/mm-Wave circuits, low-power biomedical sensors, energy-efficient IoT systems, and wireless power transfer. His work emphasizes miniaturized implants, smart healthcare, and sustainable electronics. Awards: Recipient of the NSF CAREER Award (2025), IEEE MTT-S Graduate Fellowship (2019), and the 2023 Best Paper Award in the Journal of Microwave. He serves on technical committees for major conferences like CICC and IMS. Labs & Groups: Directs the RAISE Lab, collaborating with NYU WIRELESS on 6G research and CATT for technology transfer.
University of Illinois Urbana-ChampaignUnited States
Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.
Gert Cauwenberghs is a Professor of Bioengineering at the University of California San Diego (UCSD), affiliated with the Jacobs School of Engineering. He co-directs the Institute for Neural Computation and holds a visiting professorship at MIT. His research focuses on neuromorphic engineering, energy-efficient neural interfaces, and wearable biosensors. Key contributions include silicon-based adaptive neural circuits, implantable neural recording systems, and in-ear biosensing devices. Education: M.Eng. in Applied Physics (University of Brussels, 1988), M.S. and Ph.D. in Electrical Engineering (Caltech, 1989–1994). Prior roles include Professorships at Johns Hopkins University and Visiting Professor at MIT. Research Interests: Biomedical integrated circuits, neuromorphic computing, brain-machine interfaces, and energy-efficient neural systems. His work bridges neuroengineering and clinical applications, emphasizing adaptive intelligence and low-power designs. Recent Work: Development of femtojoule-efficient neural chips, high-density neural interfaces, and closed-loop wearable systems. Projects include neurobench benchmarking frameworks and RRAM-based neuromorphic hardware. Awards: NSF Career Award (1997), ONR Young Investigator (1999), PECASE (2000), IEEE Distinguished Lecturer (2003–2004). Grants & Labs: Active in NIH and DoD-funded projects, co-directs the UCSD Institute for Neural Computation. Collaborates with industry on neural interface technologies. Labs/Teams: Cauwenberghs Lab at UCSD focuses on integrated neuroengineering systems, including neural recording systems and neuromorphic computing architectures.
Michael McAlpine is a Professor in the Mechanical Engineering department at the University of Minnesota . He also holds affiliations with the Biomedical Engineering and Electrical and Computer Engineering departments. His research focuses on 3D printing functional materials & devices , Nanoscale inks , Biomedical devices , Bioelectronics , and Flexible Microsystems . Research Interests : 3D Printing, Biomedical Engineering, Nanotechnology, Flexible Electronics, Microfluidics Labs : ME 361/363 Contact : mcalpine@umn.edu , (612) 626-3303, ME 117 Recent Research Trends include 3D Printed Biomedical Devices , Flexible Electronics , and Bioprinting Applications . His work spans from Spinal Organoid Formation to Programmable Drug Release Capsules . Scientific Award : Circulation Research 2020 Best Manuscript Award
Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology and serves as the Director of the 3D Systems Packaging Research Center. His research focuses on heterogeneous integration of microsystems, including 2.5D and 3D ICs and packaging technologies, with significant contributions to advanced cooling systems, electrical and photonic interconnects, and biosensor integration with CMOS. Dr. Bakir's research interests span heterogeneous microsystem design and integration, advanced cooling and power delivery for emerging architectures, electrical and photonic interconnect technologies, biosensor technologies, and nanofabrication. His work addresses critical challenges in next-generation electronics, enabling polylithic integration that concatenates heterogeneous ICs of various functionalities while mimicking monolithic-like densities. His research particularly focuses on co-design of thermal technologies, power delivery networks, and signaling networks for silicon nanoelectronic systems. His recent publications demonstrate strong trends in fused-silica stitch-chip technology for heterogeneous integration, with particular emphasis on RF and mm-wave applications, power delivery for AI accelerators, and thermal management solutions. His work bridges electrical engineering, materials science, and thermal management to solve critical bottlenecks in computing performance and efficiency. 2013 Intel Early Career Faculty Honor Award 2012 DARPA Young Faculty Award 2011 IEEE CPMT Society Outstanding Young Engineer Award 2012 National Academy of Engineering Frontiers of Engineering Symposium Invited Participant 2015 IEEE CPMT Society Distinguished Lecturer 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology More than 25 conference and student paper awards Twelve issued US Patents Dr. Bakir leads the Integrated 3D Systems Lab (I3DS) at Georgia Tech, which is actively researching advanced packaging, interconnects, electrical and thermal design, and system integration. His team has received significant recognition for their work, including multiple best paper awards from major conferences like ECTC, IITC, and CICC. The lab is currently seeking postdoctoral researchers and research faculty to advance next-generation electronics through collaborative research. His lab focuses on enabling the next phase of Moore's Law through polylithic integration, which concatenates heterogeneous ICs of various functionalities (digital, analog, photonic, and mm-wave) using advanced off-chip '2.5D' and '3D' heterogeneous interconnects and packaging. This work impacts applications in high-performance computing, machine learning, edge intelligence, autonomous vehicles, augmented/virtual reality, and healthcare.
Sumeet Kumar Gupta is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University. His academic career spans from his current role to a prior Assistant Professorship at Pennsylvania State University (2014-2017) and an engineering position at Qualcomm Inc. (2012-2014). He holds a PhD in Electrical and Computer Engineering from Purdue University (2012), an M.S. from the same institution (2008), and a B.Tech in Electrical Engineering from IIT Delhi (2006). B.Tech, Electrical Engineering, IIT Delhi (2006) M.S., Electrical and Computer Engineering, Purdue University (2008) PhD, Electrical and Computer Engineering, Purdue University (2012) Dr. Gupta's research focuses on neuromorphic computing, low power variation-aware VLSI design in emerging nanotechnologies, device-circuit co-design, and nano-scale device modeling/simulations. His work addresses challenges in ferroelectric materials, crossbar arrays for deep neural networks, and energy-efficient AI hardware. Recent publications (2025-2024) highlight trends in: Ferroelectric HfO2/HZO thin films Compute-in-memory architectures Variability/stochasticity analysis Machine learning for device optimization Interconnect resistance/temperature effects AI hardware fault tolerance Scientific Awards & Recognitions: DARPA Young Faculty Award (2016) Early Career Professorship, Penn State (2014) 6th TSMC Outstanding Student Research Bronze Award (2012) Magoon Award (Purdue) Outstanding Teaching Assistant Award (Purdue, 2007) Intel PhD Fellowship (2009) His professional journey includes academic appointments at Purdue University (2020-present, Associate Professor) and Pennsylvania State University (2014-2017, Assistant Professor) after industry experience at Qualcomm Inc. (2012-2014). He maintains IEEE and EDS membership while publishing over 100 refereed works.
Mark Foster is an Associate Professor in the Department of Electrical and Computer Engineering at Johns Hopkins University, with a primary appointment in the Whiting School of Engineering. He is also a Fellow of the Hopkins Extreme Materials Institute. His research focuses on developing ultrahigh-speed optical systems at the intersection of photonics and electronics, emphasizing photonic devices and information theory to advance imaging, sensing, and communications technologies. Applications include quantum-optical systems, ultrawide-bandwidth microwave photonics, and terahertz-rate imaging systems. Dr. Foster received his BS (2003), MS (2007), and PhD (2008) in Applied and Engineering Physics from Cornell University. Before joining Johns Hopkins in 2010, he served as a postdoctoral associate there. His work has been funded by the NSF, IARPA, DTRA, and NIH, resulting in over 200 publications and eight patents. He has held leadership roles, including chairing the IEEE Photonics Society’s Baltimore chapter (2011–2014). Research Highlights: World-leading imaging systems achieving terahertz frame rates Quantum-optical platforms and nonlinear photonic materials (e.g., NbTiOx) Secure authentication via physically unclonable functions (PUFs) Applications in fusion energy diagnostics and medical imaging His awards include the NSF CAREER Award (201?), DARPA Young Faculty Award, and ONR Young Investigator Award. Current projects explore machine learning-resistant PUFs, multi-modal imaging systems, and photonics for extreme environments.
University of California , Santa Barbara (UCSB)United States
Dmitri Strukov is a Professor at the University of California, Santa Barbara in the Department of Electrical and Computer Engineering. His work spans material science, electrical engineering, and computer science, focusing on novel computing paradigms using emerging memory devices. Education: PhD in Electrical and Computer Engineering from SUNY Stony Brook, MS in Applied Physics and Mathematics from Moscow Institute of Physics and Technology. Research Interests include neuromorphic computing , non-volatile memory applications , and mixed-signal circuits for machine learning and hardware security. His group develops memristive crossbar arrays and 3D NAND flash for energy-efficient systems. Scientific Leadership features Fellow of IEEE and Distinguished Lecturer roles. His work has been recognized with best paper awards at ASPLOS’19 and Computing Frontiers’13. Students: Mentored PhD graduates in neurocomputing, security, and memristor design including Z. Fahimi, S. Larimian, M.R. Mahmoodi, and X. Guo. Grants: Funded by AFOSR, ARO, DARPA, NSF, and industry leaders like Google and Samsung. Labs: Utilizes UCSB’s nanofabrication center and advanced tools for memristor characterization.
University of Illinois Urbana-ChampaignUnited States
Naresh R. Shanbhag is the Jack Kilby Professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. He serves as Director of the Systems on Nanoscale Information fabriCs (SONIC) Center and held the D.J. Gandhi Distinguished Visiting Professorship at IIT Mumbai from 2015-2020. Previously, he was a visiting faculty member at National Taiwan University (2007) and Stanford University (2014). Dr. Shanbhag received his doctorate from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories as the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. His research focuses on the design of energy-efficient machine learning, communications, and signal processing systems on resource-constrained embedded platforms. He explores fundamental trade-offs between energy efficiency, latency and accuracy of decision-making systems implemented in nanoscale technologies, with applications to computer vision, biomedicine, automatic target recognition, and imaging. His work spans four primary focus areas: Resource-efficient Machine Learning for the Edge, In-memory Computing (IMC), Energy-efficient High Data Rate Communications, and Shannon-inspired Statistical Error Compensation (SEC). Analysis of his recent publications reveals a strong emphasis on in-memory computing architectures (SRAM, MRAM, RRAM) for machine learning acceleration. His work consistently addresses energy-accuracy trade-offs, with increasing attention to security aspects of hardware implementations and applications to MIMO signal processing and edge AI systems. His research demonstrates a progression from theoretical foundations to practical silicon implementations. 2024 Semiconductor Research Corporation Innovation Award 2018 Semiconductor Industry Association/Semiconductor Research Corporation University Researcher Award 2018 IEEE International Symposium on Circuits and Systems Best Paper Award 2006 IEEE Fellow 1996 National Science Foundation CAREER Award Professor Shanbhag has mentored over 50 graduate students who now work at leading technology companies including Qualcomm, Amazon, Nvidia, Intel, and Apple. His research has been generously supported by the National Science Foundation, DARPA, AFRL, Semiconductor Research Corporation, Texas Instruments, Sandia National Laboratories, and industry partners including IBM, GlobalFoundries, and Intel Corporation. He led the Alternative Computational Models research theme (2006-2012) and was the founding Director of the SONIC Center (2013-2017), a 5-year multi-university center funded by DARPA and SRC. Currently, he leads research themes in the SRC and DARPA funded JUMP 2.0 Program's Center for Co-Design of Cognitive Systems and the Center for Ubiquitous Connectivity, and in the NSF IUCRC Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). As Director of the Systems on Nanoscale Information fabriCs (SONIC) Center, Professor Shanbhag leads a multidisciplinary team exploring novel computing paradigms for the nanoscale era. His group has benchmarked an extensive collection of in-memory computing and digital accelerator IC designs, maintaining a publicly available IMC benchmarking repository of metrics extracted from published IC prototypes. His research philosophy integrates concepts from information theory, statistical signal processing, detection and estimation, VLSI architectures, and digital and analog integrated circuits to develop energy-efficient systems from algorithms to silicon implementations.
University of California, Los AngelesUnited States
Aydin Babakhani is a Professor in the Department of Electrical and Computer Engineering at the University of California, Los Angeles (UCLA), affiliated with the College of Life Sciences. He directs the Integrated Sensors Laboratory (ISL), which focuses on the design and implementation of integrated sensors and systems. His research spans high-speed wireless communication, terahertz technology, medical implants, radar systems, and industrial monitoring solutions. Research Interests: Prof. Babakhani's work integrates silicon-based technologies with applications across multiple domains. Key areas include: Silicon mm-Wave/THz transceivers and on-chip antennas for communication and sensing Wirelessly powered medical implants for biopotential monitoring and neural stimulation THz radar systems for micrometer-resolution imaging and vibration detection Energy harvesting solutions for batteryless sensors in industrial and biomedical applications CMOS-based optoelectronic systems and photonic computing accelerators His recent publications (2021-2025) demonstrate a strong emphasis on terahertz systems, wireless power transfer, and miniaturized medical electronics. Over 80% of his latest articles involve silicon-integrated solutions for biomedical implants or THz sensing, with emerging focus on AI-accelerated photonic computing and multi-Gbps wireless links.
Massachusetts Institute of TechnologyUnited States
Anantha Chandrakasan is the Vannevar Bush Professor of Electrical Engineering and Computer Science at MIT, serving as Dean of the MIT School of Engineering and Chief Innovation and Strategy Officer. His research focuses on energy-efficient integrated circuits, medical devices, and AI hardware security. He leads the MIT Energy-Efficient Circuits and Systems Group, developing systems for biomedical applications, wireless communication, and quantum computing. He holds appointments at MIT's Microsystems Technology Laboratories and has contributed to collaborations like the MIT-Takeda Program in AI-driven healthcare and a partnership with GlobalFoundries for energy-efficient AI chips. His work spans implantable drug delivery systems, conformable ultrasound patches, and secure edge computing architectures. Chandrakasan's innovations include ultra-low-power circuits for IoT devices, cryptographic processors for post-quantum security, and AI accelerators for edge applications. He emphasizes interdisciplinary research bridging electrical engineering with biomedical and quantum fields, supported by leadership roles in MIT's strategic initiatives. His contributions to energy-efficient computing have led to advancements in wearable health monitors, batteryless sensors, and secure communication protocols for medical devices. Ongoing projects include THz integrated systems and AI-enhanced analog circuit design optimization.
