جست‌وجوی استاد و پژوهشگر

• Nanoelectronic devices
• Integrated circuits
• AI hardware
• +۵ مورد دیگر

Haitong Li is an Assistant Professor in the School of Electrical and Computer Engineering at Purdue University's College of Engineering, joining the faculty in 2022. His research bridges nanoelectronic devices, integrated circuits, and nanotechnology-inspired AI hardware to address critical challenges in energy-efficient artificial intelligence systems. Education: Ph.D. in Electrical Engineering, Stanford University Research Interests: Dr. Li pioneers emerging memory technologies—particularly Resistive RAM (RRAM)—for in-memory computing and neuromorphic systems. His work focuses on 3D monolithic integration of RRAM and gain cell memory with CMOS to enable edge AI, with recent breakthroughs in hardware acceleration for large language models and sustainable computing. Key innovations include carbon footprint prediction for LLMs and zeroth-order fine-tuning techniques. Publication Trends: Dr. Li's 2023-2025 publications reveal a strategic shift toward sustainable AI hardware, emphasizing carbon-aware LLM inference and edge deployment. His research consistently targets data movement reduction through memory-centric architectures, spanning photonic accelerators, neuro-symbolic computing, and heterogeneous 3D integration. Awards: No scientific awards were documented in the provided sources. Advising and Grants: Current advisees and grant funding details were not specified in the available materials. Labs and Teams: Research group composition and laboratory facilities were not described in the source text.

Jian Huangمشاهده پروفایل

دانشیار

• Computer Architecture
• Memory and Storage Systems
• AI Infrastructure
• +۵ مورد دیگر

Jian Huang is an Associate Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign (UIUC), holding a 100% appointment since August 2024. He is also an affiliated Associate Professor in Computer Science and serves as the Y. T. Lo Faculty Fellow in ECE. Huang leads the Systems Platform Research Group and received his Ph.D. in Computer Science from Georgia Institute of Technology in August 2017, where his dissertation earned the College of Computing Dissertation Award. His research focuses on Computer Architecture, Memory and Storage Systems, AI Infrastructure, Distributed Systems, and Systems Security . Huang has pioneered work in sustainable AI infrastructures, modular data centers, neural processing unit virtualization, and ransomware-aware storage systems. His research has been featured in top-tier conferences including ISCA, MICRO, ASPLOS, OSDI, SOSP, and USENIX ATC, with over 50 publications and multiple patents issued worldwide. Huang's research has significant industry impact, with some work transferred into products and featured in popular media outlets including ACM CACM, TechXplore, and Science Daily. His work on non-volatile memory and storage systems has received extensive coverage, with some projects generating over 50 media reports. Among his notable achievements are the ACM SIGMICRO Early Career Award, NSF CAREER Award, IEEE Micro Top Picks (three times), USENIX Best Paper Award, and the MICRO Best Paper Runner Up in 2024. He has secured over $4.01M in grants ($11.12M with collaborators) from NSF, DARPA, Army Research Office, and industry partners. ACM SIGMICRO Early Career Award NSF CAREER Award IEEE Micro Top Picks (three times) USENIX Best Paper Award MICRO Best Paper Runner Up (2024) Google Faculty Research Award NetApp Faculty Fellowship Award Huang actively contributes to the academic community as program co-chair of NVMW'23 and organizer of HotInfra'23. He currently advises 12 Ph.D. students, 1 master student, and multiple undergraduates. His teaching innovations include developing ECE522: Emerging Memory/Storage System and revising ECE511: Computer Architecture with cutting-edge content.

Rakesh Kumarمشاهده پروفایل

استاد

• Computer Architecture
• System-Level Design Automation
• Low Power Computing
• +۳ مورد دیگر

Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.

Karthik R. Narasimhanمشاهده پروفایل

استاد

• Language Agents
• Reinforcement Learning
• Natural Language Processing
• +۳ مورد دیگر

Karthik R. Narasimhan is a Professor at Princeton University's School of Engineering and Applied Science in the Department of Computer Science. Previously, he earned his PhD from MIT under Regina Barzilay and served as a visiting research scientist at OpenAI during 2017-18. His research focuses on the intersection of language and decision-making, building autonomous agents that learn from both experience and human knowledge. His research spans multiple high-impact areas including language agents (Text-DQN, CALM, ReAct, Tree of Thoughts), reinforcement learning (h-DQN, Multi-Objective RL), and AI safety (Toxicity in ChatGPT, DataMUX). He has developed critical datasets and benchmarks such as WebShop, InterCode, SWE-bench, and SILG that have become standard evaluation tools in the field. Current work emphasizes agent capabilities, software engineering automation, and multimodal interaction. His publication trends show strong focus on practical agent deployment (SWE-agent, Tree of Thoughts), safety evaluation (Probing AI Safety), and efficiency improvements (DataMUX). Recent work increasingly addresses real-world challenges in software engineering, security, and human-AI collaboration through rigorous benchmarking. Co-author of foundational GPT (2018) paper Key developer of Text-DQN (2015), CALM (2020), ReAct (2022), Tree of Thoughts (2023) Creator of influential benchmarks: WebShop (2022), SWE-bench (2023), InterCode (2023) He actively advises students through Princeton's computer science program, with research supported by multiple grants focused on autonomous agent development and language-based decision systems. His GitHub repositories (nlp-datasets, text-world-player) demonstrate strong community engagement in open-source research tools. Current projects include advancing language agent capabilities through Reflexion (2023) and Tree of Thoughts (2023) frameworks while addressing critical safety and efficiency challenges.

Gert Cauwenberghsمشاهده پروفایل

استاد

• Neuromorphic Engineering
• Biomedical Integrated Circuits
• Neural Interfaces
• +۷ مورد دیگر

Gert Cauwenberghs is a Professor of Bioengineering at the University of California San Diego (UCSD), affiliated with the Jacobs School of Engineering. He co-directs the Institute for Neural Computation and holds a visiting professorship at MIT. His research focuses on neuromorphic engineering, energy-efficient neural interfaces, and wearable biosensors. Key contributions include silicon-based adaptive neural circuits, implantable neural recording systems, and in-ear biosensing devices. Education: M.Eng. in Applied Physics (University of Brussels, 1988), M.S. and Ph.D. in Electrical Engineering (Caltech, 1989–1994). Prior roles include Professorships at Johns Hopkins University and Visiting Professor at MIT. Research Interests: Biomedical integrated circuits, neuromorphic computing, brain-machine interfaces, and energy-efficient neural systems. His work bridges neuroengineering and clinical applications, emphasizing adaptive intelligence and low-power designs. Recent Work: Development of femtojoule-efficient neural chips, high-density neural interfaces, and closed-loop wearable systems. Projects include neurobench benchmarking frameworks and RRAM-based neuromorphic hardware. Awards: NSF Career Award (1997), ONR Young Investigator (1999), PECASE (2000), IEEE Distinguished Lecturer (2003–2004). Grants & Labs: Active in NIH and DoD-funded projects, co-directs the UCSD Institute for Neural Computation. Collaborates with industry on neural interface technologies. Labs/Teams: Cauwenberghs Lab at UCSD focuses on integrated neuroengineering systems, including neural recording systems and neuromorphic computing architectures.

Michael O'Boyleمشاهده پروفایل

استاد

• Heterogeneous Code discovery and Optimisation
• Neural Machine Translation and Neural Synthesis
• Deep Neural Network system stack
• +۷ مورد دیگر

Michael O'Boyle is a Professor at the University of Edinburgh's School of Informatics, where he serves as Director of the ARM Research Centre of Excellence and the EPSRC Centre for Doctoral Training in Pervasive Parallelism. Holding an EPSRC Established Career Research Fellowship, he leads pioneering work in compiler technology for heterogeneous architectures, bridging theoretical advances with practical high-performance computing applications. Professor O'Boyle's research spans multiple cutting-edge areas including heterogeneous code discovery and optimization, neural machine translation for program synthesis, deep neural network system stack optimization, software-defined hardware, and compiler/architecture co-design. His approach integrates constraint analysis, program synthesis, and machine learning to address complex challenges in high-performance computing across diverse hardware platforms. His recent publications reveal a strong trend toward integrating machine learning with traditional compiler techniques, particularly in neural program synthesis, tensor optimization, and architecture-aware compilation. This work represents a paradigm shift in compiler design, moving from rule-based systems to learning-based approaches that can automatically adapt to diverse hardware targets. IEEE/ACM CGO 2025 Distinguished Paper Award for 'Tensorize: Fast Synthesis of Tensor Programs from Legacy Code' IEEE/ACM CGO 2024 Test of Time Award ACM GPCE 2023 Best Paper Award for 'C2TACO: Lifting Tensor Code to TACOM' ACM ASPLOS 2021 Distinguished Paper Award IEEE HPCA 2021 Best Paper Award for 'Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads' Professor O'Boyle has successfully mentored numerous PhD students who have secured prominent positions in academia (including at Cambridge, Edinburgh, Leeds, and McGill) and industry (including Meta, NVIDIA, Qualcomm, Huawei, and Microsoft). His research is supported by significant funding from EPSRC, ARM, and European projects including Bonseyes and Transmuter, demonstrating strong international recognition and industry impact. He leads the influential Compiler and Architecture Design (CArD) Group at the University of Edinburgh and is a founder of the HiPEAC Network of Excellence, which has grown into a major European initiative connecting researchers and practitioners in high-performance and embedded computing.

Muhannad S Bakirمشاهده پروفایل

استاد

• Heterogeneous Integration
• 3D IC Packaging
• Advanced Cooling Systems
• +۷ مورد دیگر

Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology and serves as the Director of the 3D Systems Packaging Research Center. His research focuses on heterogeneous integration of microsystems, including 2.5D and 3D ICs and packaging technologies, with significant contributions to advanced cooling systems, electrical and photonic interconnects, and biosensor integration with CMOS. Dr. Bakir's research interests span heterogeneous microsystem design and integration, advanced cooling and power delivery for emerging architectures, electrical and photonic interconnect technologies, biosensor technologies, and nanofabrication. His work addresses critical challenges in next-generation electronics, enabling polylithic integration that concatenates heterogeneous ICs of various functionalities while mimicking monolithic-like densities. His research particularly focuses on co-design of thermal technologies, power delivery networks, and signaling networks for silicon nanoelectronic systems. His recent publications demonstrate strong trends in fused-silica stitch-chip technology for heterogeneous integration, with particular emphasis on RF and mm-wave applications, power delivery for AI accelerators, and thermal management solutions. His work bridges electrical engineering, materials science, and thermal management to solve critical bottlenecks in computing performance and efficiency. 2013 Intel Early Career Faculty Honor Award 2012 DARPA Young Faculty Award 2011 IEEE CPMT Society Outstanding Young Engineer Award 2012 National Academy of Engineering Frontiers of Engineering Symposium Invited Participant 2015 IEEE CPMT Society Distinguished Lecturer 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology More than 25 conference and student paper awards Twelve issued US Patents Dr. Bakir leads the Integrated 3D Systems Lab (I3DS) at Georgia Tech, which is actively researching advanced packaging, interconnects, electrical and thermal design, and system integration. His team has received significant recognition for their work, including multiple best paper awards from major conferences like ECTC, IITC, and CICC. The lab is currently seeking postdoctoral researchers and research faculty to advance next-generation electronics through collaborative research. His lab focuses on enabling the next phase of Moore's Law through polylithic integration, which concatenates heterogeneous ICs of various functionalities (digital, analog, photonic, and mm-wave) using advanced off-chip '2.5D' and '3D' heterogeneous interconnects and packaging. This work impacts applications in high-performance computing, machine learning, edge intelligence, autonomous vehicles, augmented/virtual reality, and healthcare.

Sumeet Kumar Guptaمشاهده پروفایل

دانشیار

• Neuromorphic Computing
• Low Power VLSI Design
• Emerging Nanotechnologies
• +۳ مورد دیگر

Sumeet Kumar Gupta is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University. His academic career spans from his current role to a prior Assistant Professorship at Pennsylvania State University (2014-2017) and an engineering position at Qualcomm Inc. (2012-2014). He holds a PhD in Electrical and Computer Engineering from Purdue University (2012), an M.S. from the same institution (2008), and a B.Tech in Electrical Engineering from IIT Delhi (2006). B.Tech, Electrical Engineering, IIT Delhi (2006) M.S., Electrical and Computer Engineering, Purdue University (2008) PhD, Electrical and Computer Engineering, Purdue University (2012) Dr. Gupta's research focuses on neuromorphic computing, low power variation-aware VLSI design in emerging nanotechnologies, device-circuit co-design, and nano-scale device modeling/simulations. His work addresses challenges in ferroelectric materials, crossbar arrays for deep neural networks, and energy-efficient AI hardware. Recent publications (2025-2024) highlight trends in: Ferroelectric HfO2/HZO thin films Compute-in-memory architectures Variability/stochasticity analysis Machine learning for device optimization Interconnect resistance/temperature effects AI hardware fault tolerance Scientific Awards & Recognitions: DARPA Young Faculty Award (2016) Early Career Professorship, Penn State (2014) 6th TSMC Outstanding Student Research Bronze Award (2012) Magoon Award (Purdue) Outstanding Teaching Assistant Award (Purdue, 2007) Intel PhD Fellowship (2009) His professional journey includes academic appointments at Purdue University (2020-present, Associate Professor) and Pennsylvania State University (2014-2017, Assistant Professor) after industry experience at Qualcomm Inc. (2012-2014). He maintains IEEE and EDS membership while publishing over 100 refereed works.

• Databases
• Data Mining
• Machine Learning
• +۳ مورد دیگر

Ming-Syan Chen is a distinguished academic holding dual roles as a Distinguished Research Fellow and Director of the Research Center for Information Technology Innovation (CITI) at Academia Sinica, Taiwan, and a Distinguished Professor jointly appointed across multiple departments at National Taiwan University (NTU), including Electrical Engineering (EE), Computer Science and Information Engineering (CSIE), and the Graduate Institute of Communication Engineering (GICE). His career spans academia and industry, with prior roles as a research staff member at IBM Watson Research Center and leadership positions in Taiwan's technology sector. Education: He earned a B.S. in Electrical Engineering from National Taiwan University, followed by M.S. and Ph.D. degrees in Computer, Information, and Control Engineering from the University of Michigan, Ann Arbor. Research Interests: Chen's work focuses on databases, data mining, machine learning, multimedia networking, and cloud computing. He has authored over 350 papers and holds numerous patents, contributing to foundational advancements in query processing, data management, and networked systems. Award Highlights: Recipient of ACM and IEEE Fellowships, National Chair Professorship (lifetime honor), Teco Award, Pan Wen Yuan Distinguished Research Award, and IBM's Outstanding Innovation Award. His contributions span research, teaching, and technology commercialization. Leadership & Service: Former Dean of NTU's College of Electrical Engineering and Computer Science, CEO of Taiwan's Networked Communication Program, and Editor-in-Chief of the International Journal of Electrical Engineering. He has chaired international conferences and served on editorial boards of journals like IEEE TKDE and VLDB. Labs & Teams: Leads the Network Database Laboratory and collaborates on national initiatives in information and communication technologies. His research groups focus on data science, distributed systems, and social network analysis.

• Computer Engineering
• Circuit Design
• Fault Tolerance
• +۶ مورد دیگر

Matteo Sonza Reorda is a Full Professor at the Polytechnic University of Turin, affiliated with the Department of Automatic Control and Computer Science (DAUIN). He holds roles such as Partnership Agreement Coordinator with SMAT and has served as Vice-Rector for Research (2021–2024). His research focuses on fault tolerance, hardware reliability, and AI acceleration, with contributions to GPU/CNN reliability, self-test libraries, and defect-oriented testing. Education: M.S. in Electronics Engineering, Politecnico di Torino (1986) Ph.D. in Computer Engineering, Politecnico di Torino (1990) Research Interests: His work spans automatic test equipment, circuit reliability, GPU fault tolerance, neural network hardening, and embedded systems safety . He leads the Electronic CAD & Reliability Group and collaborates with institutions like the ISI Foundation and the National Research Council (CNR). Publications & Impact: With over 180 publications, his recent work emphasizes AI accelerator reliability, fault injection techniques, and safety-critical systems. Key trends include GPU resilience for CNNs, self-test library optimization, and radiation fault modeling in neural networks. Awards & Recognition: IEEE Fellow (2016–) Multiple best-paper awards at IEEE conferences (DDECS, DATE, etc.) Grants & Collaborations: Coordinator of EU projects (RESCUE, TUTORIAL) Partnerships with EDF, Marelli Europe, and SMAT Lead on National HPC/Quantum Computing Spoke 1 (2022–2025) Labs/Teams: Leads the CAD Group and collaborates with the French-Italian LIA LAFISI lab on hardware-software integration.

• Computer Architecture
• Datacenter Systems
• Cloud-Native Server Architecture
• +۷ مورد دیگر

Babak Falsafi is a Full Professor at the School of Computer and Communication Sciences (IC) at EPFL, leading the Parallel Systems Architecture Laboratory (PARSA). He is a renowned expert in computer architecture, datacenter systems, and cloud-native server design. His research focuses on post-Moore era computing, emphasizing heterogeneous architectures, energy efficiency, and scalable IT infrastructure. Falsafi is the founder of EcoCloud, an EC-sponsored industrial-academic consortium investigating sustainable information technology. He holds ACM and IEEE fellowships, a Sloan Research Fellowship, and has contributed to major projects like Optimus Prime (data transformation acceleration), AstriFlash (flash-based online service systems), and Midgard (virtual memory re-design). His work spans hardware-software co-design, memory systems, and security. Falsafi advises numerous PhD students and collaborates with industry partners such as Google and Cavium. Key achievements include pioneering scalable multiprocessor architectures, snoop filters in IBM BlueGene, and spatial memory streaming in ARM cores. His lab develops open-source tools like QFlex for server simulation. He frequently presents at top conferences (HPCA, ISCA, MICRO) and chairs workshops on post-Moore infrastructure. Teaching roles include leading courses in computer architecture and parallel systems across multiple EPFL departments (SIN, EDIC, SSC, SMA). His work addresses datacenter challenges like the 'data tax' and mitigating latency through specialized accelerators.

Bernhard J. Bergerمشاهده پروفایل

مدرس

• Software Security
• Static Code Analysis
• Machine Learning
• +۴ مورد دیگر

Bernhard J. Berger is a Lecturer in the Department of Computer Engineering at the Institute of Embedded Systems, Hamburg University of Technology (TUHH). His research focuses on software security, static code analysis, machine learning, optimization, and research data management. He has held significant roles such as Program Committee member for ICPC 2025 and MSR 2025, and has received awards including the Best Reviewer Award (ICPC 2023) and Best Engineering Paper Award (SCAM 2019). His work spans interdisciplinary applications including maritime systems security, GPU-accelerated AI, and evolutionary algorithms. Recent studies emphasize AI-driven security tools (e.g., ML-SAST) and domain-specific language approaches to optimization (EvoAl). He has contributed to over 30 peer-reviewed publications, with notable work in IEEE Transactions on Software Engineering and Science of Computer Programming. Berger collaborates closely with industry through DAAD review committees and serves on artifact evaluation boards for ISSTA and ARES conferences. Education: Doctoral Thesis (2022), Diploma in Computer Science (2007) Key Projects: ArchSec tool suite, Threat Modeling Frameworks, Bauhaus static analysis methodology Lab Affiliation: Embedded Systems Design Group His advisory roles include Deputy of TUHH's Election Verification Committee and Session Chair at IEEE Congress on Evolutionary Computation 2023. Current research trends integrate machine learning with static analysis for automated vulnerability detection, while also exploring explainable AI techniques for neural network optimization.

Yang Zhouمشاهده پروفایل

دانشیار

• Big Data Algorithms
• Data Mining
• Machine Learning
• +۵ مورد دیگر

Yang Zhou is an Associate Professor in the Department of Computer Science and Software Engineering at Auburn University, part of the Samuel Ginn College of Engineering. His research focuses on big data algorithms, machine learning, data mining, and distributed computing. He has contributed to advancements in federated learning frameworks, graph mining tools, and spatial machine learning for environmental applications like flood mapping. Education includes a Ph.D. in Computer Science from Georgia Tech (2021), M.E. in Computer Application Technology from Chongqing University (2016), and B.E. in Engineering from Jiangnan University (2014). His work emphasizes scalable algorithms for large-scale systems, with tools like DirDense for dense subgraph mining and FedASMU for federated learning optimization. Recent publications explore adversarial robustness, blockchain strategies in IoT, and curriculum-based learning for large language models. He advises on interdisciplinary projects at the intersection of AI and environmental science.

Hayden Kwok Hay SOمشاهده پروفایل

دانشیار

• Reconfigurable Computing
• FPGA-Based Systems
• Computer Architecture
• +۷ مورد دیگر

Prof. Hayden Kwok Hay SO is an Associate Professor at the University of Hong Kong (HKU), affiliated with the Department of Electrical and Electronic Engineering. He currently serves as Acting Director of the School of Innovation and previously co-directed the Computer Engineering Program. His research focuses on reconfigurable computing systems, FPGA-based architectures, and their applications in AIoT, medical imaging, and high-performance computing. He holds a B.S., M.S., and Ph.D. in Electrical Engineering and Computer Sciences from UC Berkeley (1998–2007). Prof. So has been recognized with awards such as the IEEE-HKN Teaching Award (2021), Croucher Innovation Award (2013), and multiple teaching excellence awards. He leads the Computer Architecture & System Research Lab (CASR) and co-founded the Joint Lab on Future Cities (JLFC). His work spans FPGA overlay architectures, graph processing systems, and hardware-software co-design for efficient computing. Key research contributions include advancements in FPGA-based reconfigurable systems, sparse dataflow architectures, and medical imaging accelerators. He has secured grants for projects like 'Advanced machine vision guided aquatic surface vehicles' and 'Efficient and Productive Parallel Data Processing in Hybrid FPGA-CPU Clusters.' Prof. So has advised numerous students and researchers, contributing to over 150 peer-reviewed publications. His current projects explore AI hardware acceleration, neuromorphic computing, and FPGA-driven solutions for big data challenges.

Geng Yuanمشاهده پروفایل

استادیار

• Artificial Intelligence Systems
• Energy-Efficient Deep Learning
• Model Compression
• +۵ مورد دیگر

Geng Yuan is an Assistant Professor at the University of Georgia's School of Computing, specializing in AI systems, energy-efficient deep learning, and hardware-software co-design. His work bridges machine learning algorithms with emerging hardware technologies like superconducting circuits and ReRAM. He holds a Ph.D. in Computer Engineering from Northeastern University (2023) and a Master's in Electrical & Computer Engineering from Syracuse University (2016). Doctor of Philosophy (Ph.D.) in Computer Engineering, Northeastern University (2023) Master of Science (M.S.) in Electrical & Computer Engineering, Syracuse University (2016) Bachelor of Science (B.S.) in Electrical Engineering, Beijing University of Technology (2014) His research focuses on optimizing deep learning systems for edge computing and mobile platforms through techniques like model compression, sparse training, and hardware-aware neural architecture search. Recent projects include adapting large language models via hybrid-grained pruning and developing ultra-low-power AQFP circuits for binary networks. Geng Yuan's publications span top venues like NeurIPS, CVPR, ICML, ICLR, ISCA, and DAC, with notable awards including a Best Paper Award at ICLR Workshop 2021, Spotlight Papers at ICLR 2023 and NeurIPS 2021, and a Design Contest 1st Place at ISLPED 2020. Best Paper Award (ICLR Workshop'21) Spotlight Paper Award (ICLR'23, NeurIPS'21) Design Contest 1st Place (ISLPED'20) Best Paper Nomination (DATE'21, ISQED'18) He actively recruits Ph.D., Master's students, and interns to his research group, focusing on advancing AI systems through interdisciplinary approaches combining machine learning, computer architecture, and electronic design automation.