Giorgio C. Buttazzo is a Full Professor of Computer Engineering at the Scuola Superiore Sant'Anna in Pisa, Italy, and founder/director of the RETIS Lab. His career includes roles at the University of Pavia and co-founding Evidence s.r.l. (a real-time embedded systems company). He holds an IEEE Fellowship (2012) and the IEEE TC RTS Outstanding Technical Contributions Award (2013). Education: Electronic Engineering (University of Pisa, 1985), Master in Computer Science (University of Pennsylvania, 1987), PhD in Computer Engineering (Scuola Superiore Sant'Anna, 1991). Affiliations: TeCIP Institute, RETIS Lab, and leadership roles in IEEE Technical Committees. Research focuses on real-time systems, robotics, and AI integration. He has authored 10 books, over 300 papers, and pioneered frameworks like the ERIKA/SHARK kernels. Current projects include RETICULATE, OPERAND, and NANCY (5G networks). Teaching includes Real-Time Systems, Neural Networks, and Jazz Guitar Improvisation. Advised over 150 master and PhD students. Active in conferences like ECRTS, RTSS, and RTAS.
David Wood is a Professor in the Department of Computer Sciences at the University of Wisconsin-Madison, with primary affiliation to the College of Engineering. His research focuses on cost-effective computer architectures and tools for evaluating performance, feasibility, and correctness of new systems. Multi-paradigm multiprocessors integrating shared-memory, message-passing, and hybrid programming Virtual prototyping systems leveraging similarities between existing and hypothetical parallel machines Performance tuning techniques for program optimization He developed Fast-Cache, a memory system simulation method optimizing cache hits to reduce simulation time, and Typhoon, a hardware platform implementing Tempest mechanisms for low-overhead inter-paradigm communication.
Mark Heinrich is an Associate Professor in the Department of Computer Science at the University of Central Florida (UCF), where he also serves as Undergraduate Coordinator for CS and IT, and Senior Design Coordinator. He previously held roles at Cornell University and has industry experience co-founding companies like Phanfare and Flashbase. His research focuses on parallel computer architecture, heterogeneous systems, cache coherence protocols, and multiprocessor simulation. Heinrich holds a Ph.D. in Electrical Engineering from Stanford University (1998) under John Hennessy, and a B.S. in Electrical Engineering and Computer Science from Duke University (1991). Research Interests His work spans parallel architectures, active memory systems, scalable cache coherence protocols, and hardware/software co-design. Recent efforts include innovations in persistent memory technologies and multiprocessor simulation methodologies. Teaching In Spring 2020, he taught CS Senior Design I and II courses (COP 4934/4935), with office hours focused on senior design and undergraduate coordination. Professional Background Associate Professor at UCF since 2003 Past roles: Director of UCF's School of Computer Science (2005), Associate Director of EECS (2005-2007) Co-founder of the Cornell Computer Systems Laboratory Contributed to the FLASH multiprocessor architecture and its simulation tools Labs & Projects He has been involved in projects like Active Memory Clusters and architectural support for multiprocessor systems. His work often bridges theoretical computer architecture with practical hardware implementations.
Tyler Bletsch is an Associate Professor of the Practice in the Department of Electrical and Computer Engineering at Duke University's Pratt School of Engineering. He joined the Duke faculty in November 2015 after several years of work in industry with NetApp, bringing practical industry experience to his academic role. His teaching focuses on practical aspects of computer engineering and systems programming. Dr. Bletsch received his B.S. from North Carolina State University in 2004, followed by his D.Phil. from the same institution in 2011. His doctoral research focused on software security, particularly addressing code-reuse attacks. His research interests span hardware and software security, with a particular focus on Rowhammer vulnerabilities and mitigation techniques. He also explores power-aware computing for high-performance systems and has interests in robotics and technology education with an emphasis on project-oriented learning. Dr. Bletsch's publication record shows a consistent focus on computer security, particularly Rowhammer attacks and mitigation strategies in recent years. His earlier work addressed code-reuse attacks like Jump-oriented Programming and Return-oriented Programming. He has also contributed to power management research for high-performance computing systems. Dr. Bletsch is actively involved in mentoring students through the Duke Combat Robotics club and FIRST robotics teams. He teaches a variety of courses including Computer Architecture, Digital Systems, Computer and Information Security, and Engineering Software for Maintainability. His teaching philosophy emphasizes hands-on, project-based learning. He maintains an active research laboratory focused on computer security and has been featured in Duke Today for his educational video "Tyler Bletsch Takes You on a Tour of the Insides of a Computer," which demystifies computer hardware for general audiences.
Pontus Ekberg is an Associate Professor at Uppsala University's Department of Information Technology. His email address is pontus.ekberg@it.uu.se , and he can be reached at +46 18 471 73 41. He is affiliated with the Division of Computer Systems and holds the academic merit 'Docent' in real-time scheduling theory. Ekberg's research focuses on algorithms and computational problems in real-time scheduling theory. His work addresses NP-hardness in scheduling, fixed-priority algorithms, and formal verification of task feasibility. Current projects include applying pseudo-polynomial time analysis, combating butterfly attacks, and integrating deep learning for schedulability verification in safety-critical systems. His recent publications span topics like pseudo-polynomial time analysis (2025), optimistic period predictions (2024), and explainability in real-time schedulability (2023). He collaborates frequently with Sanjoy Baruah and others on uniprocessor and multiprocessor scheduling models. Although no formal awards are listed, his contributions to real-time scheduling theory are evident through 15+ publications in top conferences like RTSS and ECRTS.
Iain Bate is a Lecturer in Real-Time Systems and Head of the Department of Computer Science at the University of York. His research focuses on scheduling and timing analysis, systems engineering with optimization of design trade-offs, design assurance, component-based engineering, and managing emergent behavior, particularly in critical systems. University of York, Department of Computer Science Research areas: Real-Time Systems, Mixed-Criticality Scheduling, Multi-Core Architecture Departmental Roles: Head of Department, Research Group Lead (Real-Time Systems) His recent research explores cache-aware scheduling, fault tolerance, and resource stress management in multi-core environments. He has contributed to journals like Microprocessors and Microsystems as an editor and collaborated on projects funded by EPSRC and industry partners such as Rolls Royce. He actively supervises PhD students and leads research initiatives related to wireless sensor networks, task allocation, and system certification for critical applications.
Xuehai Qian is a Tenured Full Professor in the Department of Computer Science at Tsinghua University since July 2024. Prior to this, he served as an Associate Professor at Purdue University (2022-2024), Assistant Professor at the University of Southern California (2015-2022), and Postdoctoral Researcher at the University of California Berkeley (2013-2015). Ph.D. in Computer Science, University of Illinois at Urbana-Champaign, USA (2013) ME in Computer Science and Technology, Institute of Computing Technology, Chinese Academy of Sciences, China (2007) BE in Computer Science and Technology, Beihang University, China (2004) His research focuses on parallel computer architecture , hardware/software co-designed domain-specific architectures for graph analytics and machine learning , hardware security , and quantum computer architecture . He has pioneered scalable cache coherence protocols for atomic block execution, hardware sequential consistency violation detection, and distributed frameworks for graph processing leveraging emerging memory technologies. Xuehai Qian’s publications span computer architecture , graph analytics , machine learning systems , and quantum computing , with a strong emphasis on distributed systems , accelerators , and memory optimization . His work includes novel architectures for graph processing, decentralized training protocols, and ReRAM-based accelerators for deep learning. NSF CAREER Award (2018) ACSIC (American Chinese Scholar In Computing) Rising Star Award (2019) IEEE Senior Member (2019) Hall of Fame inductions: ASPLOS (2018), HPCA (2019), ISCA (2021), MICRO (2021) W.J. Poppelbaum Memorial Award (2013) He has advised students who have received Microsoft Research Lovelace Fellowships , Ph.D. Fellowships , and Facebook Fellowships . His research has been supported by grants such as the NSF SPX project on FPGA-based machine learning platforms and smaller NSF grants. Notably, he has served as an Associate Editor for Science China (Information Sciences) since 2023 and as a Guest Editor for IEEE Transactions on Parallel and Distributed Systems (2019).
Donatella Sciuto is a Full Professor of Computer Science and Engineering at Politecnico di Milano, serving as Executive Vice Rector overseeing research strategies. She holds a PhD from the University of Colorado, Boulder and an MBA from Bocconi University. Her research focuses on embedded systems design, low-power electronics, and cyber-physical systems, with contributions to smart cities and ICT infrastructure. Education: Bachelor's in Electronic Engineering, Politecnico di Milano (1984) PhD in Electrical and Computer Engineering, University of Colorado, Boulder MBA, SDA Bocconi School of Management Research Interests: Embedded systems, multiprocessor architectures, hardware/software co-design, power-efficient computing, and building automation via IoT technologies. She leads the Embedded Systems Design research group at Politecnico di Milano and coordinates EU-funded projects in smart cities and reconfigurable systems. Awards: IBM Women Leaders in AI (2021) IEEE Fellow (2011) EDAA Fellow (2010) Outstanding Contribution Award, IEEE Computer Society (2009) Professional Roles: Board Member: Bank of Italy, Istituto Italiano di Tecnologia, STM, Avio Former President, IEEE Council of Electronic Design Automation (2011-2013) Executive Committee Member, Design Automation and Test in Europe (DATE) conference Labs/Teams: Leads the Embedded Systems Design and Design Methodologies group at Politecnico di Milano, collaborating with CEFRIEL on executive education programs in embedded systems and IoT.
Abdelhakim HAFID is a Full Professor at the University of Montreal , affiliated with the Faculty of Arts and Science and the Department of Computer Science and Operations Research . He leads the LRC — Laboratoire de recherche en réseaux de communication and is a member of several research centers including CIRRELT (interuniversity research center on enterprise networks, logistics, and transportation), the Cyberjustice Lab , and talents (AI for cybersecurity lab). His research focuses on Blockchain security , IoT , edge and fog computing , intelligent transport systems , and network resource management . He has supervised over 30 graduate students and led/co-led numerous research projects funded by agencies like NSERC , FRQNT , and MITACS . Notable projects include Blockchain Evolution: Quantum-Resistant Security (2025–2031) and Design and Management of Fog Networks (2019–2026). His work spans vehicular networks , mobile cloud computing , and machine learning for network optimization . He actively contributes to cybersecurity initiatives, including IoT authentication frameworks and AI-driven solutions for judicial systems (e.g., Cyberjustice ). Key Projects : Quantum-Resistant Blockchain Security (2025–2031) IoT Authentication via Blockchain and Intelligent SIM (2022–2026) Fog Network Design (2019–2026) Grants : NSERC Discovery Grants MITACS Acceleration Fellowships FRQNT Team Research Grants His lab collaborations include CIRRELT (logistics & transport) and Cyberjustice (digital law), reflecting interdisciplinary strengths in both technical and societal domains.
Donald Yeung is a Professor and Associate Chair for Undergraduate Education in the Department of Electrical and Computer Engineering at the University of Maryland , with an additional appointment as Affiliate Professor in the Department of Computer Science . His research focuses on Computer Architecture , particularly in memory systems , 3D integration , energy-efficient processors , and parallel processing . He leads projects like Monolithic 3D Integration of CPU and Main Memory and Approximate Computing . Recent work emphasizes ReRAM-based memory architectures , extreme-scale processor design , and micro-fluidic cooling solutions for 3D CPUs. His teaching includes courses like ENE 646: Computer Architecture and ENE 150: Intermediate Programming Concepts . Key achievements include the Best Paper Award at MULTIPROG-2017 and contributions to IEEE Micro and ACM Transactions . His research spans cache optimization , reuse distance analysis , and directory coherence protocols . Current grants include funding for heterogeneous microprocessor parallelism and low-power system design . Advises graduate students Yinuo Wang and Hung-Yu Yeh, and collaborates with teams like the UMIACS Technical Report Group . His lab focuses on memory-centric computing and scalable multicore systems .
Miquel Moreto Planas is a Senior Lecturer in the Department of Computer Architecture at the Barcelona School of Informatics, Universitat Politècnica de Catalunya (UPC). He is also affiliated with the Barcelona Supercomputing Center (BSC-CNS), a leading institution in high-performance computing. His academic profile is deeply rooted in computer architecture and high-performance computing, with a strong emphasis on practical and theoretical advancements in multicore systems, memory management, and hardware acceleration. His research interests span a wide range of topics including computer architecture, high-performance computing, multicore and manycore systems, cache and memory management, hardware acceleration for genomics and AI, RISC-V processor design, processing-in-memory, interconnection networks, and real-time systems. These interests are reflected in his extensive publication record and collaborative projects. The most recent articles highlight a significant trend toward interdisciplinary research, particularly the application of advanced computer architecture techniques to bioinformatics and healthcare. Key themes include the acceleration of genomic sequence alignment using novel hardware such as processing-in-memory, the development of benchmarks for ARM-based HPC systems in genomics, and the creation of AI-based 3D decision support tools for neurosurgical applications. His work also continues to advance core computer architecture topics like cache management, power-aware resource allocation in heterogeneous systems, and the design of secure, post-quantum cryptographic hardware based on RISC-V. Fulbright Award 2011 HiPEAC Paper Award HiPEAC Paper Award 2024 HiPEAC Paper Award Moreto has been a principal investigator or key contributor to multiple competitive R&D+i projects, such as the STRATUM project for neurosurgical tools, REDIOH for open hardware, and the Laboratorio Zettaescala de Barcelona. He has advised several doctoral students, including López, G., Kostalampros, I., and Haghi, A., and is a core member of the CAP (High Performance Computing) research group at UPC. His work is characterized by strong collaborations with leading researchers like Mateo Valero, Eduard Ayguadé, and Jesús Labarta, often bridging the gap between UPC and BSC-CNS. His laboratory and team affiliations are centered around the CAP group and the Barcelona Supercomputing Center, where he contributes to cutting-edge research in high-performance and embedded computer architectures. His recent work on the BIMSA accelerator and the STRATUM project demonstrates a clear future direction toward applying high-performance computing solutions to critical problems in genomics and medicine.
Keiji Kimura is a Professor in the Department of Computer Science and Engineering at Waseda University's Faculty of Science and Engineering, School of Fundamental Science and Engineering. He earned his Doctor of Engineering from Waseda University and has held academic positions at the university since 1999, progressing from Research Associate to Assistant Professor (2004-2005), Associate Professor (2005-2012), and Professor (2012-present). He is affiliated with multiple professional organizations including ACM, IEEE Computer Society, The Institute of Electronics, Information and Communication Engineers, and Information Processing Society of Japan. His research focuses on computer architecture, particularly parallel computing systems and compiler technology. Kimura has made significant contributions to the development of the OSCAR (Optimally Scheduled Advanced Multiprocessor) automatic parallelizing compiler framework. His work spans multiple areas including multicore processor architecture, power reduction techniques for embedded systems, non-volatile memory systems, and parallelization methods for heterogeneous architectures. His research interests specifically include Multiprocessor Architecture and Parallelizing Compiler development, with applications in real-time systems and energy-efficient computing. Analysis of his recent publications reveals a strong focus on practical implementations of parallel computing technologies across diverse hardware platforms including RISC-V, ARM, and heterogeneous multicore systems. His work demonstrates a consistent trajectory from theoretical compiler development toward practical applications in embedded systems, security, and non-volatile memory technologies. The publications show increasing emphasis on RISC-V architecture, persistent memory programming, and power-efficient computing solutions. MEXT Award for Science and Technology (Research category), 2014.04 Ministry of Education, Culture, Sports, Science and Technology (MEXT) Kimura has served on numerous prestigious conference program committees including PACT, IPDPS, HPCA, and LCPC. His research has been supported through collaborations with major technology companies and government initiatives such as the METI/NEDO project entitled "Multicore Technology for Realtime Consumer Electronics." His work with the OSCAR compiler framework has demonstrated significant performance improvements and power reductions in real-world applications. He leads research in the APAL laboratory (http://www.apal.cs.waseda.ac.jp/) at Waseda University, focusing on advanced parallel processing technologies. His team works on compiler-directed approaches to solve challenges in heterogeneous multicore architectures, with particular emphasis on making parallel programming more accessible while optimizing for both performance and power efficiency. Current research directions include RISC-V secure boot verification, non-volatile memory systems, and GPU-based persistent memory solutions.
Dr. Liqiang Zhang is a Professor at the Department of Computer and Information Sciences, Indiana University South Bend. He holds a Ph.D. in Computer Science from Wayne State University (2005). His research focuses on wireless networks, mobile computing, resource allocation, IoT, cognitive radio networks, and network security. His work is supported by IU and the National Science Foundation. He has organized multiple conferences including ICCCN 2013 (Track Chair), GLOBECOM 2010 (Publicity Co-Chair), and founded/co-chaired WiMAN workshops. He serves as a Guest Editor for journals like ACM Transactions on Autonomous and Adaptive Systems and Elsevier's Computer Communications. He reviews for top journals including IEEE Transactions on Mobile Computing and IEEE Transactions on Parallel and Distributed Systems. Dr. Zhang teaches courses such as Computer Structures, Mobile App Development, and Network Security. Recent publications (2019-2009) include advancements in network scheduling, cognitive radio protocols, radar positioning, and digital design education. His research spans both theoretical and applied aspects of networking and distributed systems.
Muhammad Awais Bin Altaf is a researcher specializing in biomedical engineering, machine learning, and wearable technology. His work focuses on low-power embedded systems for neurological and cardiovascular monitoring, including EEG processors for seizure detection and PPG-based blood pressure classification. He has collaborated extensively with co-authors like Wala Saadeh and Jerald Yoo on IEEE journals and conferences. His research interests include Biomedical signal processing Wearable health devices Machine learning for medical diagnostics Energy-efficient hardware design Neurological disorder detection Embedded systems for clinical applications Recent publications highlight trends in shallow neural networks, autoencoders, and hardware acceleration for real-time health monitoring. Key subfields span seizure prediction, stress detection, and impedance-adaptive sensors. Collaborations include institutions in Germany, Finland, and Pakistan. His work often integrates open-source toolflows and industry-standard chip design techniques, emphasizing practical implementations for wearable environments. Contributions to HDR imaging algorithms and biomedical SoCs demonstrate interdisciplinary expertise in signal processing and healthcare technology.
Prof. Timo Hönig is a Professor leading the Bochum Operating Systems and System Software (BOSS) Research Group at Ruhr-Universität Bochum (RUB). Previously, he served as an Assistant Professor at Friedrich-Alexander-University Erlangen-Nürnberg (FAU), where he was part of Department of Computer Science 4. His research focuses on Energy-Aware Computing Systems, Operating Systems, and System Software design with applications in embedded and real-time systems. Key research projects include the DFG Collaborative Research Center/TR 89 (Invasive Computing) and the DFG SPP 1914 (Latency- and Resilience-Aware Networking). He has received notable awards such as the SOSP SRC Gold Medal (2019) and the ISORC Best Paper Award (2017). He actively contributes to conferences like ACM EuroSys and USENIX ATC, and has led initiatives like the Albatross runtime system for energy-efficient HPC clusters. Teaching includes courses on Energy-Aware Computing and Operating Systems Technology. His work bridges theoretical system software design with practical applications in energy efficiency and heterogeneous architectures. The BOSS group explores future system software challenges for many-core and NVM-based systems.
