Jan Madsen is a Professor at DTU Compute, Technical University of Denmark, and Head of the Embedded Systems Engineering section. His research focuses on system-level modeling and design of embedded computing systems, particularly cyber-physical systems, microfluidic biochips, and synthetic biology applications. Develops design automation tools and methodologies for embedded systems Supervises numerous PhD students and leads major research projects Research Interests Key areas include: Embedded systems-on-a-chip Cyber-Physical Systems (Internet-of-Things) Microfluidic Lab-on-Chip devices Synthetic biology with molecular computing Design, modeling, and optimization of complex systems Scientific Awards DATE Fellow (2019) IEEE CEDA Outstanding Recognition (2019) DTU Scientific Advise Award (2013) Best Paper Awards at MECO (2013) and CASES (2009) Jorck’s Foundation Research Award (1995) Publications His 14+ journal papers and 115+ conference papers demonstrate expertise in: SystemC-based modeling frameworks Energy-aware sensor networks Self-healing eDNA architectures Microfluidic biochip synthesis RTOS modeling and MPSoC exploration
Jiang Hu is a Professor in the Department of Electrical and Computer Engineering at Texas A&M University, holding the Eric D. Rubin '06 Endowed Professorship. He also serves as Co-Director of Graduate Programs and is affiliated with the Computer Science & Engineering department. His research focuses on VLSI design automation, machine learning applications, and hardware security. He has held roles as editor for IEEE Transactions on CAD and ACM Transactions on Design Automation, and chaired the 2012 ACM International Symposium on Physical Design. Education: B.S. in Optical Engineering (Zhejiang University, 1990), M.S. in Physics (1997), and Ph.D. in Electrical Engineering (University of Minnesota, 2001). He worked at IBM Microelectronics before joining Texas A&M in 2002. Research interests include energy-efficient VLSI circuits, on-chip communication fabrics, analog layout automation, and AI-driven EDA. Recent work emphasizes machine learning for design closure, privacy-preserving frameworks, and systolic array-based architectures. Awards: IEEE Fellow (2016) Humboldt Research Fellowship (2012) Multiple best paper awards at DAC, ICCAD, and ASPDAC Advising and grants: Leads initiatives like the SLICE project, NSF workshops on ML-EDA infrastructure, and serves as Editor-in-Chief of ACM TODAES since 2024. His work bridges academic research and industry applications in EDA and semiconductor design. Labs/Teams: Active contributor to open-source tools like ALIGN for analog layout generation and collaborations on machine learning for EDA commons.
Labros Bisdounis is a Professor at the Department of Electrical and Computer Engineering, University of the Peloponnese, Greece. He previously held positions at the Technological Educational Institute of Western Greece, including Associate Professor, Full Professor, and Dean of the School of Technological Applications (2016–2018). He has extensive industry experience as a senior research engineer and project manager at Intracom S.A. (2000–2008), focusing on VLSI circuits and telecom applications. His research interests include CMOS circuit timing/power modeling, low-power/high-speed design, MOSFET modeling, and sensor applications. He has authored over 30 papers with 740+ citations and is an IEEE member. Education: Diploma in Electrical Engineering (1992), University of Patras Ph.D. in Electrical Engineering (1999), University of Patras Research Interests: CMOS circuit timing and power dissipation modeling Deep-submicron/nano-CMOS circuit design MOSFET device modeling Low-power embedded systems and SoC Sensor applications and organic electronics Leadership Roles: Dean of the School of Engineering, University of the Peloponnese (2023–present) Director of Training & Lifelong Learning Centre (2019–2019) Board Member, Hellenic NARIC (2016–2019) Collaborations: Active at the Hellenic Open University as a tutor in Computer Architecture and Digital Systems modules. Co-developed the AETHER framework for pervasive computing and contributed to energy-aware SoC designs for 5 GHz WLANs.
Iain Bate is a Lecturer in Real-Time Systems and Head of the Department of Computer Science at the University of York. His research focuses on scheduling and timing analysis, systems engineering with optimization of design trade-offs, design assurance, component-based engineering, and managing emergent behavior, particularly in critical systems. University of York, Department of Computer Science Research areas: Real-Time Systems, Mixed-Criticality Scheduling, Multi-Core Architecture Departmental Roles: Head of Department, Research Group Lead (Real-Time Systems) His recent research explores cache-aware scheduling, fault tolerance, and resource stress management in multi-core environments. He has contributed to journals like Microprocessors and Microsystems as an editor and collaborated on projects funded by EPSRC and industry partners such as Rolls Royce. He actively supervises PhD students and leads research initiatives related to wireless sensor networks, task allocation, and system certification for critical applications.
Mark Heinrich is an Associate Professor in the Department of Computer Science at the University of Central Florida (UCF), where he also serves as Undergraduate Coordinator for CS and IT, and Senior Design Coordinator. He previously held roles at Cornell University and has industry experience co-founding companies like Phanfare and Flashbase. His research focuses on parallel computer architecture, heterogeneous systems, cache coherence protocols, and multiprocessor simulation. Heinrich holds a Ph.D. in Electrical Engineering from Stanford University (1998) under John Hennessy, and a B.S. in Electrical Engineering and Computer Science from Duke University (1991). Research Interests His work spans parallel architectures, active memory systems, scalable cache coherence protocols, and hardware/software co-design. Recent efforts include innovations in persistent memory technologies and multiprocessor simulation methodologies. Teaching In Spring 2020, he taught CS Senior Design I and II courses (COP 4934/4935), with office hours focused on senior design and undergraduate coordination. Professional Background Associate Professor at UCF since 2003 Past roles: Director of UCF's School of Computer Science (2005), Associate Director of EECS (2005-2007) Co-founder of the Cornell Computer Systems Laboratory Contributed to the FLASH multiprocessor architecture and its simulation tools Labs & Projects He has been involved in projects like Active Memory Clusters and architectural support for multiprocessor systems. His work often bridges theoretical computer architecture with practical hardware implementations.
Donatella Sciuto is a Full Professor of Computer Science and Engineering at Politecnico di Milano, serving as Executive Vice Rector overseeing research strategies. She holds a PhD from the University of Colorado, Boulder and an MBA from Bocconi University. Her research focuses on embedded systems design, low-power electronics, and cyber-physical systems, with contributions to smart cities and ICT infrastructure. Education: Bachelor's in Electronic Engineering, Politecnico di Milano (1984) PhD in Electrical and Computer Engineering, University of Colorado, Boulder MBA, SDA Bocconi School of Management Research Interests: Embedded systems, multiprocessor architectures, hardware/software co-design, power-efficient computing, and building automation via IoT technologies. She leads the Embedded Systems Design research group at Politecnico di Milano and coordinates EU-funded projects in smart cities and reconfigurable systems. Awards: IBM Women Leaders in AI (2021) IEEE Fellow (2011) EDAA Fellow (2010) Outstanding Contribution Award, IEEE Computer Society (2009) Professional Roles: Board Member: Bank of Italy, Istituto Italiano di Tecnologia, STM, Avio Former President, IEEE Council of Electronic Design Automation (2011-2013) Executive Committee Member, Design Automation and Test in Europe (DATE) conference Labs/Teams: Leads the Embedded Systems Design and Design Methodologies group at Politecnico di Milano, collaborating with CEFRIEL on executive education programs in embedded systems and IoT.
Miquel Moreto Planas is a Senior Lecturer in the Department of Computer Architecture at the Barcelona School of Informatics, Universitat Politècnica de Catalunya (UPC). He is also affiliated with the Barcelona Supercomputing Center (BSC-CNS), a leading institution in high-performance computing. His academic profile is deeply rooted in computer architecture and high-performance computing, with a strong emphasis on practical and theoretical advancements in multicore systems, memory management, and hardware acceleration. His research interests span a wide range of topics including computer architecture, high-performance computing, multicore and manycore systems, cache and memory management, hardware acceleration for genomics and AI, RISC-V processor design, processing-in-memory, interconnection networks, and real-time systems. These interests are reflected in his extensive publication record and collaborative projects. The most recent articles highlight a significant trend toward interdisciplinary research, particularly the application of advanced computer architecture techniques to bioinformatics and healthcare. Key themes include the acceleration of genomic sequence alignment using novel hardware such as processing-in-memory, the development of benchmarks for ARM-based HPC systems in genomics, and the creation of AI-based 3D decision support tools for neurosurgical applications. His work also continues to advance core computer architecture topics like cache management, power-aware resource allocation in heterogeneous systems, and the design of secure, post-quantum cryptographic hardware based on RISC-V. Fulbright Award 2011 HiPEAC Paper Award HiPEAC Paper Award 2024 HiPEAC Paper Award Moreto has been a principal investigator or key contributor to multiple competitive R&D+i projects, such as the STRATUM project for neurosurgical tools, REDIOH for open hardware, and the Laboratorio Zettaescala de Barcelona. He has advised several doctoral students, including López, G., Kostalampros, I., and Haghi, A., and is a core member of the CAP (High Performance Computing) research group at UPC. His work is characterized by strong collaborations with leading researchers like Mateo Valero, Eduard Ayguadé, and Jesús Labarta, often bridging the gap between UPC and BSC-CNS. His laboratory and team affiliations are centered around the CAP group and the Barcelona Supercomputing Center, where he contributes to cutting-edge research in high-performance and embedded computer architectures. His recent work on the BIMSA accelerator and the STRATUM project demonstrates a clear future direction toward applying high-performance computing solutions to critical problems in genomics and medicine.
Luigi Pomante is a tenured Assistant Professor at the University of L'Aquila, Italy, where he is affiliated with the Department of Engineering and Information Science and Mathematics (DISIM) and the DEWS Center of Excellence. His academic career focuses on research and teaching in embedded systems and hardware-software co-design methodologies. Dr. Pomante's primary research interest is Electronic System-Level Hardware-Software Co-Design of heterogeneous parallel dedicated systems. He is the principal developer of the HEPSYCODE framework, which provides comprehensive methodologies and tools for system-level design space exploration. His work addresses critical challenges in embedded systems development, including handling functional and non-functional requirements, heterogeneous architectures, and mixed-criticality constraints. He has published extensively in journals like IEEE Transactions on Computers and IET Computers & Digital Techniques, as well as at major international conferences. Analysis of Dr. Pomante's publication record reveals a consistent research trajectory focused on hardware-software co-design methodologies, with increasing attention to real-time constraints and mixed-criticality systems in more recent work. His publications demonstrate expertise in design space exploration techniques, system modeling using CSP-like approaches, and the development of metrics for evaluating hardware-software partitioning solutions. The HEPSYCODE framework represents his most significant contribution to the field. Dr. Pomante actively supervises student projects and theses related to electronic design automation and embedded systems. He has contributed to European research projects including EMC2 (Embedded Multi-Core systems for Mixed Criticality applications), where he was responsible for deliverables related to design methodologies, implementation approaches, and validation frameworks. His work has practical applications in aerospace and other safety-critical domains through collaborations with industry partners. He leads the HEPSYCODE research group at DEWS, which focuses on developing methodologies and tools for hardware-software co-design of heterogeneous parallel dedicated systems. The group's current work includes extensions for real-time and mixed-criticality systems, frameworks for embedded system monitoring, and techniques for handling approximate computing and energy/power constraints within the design space exploration process.
Georgios Keramidas is an Assistant Professor in Computer Architecture at the Department of Informatics, Aristotle University of Thessaloniki . He also holds an Adjunct Professor position at the Hellenic Open University and collaborates with institutions like the University of Peloponnese and University of Patras . Research Interests : Computer Architecture, Memory Systems, Multicore/GPU Design, Low-Power Techniques, Fault-Tolerant Systems His work focuses on cache optimization , energy-efficient computing , and security-aware memory design . Key contributions include DVFS frameworks , reuse-distance prediction , and non-deterministic cache mechanisms . Recent article trends highlight innovations in computation-in-memory , IoT platform components , and security/low-power co-design . Patents on image compression and GPU optimization reflect practical applications of his research. Academic Network : Collaborates with institutions including University of Patras , University of Manchester , and TU Dresden
Mark A. Holliday is a Professor in the Department of Mathematics and Computer Science at Western Carolina University (WCU), part of the College of Arts and Sciences. He holds a Ph.D. (1986) and MS (1982) in Computer Science from the University of Wisconsin-Madison, and a B.A. in Mathematics and Economics from the University of Virginia (1978). His academic roles include serving as Interim Department Head (2007-2009) and Commissioner of the ABET Computing Accreditation Commission (2023-present). Research interests focus on enhancing student learning in computer systems, software development pedagogy, and grid computing concepts. Notable work includes developing memory diagrams for CS1 assessment and creating interactive animations for computer networking education. He has authored over 50 publications in journals like ACM Transactions and IEEE, covering topics such as parallel architecture performance, distributed systems, and educational frameworks. Teaching responsibilities include courses like CS 352 (Programming Languages), CS 453 (Database Systems), and CS 495/496 (Capstone Projects). Holliday’s lab work includes the National Storm Surge Database and the Educational Times Database projects. He actively contributes to curriculum development through initiatives like the Consortium for Distributed Computing Education.
Jürgen Teich is a Professor at the University of Erlangen-Nuremberg, Department of Computer Science. His research focuses on computer architecture, embedded systems, and hardware-software co-design, with particular emphasis on energy-efficient and sustainable computing. He leads projects involving FPGA-based accelerators, neural networks on microcontrollers, and real-time systems optimization. His work spans topics such as approximation computing, MPSoCs (Multiprocessor Systems-on-Chip), and IoT device architectures. Key contributions include methodologies for optimizing resource allocation in heterogeneous systems and developing energy-harvesting solutions for embedded systems. Teich has authored numerous publications in top-tier conferences and journals, including DATE, FPL, and ACM Transactions. His research often collaborates with industry partners, emphasizing practical applications and open-source hardware.
Cláudio Maia is a Lecturer and Integrated PhD Researcher at the Faculty of Engineering of the University of Porto, Portugal. He holds a B.Sc. and M.Sc. in Computer Engineering from the Polytechnic Institute of Porto and a Ph.D. in Electrical and Computer Engineering from the University of Porto (2018). His research focuses on real-time systems, including real-time operating systems, hypervisors, multiprocessor architectures, and scheduling theory. He has contributed to advancements in task scheduling for multiprocessor platforms, resource contention analysis, and WCRT (Worst-Case Response Time) methodologies. His work has been published in venues such as RTCSA, RTNS, and DATE, and includes a Best Paper award at ICESS 2021. He is affiliated with the CISTER Research Centre, where he collaborates on projects involving embedded systems, real-time critical CPS, and automotive systems integration. His recent research explores memory and bus contention analysis in real-time task models, with applications to multiprocessor systems and industrial automation. Education: Bachelor’s Degree (B.Sc.) in Computer Engineering, School of Engineering, Polytechnic Institute of Porto Master’s Degree (M.Sc.) in Computer Engineering, School of Engineering, Polytechnic Institute of Porto Ph.D. in Electrical and Computer Engineering, University of Porto (2018) Research Interests: Real-Time Scheduling (WCRT Analysis, Partitioned/Global Scheduling) Multiprocessor Architectures and Resource Contention Real-Time Operating Systems and Hypervisors Parallel Task Models (Fork-Join, 3-Phase Tasks) Embedded Systems and Cyber-Physical Systems (CPS) Awards: Best Paper Award at ICESS 2021 for 'Bus-Contention Aware WCRT Analysis' Key Contributions: Developed contention-aware scheduling models for real-time multiprocessor systems Advanced WCRT analysis techniques for 3-Phase Task Models Contributed to frameworks for automotive systems integration and CPS emulation Labs/Teams: Active member of the CISTER Research Centre, collaborating on industrial and academic projects in real-time systems and embedded computing.
Massachusetts Institute of TechnologyUnited States
Christopher Terman is a Senior Lecturer (Emeritus) at the Massachusetts Institute of Technology (MIT), affiliated with the School of Engineering and the Department of Electrical Engineering and Computer Science (EECS). He holds office in 32-G790 and can be reached at cjt@mit.edu. His research interests span digital communication systems, VLSI design methodologies, and educational technology innovations in engineering education. Terman has contributed extensively to the development of simulation tools for digital integrated circuits and has pioneered interactive learning environments for VLSI design education. His work integrates theoretical advancements with practical applications in both industry and academia. Over his career, Terman has authored influential papers on topics ranging from multiprocessor architectures to compiler optimization techniques, reflecting his interdisciplinary expertise in electrical engineering and computer science. His educational contributions include the design of MIT's 6.004 Computation Structures course, emphasizing scalable and learner-centered pedagogical strategies. Terman's publications demonstrate a sustained focus on bridging computational theory with real-world implementation challenges, particularly in the realms of digital signal processing and embedded systems. While no formal scientific awards are listed, his long-term academic leadership and contributions to foundational engineering education have had lasting impacts on both the field and MIT's curriculum. His work continues to inform modern approaches to integrating simulation, design automation, and collaborative learning in technical disciplines.
Johnny Öberg is an Associate Professor at the Division of Electronics and Embedded Systems, KTH Royal Institute of Technology. He specializes in embedded systems, FPGA design, and fault-tolerant hardware architectures. His research focuses on radiation effects in electronics, machine learning acceleration, and network-on-chip (NoC) systems. He teaches and examines courses such as Computer Systems Architecture (IS2202), Embedded Hardware Design in ASIC and FPGA (IL2225), and Embedded Systems Design Project (IL2232). His work often bridges theory and practice, emphasizing real-world applications in aerospace, automotive, and IoT domains. Key research trends include improving reliability in SRAM-FPGAs through statistical fault injection, developing hardware-accelerated machine learning frameworks, and optimizing NoC architectures for predictable performance in mixed-criticality systems. Recent projects include the SAFEPOWER architecture for energy-efficient systems and collaborations on structural health monitoring using Lamb wave analysis. No scientific awards are explicitly mentioned in the provided texts. Johnny has advised on multiple degree projects but no specific student names are listed. His contributions include foundational work in GALS (Globally Asynchronous, Locally Synchronous) communication bridges and protocol grammars for low-power implementations. Labs/teams: Active involvement in the ICES (Innovative Centre for Embedded Systems) and the Suaineadh project for space-deployable structures. Collaborates on interdisciplinary initiatives like the ABB NoC and Panacea NoC prototypes.
Swiss Federal Institute of Technology in LausanneSwitzerland
David Atienza Alonso is a Full Professor in the Department of Electrical and Electronics Engineering at the School of Engineering, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland. He leads the Embedded Systems Laboratory (ESL) and serves as Associate Vice President for Centers and Platforms, overseeing major research infrastructure. His work spans embedded systems, IoT, edge AI, and sustainable computing. His research interests focus on system-level design for high-performance and low-power computing systems. Key areas include thermal-aware design of multi-processor systems-on-chip (MPSoC), energy-efficient embedded machine learning, wireless body sensor networks, and electronic design automation (EDA). His lab develops novel methodologies for hardware-software co-design, memory optimization, and edge computing architectures. The analysis of his recent publications reveals a strong trajectory in intelligent, energy-efficient computing systems. His work integrates machine learning with traditional EDA techniques for data center optimization, applies ultra-low power heterogeneous architectures to healthcare wearables, and advances thermal modeling for 3D ICs. Themes of sustainability, real-time processing, and edge intelligence are consistent across his research. Dr. Atienza has received numerous accolades, including: ERC Consolidator Grant (2016) DAC Under-40 Innovators Award (2018) IEEE TCCPS Mid-Career Award (2018) ACM SIGDA Outstanding New Faculty Award (2012) ICCAD 10-Year Most Influential Paper Award (2020) Best paper awards at top-tier conferences He has advised over 40 PhD students, many of whom have gone on to successful academic and industry careers. His research has been supported by major grants, including the ERC grant, and he has co-authored over 450 publications and 14 licensed patents. He plays a significant leadership role in the academic community, having served as Editor-in-Chief of IEEE Transactions on CAD, President of IEEE CEDA (2018–2019), and currently as Chair of the European Design Automation Association (EDAA). He is a Fellow of both IEEE and ACM. His laboratory, the Embedded Systems Laboratory (ESL), is a leading center for research in embedded and cyber-physical systems, fostering interdisciplinary collaboration and innovation in sustainable computing technologies.
