Prof. Dr. Michael Gerndt is a Full Professor at the Chair of Computer Architecture and Parallel Systems , School of Informatics, Technische Universität München (TUM). His research focuses on cloud and IoT systems, high-performance computing (HPC), and performance analysis tools for parallel/distributed systems. Current projects: SEANERGYS , PlasmaPEPS , OpenCUBE , and MUNIQC-ATOMS Past projects: AutoTune , READEX , InvasIC , and CrossGrid Research Highlights: Developed the Periscope Tuning Framework and iOMP (OpenMP extension for invasive computing) Pioneering work in performance analysis, energy efficiency, and resource management in HPC and cloud systems Focus on AI-driven cloud operations, quantum-HPC integration, and hardware accelerators for machine learning Scientific Awards: Outstanding Paper Award, IEEE SC2 Symposium (2017) Teaching Contributions: Lectures: Parallel Programming Systems , Advanced Computer Architecture , Cloud Computing Lab courses: Efficient Programming of Multicore Processors , IoT Sensor Nodes Seminars: Hardware Accelerators for AI , Quantum Computing Integration Education & Career: PhD in Computer Science (1989, University of Bonn), postdoc at University of Vienna (1990-1991), habilitation at TUM (1998), Professor at TUM since 2000.
Dr. Frank Hannig is a Professor at the Department of Computer Science, Friedrich Alexander University Erlangen-Nuremberg (FAU), Germany. He serves as the Head of the Architecture and Compiler Design Group within the Hardware-Software-Co-Design department (Department 12). With a career spanning over two decades at FAU since 2003, he has established himself as a leading researcher in hardware-software co-design, compiler design, and embedded systems. Dr. Hannig received his Diploma degree in Electrical Engineering/Computer Science from the University of Paderborn in 2000, followed by his Dr.-Ing. degree in Computer Science from FAU in 2009 with a thesis on "Scheduling Techniques for High-Throughput Loop Accelerators." He completed his habilitation (Dr.-Ing. habil.) in 2018 with a thesis titled "Domain-specific and Resource-aware Computing," which qualifies him for a full professorship in the German academic system. His research focuses on hardware-software co-design, compiler design for embedded systems, reconfigurable computing, parallel systems, and machine learning acceleration. Dr. Hannig has made significant contributions to domain-specific and resource-aware computing, with applications in image processing, automotive systems, and edge AI. His work bridges the gap between high-level programming models and efficient hardware implementations, particularly for resource-constrained environments. Dr. Hannig's recent publications reveal a strong trend toward efficient machine learning deployment on embedded devices and microcontrollers, with particular emphasis on memory optimization, hardware acceleration, and low-precision computing. His research spans multiple domains including computer architecture, machine learning, and embedded systems, with a focus on practical implementations for real-world applications. Dr. Hannig serves as an Associate Editor for IEEE Embedded Systems Letters and the Journal of Real-Time Image Processing. He has organized numerous prestigious conferences including SLOHA 2021, ARC 2021, and Euro-Par 2021, demonstrating his leadership in the academic community. As an educator, Dr. Hannig teaches courses on Domain-Specific and Resource-Aware Computing on Multicore Architectures, Parallel Systems, and Embedded Systems. He has supervised numerous students through lectures, exercises, and seminars covering electronic system level design and multi-core architectures. Dr. Hannig leads several significant research projects including InvasIC (DFG Transregional Collaborative Research Centre), ExaStencils (Advanced Stencil-Code Engineering), and HBS (DFG Research Training Group on Heterogeneous Image Systems). His work with the HIPAcc open-source project has contributed to domain-specific language and compiler development for image processing applications.
Mahmut Kandemir is a Professor in the Department of Computer Science and Engineering at Pennsylvania State University, where he leads the Microsystems Design Lab. His work bridges compiler design, runtime systems, and hardware-software co-design for energy-efficient computing. Education: B.S. in Computer Engineering, Istanbul Technical University (1988) M.S. in Computer Engineering, Istanbul Technical University (1992) Ph.D. in Computer Science, Syracuse University (1999) Research Interests span optimizing compilers, runtime systems, embedded systems, high-performance storage, power-aware computing, and multi-core architectures. His innovations include compiler-directed techniques to address memory bottlenecks, adaptive runtime systems for dynamic resource allocation, and energy-efficient designs for GPUs and 3D NAND SSDs. Publication Trends highlight interdisciplinary work integrating machine learning into hardware-software co-design. Key focus areas include graph neural networks (KDD, NeurIPS), GPU-optimized molecular docking (J. Chem. Inf. Model.), 3D NAND SSD resource allocation (HPCA, ASPLOS), and energy-efficient VR streaming (ISCA). Awards & Honors: NSF CAREER Award Penn State Premier Research Award IEEE Fellow Best Paper Award at DATE 2007 Top Download from ACM Digital Library (2006) Advising & Grants include mentoring 15 Ph.D. and 5 master’s students, with 32 Ph.D. and 20 master’s graduates. His research is funded by NSF, DOE, DARPA, SRC, Intel, and Microsoft, spanning 11 active projects. Labs & Collaborations include the Microsystems Design Lab at Penn State and partnerships with Argonne National Lab, Microsoft, HP Labs, Intel, and NVIDIA. His work has transitioned into product file systems for large-scale simulations in astrophysics and computational chemistry.
Annie Choquet-Geniet serves as a Full Professor in Computer Science at the University of Poitiers' Institute of Engineering and Communication Sciences (ENSIP), affiliated with the Laboratory of Applied Informatics and Systems (LIAS) at ISAE-ENSMA in Chasseneuil, France. Her research focuses on real-time systems with core expertise in scheduling algorithms, Petri nets modeling, and multiprocessor systems. Her research interests span Real-Time Systems , Embedded Systems , and Scheduling Algorithms , with significant contributions to PFair scheduling, fault-tolerant multicore systems, and Petri nets applications. Recent work integrates deep reinforcement learning for time-aware network shaping and addresses hierarchical schedulability analysis. Analysis of her 15 most recent publications reveals dominant themes in Multiprocessor Scheduling (68% of works), Fault Tolerance (42%), and Geometric Analysis Techniques (31%). Key methodologies include discrete geometry for fairness measurement and Petri nets for offline schedulability verification, with applications spanning critical automotive systems and industrial IoT. Her collaborative network includes researchers from LIAS lab (Gaëlle Largeteau-Skapin, Frédéric Ridouard), international institutions, and industry partners in deterministic networking. Current projects focus on IEEE 802.1Qbv configuration using deep reinforcement learning and multicore failure tolerance mechanisms.
Eddie Kohler is the Microsoft Professor of Computer Science at Harvard University's Harvard John A. Paulson School of Engineering and Applied Sciences (SEAS), where he also serves as Director of Undergraduate Studies in Computer Science. His research focuses on high-performance systems, networks, and databases with an emphasis on concurrency control, data privacy, and scalable software design for multicore processors. He has contributed to foundational work in transactional systems, web application backends (e.g., Noria), and privacy-preserving technologies (e.g., Edna). His research spans theoretical frameworks like the Scalable Commutativity Rule and practical implementations such as the Alto lightweight virtualization system. Kohler's work often bridges theory and practice, addressing challenges in distributed systems, sensor networks, and regulatory compliance (e.g., GDPR). Notable contributions include innovations in in-memory database concurrency, optimistic transaction processing, and network congestion control protocols (e.g., TFRC-SP). His projects frequently emphasize system correctness through formal verification and empirical evaluation. His articles reflect a trajectory from foundational concurrency research to applied systems engineering, with recent focus on privacy in web applications and optimizing modern multicore architectures. No specific grants or advisees are listed in the provided information. Kohler leads research initiatives in scalable systems and maintains active collaboration with industry through his academic leadership roles.
Nathan Fisher is Professor of Computer Science at Wayne State University's College of Engineering. He earned his PhD from the University of North Carolina at Chapel Hill in 2007, specializing in real-time systems and embedded computing. His research develops scheduling algorithms and resource allocation strategies for secure, efficient computing systems. Fisher's work spans security-aware scheduling models, cache optimization for multicore processors, and swarm robotics coordination. Recent publications focus on limited-preemption scheduling, adaptive task management, and hardware-software co-design approaches for real-time systems. He teaches graduate seminars on advanced computing topics and has developed novel scheduling frameworks that balance performance with security constraints in cyber-physical environments.
Paulo Garcia is an Assistant Professor in the Department of Systems and Computer Engineering at Carleton University, Ottawa, Canada. He holds a Ph.D. in Computer Engineering from the University of Minho, Portugal, with research periods at Asian Institute of Technology and University of Würzburg. His academic roles include serving as a faculty member, thesis chair/examiner, and committee member in multiple university initiatives. Research Focus: Embedded real-time systems, hardware/software co-design, FPGA acceleration, and engineering pedagogy. Specific technical areas include multicore architectures, runtime systems, and hardware accelerators for embedded applications. His work emphasizes synergies between processor architectures, compilers, and FPGA-based solutions. Teaching: Courses include SYSC 3310 (Real-Time Systems), SYSC 4310 (Computer Architecture), and SYSC 5807 (Hardware/Software Co-Design). He supervises senior projects like robotic systems and eHealth wearable devices. Awards & Grants: Includes 2020 awards from General Dynamics Mission Systems and Carleton’s Rapid Response Grant, plus multiple scholarships from FCT Portugal and EU programs. His research has been supported by industry partnerships and defense collaborations. Service: Active in academic service as a thesis evaluator, member of student mental health committees, and representative in university governance bodies. Engaged in curriculum development and embedded systems program revisions.
Vasileios Karakostas is an Assistant Professor at the Department of Informatics and Telecommunications, National and Kapodistrian University of Athens. He is a member of the Computer Architecture Lab and focuses on computer architecture, memory systems, and resource management. Previously, he was a postdoctoral researcher at the National Technical University of Athens' Computing Systems Lab. He holds a PhD in Computer Architecture from Universitat Politècnica de Catalunya and Barcelona Supercomputing Center. Education: Ph.D. in Computer Architecture, Universitat Politècnica de Catalunya (2016) M.Sc. in Computer Architecture, Networks, and Systems, UPC (2012) B.Eng. in Electrical and Computer Engineering, NTUA (2009) Research Interests: Memory systems (virtual memory, NVM) Hardware/OS interaction Resource management in data centers Parallel systems and serverless computing RISC-V architectures and cloud infrastructure Projects: Active in Horizon Europe projects Vitamin-V, Neuropuls, and REBECCA. Previously contributed to DAPHNE and ACTiCLOUD (EU H2020). Awards: 2024: Distinguished Artifact Award (ASPLOS) 2011: Best Paper Award (ICPE) Selected for IEEE Micro's Top Picks (2015, 2016) Teaching: Courses include Logic Design, Parallel Systems, and Large-scale Computing Systems at undergraduate and graduate levels. Labs/Teams: Leads research in the Computer Architecture Lab, collaborating on resilient architectures and cloud computing innovations.
Anant Agarwal is a Professor of Electrical Engineering and Computer Science at MIT, holding the rank of 'Professor Post-Tenure' in both CS and EE disciplines. He serves as CEO of edX, a leading platform for open online education. His primary affiliation is with the MIT Electrical Engineering & Computer Science Department within the MIT College of Engineering. Agarwal's research focuses on computer architecture, parallel processing, caching systems, and the integration of AI in clinical information systems. He has pioneered work on multicore processors, memory management, and self-optimizing computing systems. His academic contributions span over two decades, with notable advancements in tiled processor architectures, cache coherence protocols, and the design of energy-efficient embedded systems. Agarwal has been instrumental in developing MITx and edX, revolutionizing online education through scalable platforms like the 6.002x Circuits course. His work emphasizes blending traditional and digital learning modalities to enhance global access to education. Key research themes include parallel computing, machine learning applications in healthcare, and the future of higher education. His publications reflect a sustained focus on improving system performance, optimizing data management, and advancing educational technologies. Agarwal's leadership at edX underscores his commitment to democratizing access to world-class learning resources.
Brian Sierawski is a Research Associate Professor in the Department of Electrical and Computer Engineering at Vanderbilt University's School of Engineering, serving as Associate Director. His research focuses on radiation effects on microelectronics, simulation software development, small satellites, and on-orbit experiments. He also teaches courses on microcontrollers, FPGAs, and spacecraft systems. Education: Ph.D. in Electrical Engineering (Vanderbilt University), M.S.E. in Computer Science and Engineering (University of Michigan), B.S.E. in Computer Engineering (University of Michigan). Research interests emphasize radiation-hardened electronics, space system reliability, and radiation modeling tools like the SIRE2 toolkit. His work bridges academic research with practical applications in satellite design and radiation assurance. Awards: Received the Outstanding Conference Paper Award at the 2024 IEEE Nuclear and Space Radiation Effects Conference and the 2014 equivalent. These recognize contributions to understanding radiation effects in advanced electronics. Advising and grants: Leads initiatives like the RadFxSat mission, focusing on radiation effects in space. His team develops methodologies for radiation hardness assurance in commercial-off-the-shelf (COTS) components, enhancing mission reliability for small satellites. Labs/Teams: Collaborates on projects involving CubeSats, radiation climatology, and Bayesian modeling for component degradation. His work integrates computational tools with experimental validation for real-world space applications.
Frank Bellosa is a Professor and head of the Operating Systems Group at the Karlsruhe Institute of Technology (KIT). Previously, he held roles at the University of Erlangen, including Assistant Professor and researcher in the Operating Systems Department. He earned his PhD from the University of Erlangen in 1998, focusing on memory-conscious scheduling in multiprocessor systems. His research interests center on energy-aware systems, including OS-directed power management, thermal management in distributed systems, and flexible operating system architectures. Key projects include Event-Driven Clock Scaling (Process Cruise Control) and Energy-Aware Memory Management. He has advised numerous students on topics like temperature-aware scheduling and power management for embedded systems. Bellosa's publications span dynamic thermal management, cooperative I/O, and energy-efficient file systems. His work emphasizes reducing energy consumption while maintaining performance through innovative OS mechanisms. He has contributed to international conferences and workshops, including EuroSys and USENIX, and serves on program committees for major systems conferences. Current roles include leading the Operating Systems Group at KIT and contributing to initiatives like the Disruptive Memory Systems workshop. His research bridges hardware and software, addressing challenges in modern computing systems' efficiency and scalability.
Mohamed Zahran is a Clinical Professor of Computer Science at New York University's Courant Institute of Mathematical Sciences. He holds a Ph.D. in Electrical and Computer Engineering from the University of Maryland (2003) and has extensive experience in academia and industry, including roles at CUNY and The George Washington University. His research focuses on computer architecture, heterogeneous systems, parallel computing, and AI-driven hardware optimization. Education: Ph.D., Electrical and Computer Engineering, University of Maryland (2003); M.Sc., Cairo University (1999); B.Sc., Cairo University (1997). Research interests include exascale computing, GPU architectures, cache hierarchy design, and AI support for architecture. He has authored over 40 refereed papers and a book on heterogeneous computing. Awards include ACM Distinguished Speaker (2019–2025) and IEEE Distinguished Contributor (2021). Teaching: Courses on multicore processors, GPUs, parallel computing, and compilers. Advised numerous graduate and undergraduate students, including notable achievements in student research competitions.
Luis Alfonso Train Arrontes is a Full Professor at the Electronic Technology Department of Carlos III University of Madrid, affiliated with the Pedro Juan de Lastanosa Institute of Technology Development and Innovation and the Microelectronic Design and Applications (DMA) research group. His work focuses on radiation effects on microprocessors, fault-tolerant architectures, and error mitigation techniques for aerospace applications. Key Research Areas: Radiation-hardened electronics, FPGA-based fault injection, approximate computing, lockstep architectures, and GPU-accelerated systems. Notable Projects: Principal Investigator for RADNEXT (European Commission, 2021–2026), Modulos Hardware de Alta Fiabilidad para RISC-V (AEI, 2024–2025), and Diseño y verificación de sistemas en chip heterogéneos (AEI, 2020–2023). Publications: Over 40 peer-reviewed articles in journals like IEEE Transactions on Nuclear Science , IEEE Access , and Microelectronics Reliability , covering topics such as radiation-induced errors, fault detection, and self-repairing hardware. Patents: Co-inventor of a 2019 patent for an integrated circuit identification device. His research bridges hardware design, radiation physics, and aerospace engineering, with applications in space-grade electronics and terrestrial radiation environments.
Kunle Olukotun is the Cadence Design Systems Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a faculty member since 1991. He is a pioneer in multicore processor design, leading the Stanford Hydra CMP project and founding Afara Websystems (acquired by Sun Microsystems), which developed the Niagara processor. Currently, he co-leads SambaNova Systems as Chief Technologist and directs the Pervasive Parallelism Lab (PPL), focusing on domain-specific languages (DSLs) and machine learning infrastructure. Education: PhD in Computer Engineering from the University of Michigan (1991). Research interests include parallel computing architectures, transactional memory, and scalable systems. Awards include ACM Fellow, IEEE Fellow, and the Harry H. Goode Memorial Award. Key projects include the Hydra chip multiprocessor, Transactional Coherence and Consistency (TCC), and modern initiatives in dataflow architectures and AI acceleration. His work spans over 100 publications, emphasizing compiler design, hardware-software co-design, and high-performance computing. Current roles: Director of PPL and DAWN Lab, advisor to multiple students, and leader in industry collaborations like SambaNova’s dataflow accelerators. His research bridges academic innovation with commercial impact, addressing challenges in parallelism and scalable systems.
Paulo Flores holds the position of Associate Professor at the Department of Electrical and Computer Engineering within the Instituto Superior Técnico of the University of Lisbon. His academic career is deeply rooted in Electronics and Digital Systems, with a focus on VLSI design, FPGA optimization, and hardware acceleration for bioinformatics applications. He has contributed extensively to research in multiplierless constant multiplication algorithms, low-power circuit design, and quaternary logic implementations. Notable achievements include the SAT Competition 2014 and 2013 Bronze Medals for innovative contributions in formal methods and algorithmic efficiency. His teaching responsibilities include advanced courses in digital systems design, electronic engineering projects, and laboratory guidance in topics like operational amplifiers and FIR filters. Flores actively collaborates with research units like INESC-ID and has supervised multiple academic projects in electronic engineering and digital signal processing. Research interests span across circuit testing, embedded systems optimization, and multi-valued logic architectures. His work frequently explores trade-offs between computational efficiency and energy consumption in hardware implementations.
