Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.
Giacomo Indiveri is a dual Professor at the Faculty of Science of the University of Zurich and the Department of Information Technology and Electrical Engineering of ETH Zurich . He serves as the Director of the Institute of Neuroinformatics at both institutions. Indiveri holds an M.Sc. in Electrical Engineering (1992) from the University of Genoa and a Ph.D. in Computer Science (2004) from the same university. Primary Affiliation: University of Zurich (Faculty of Science, Institute of Neuroinformatics) Secondary Affiliation: ETH Zurich (Department of Information Technology and Electrical Engineering) Indiveri's research bridges neuroscience , computer science , and machine learning to develop neuromorphic cognitive systems . His work focuses on spike-based learning , recurrent neural networks , and analog/digital circuit design for real-time sensory-motor systems . He integrates emerging memory technologies into fault-tolerant event-based architectures, enabling brain-inspired computing paradigms in applications like robotics and medical monitoring. His recent publications emphasize neuromorphic hardware for epileptic seizure detection , spiking neural networks in robotic painting , and scalable processors with on-chip learning . These works explore biologically plausible neurons , delay lines , and memory arrays for temporal processing, with applications in healthcare , edge computing , and adaptive control . Scientific Awards & Recognitions: 2021 IEEE Biomedical Circuits and Systems Best Paper Award Senior Member of IEEE Society ERC Fellow with three European Research Council grants Indiveri's group at the Institute of Neuroinformatics develops event-based systems for real-world validation of brain-inspired computing. His work includes multi-core processors , feedback optimizers , and dynamic routing architectures , supported by grants for advancing neuromorphic technologies .
Takeshi Ikenaga is a Professor at Waseda University’s School of Fundamental Science and Engineering and Graduate School of Information, Production and Systems . He earned his Ph.D. in Information & Computer Science from Waseda University in 2001, following B.E. and M.E. degrees in Electrical Engineering (1988–1990). His career spans roles at NTT LSI Laboratories (1990–2002), Kitakyushu Foundation for Advancement of Industry, Science and Technology (FAIS) (1999–2002), and visiting researcher at the University of Massachusetts (1999–2000). Research Interests : Application-specific SoCs for video/image processing, including compression (H.264/AVC, H.265/HEVC), filters (super-resolution, noise reduction), recognition systems (feature detection, object tracking), and communication (UWB, LDPC). He also works on many-core processor design, ultra-low-delay vision systems, and sports analytics (volleyball, figure skating) with real-time 3D pose estimation and ball tracking. Awards : Recipient of the Furukawa Sansui Award (Waseda University, 1988) IEICE Research Encouragement Award (1992) Multiple Best Paper/Presentation Awards (2006–2022) at conferences including DAC/ISSCC, LSI IP Design, ISOCC, ISPACS, and CVIT APSIPA Distinguished Lecturer Certificate (2015) Waseda University Presidential Teaching Award (2020)
Mirjana Stojilovic is a Researcher at École Polytechnique Fédérale de Lausanne (EPFL) in the School of Computer and Communication Sciences (IC), specifically within the Institute of Computer Engineering (IINFCOM) and the Parallel Systems Architecture Laboratory (PARSA). She also serves as a Lecturer in the SSC - Teaching department at EPFL. Her office is located at INJ 235, Station 14, 1015 Lausanne, Switzerland. Mirjana Stojilović received her Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. Her academic journey includes collaborating with the Processor Architecture Laboratory at EPFL as a Guest Researcher from 2010 to 2013, working at the University of Applied Sciences Western Switzerland as a senior researcher from 2013 to 2016, and joining the Parallel Systems Architecture Lab at EPFL in October 2016. Dr. Stojilovic's research spans field-programmable technology, electronic design automation (EDA), and electrical-level attacks and countermeasures for reconfigurable hardware. Her work bridges the gap between hardware design and security, with a particular focus on vulnerability analysis and protection mechanisms for FPGA-based systems in cloud environments. She has made significant contributions to understanding side-channel attacks, fault injection techniques, and secure multi-tenancy solutions for shared hardware resources. Her extensive publication record reveals a clear research trajectory from traditional FPGA design and EDA topics toward increasingly security-focused investigations. Recent work demonstrates deep expertise in power analysis attacks, hardware trojans, and countermeasures for cloud-based FPGA systems, reflecting the growing importance of hardware security in distributed computing environments. Scientific Awards and Recognitions: Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016) Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016) Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012) EPFL School of Computer and Communication Sciences (IC) Teaching Award (2015) Nominated for Best Paper Award at the International Conference on Field-Programmable Technology (FPT) (2020) Dr. Stojilovic has advised numerous PhD students including Coulon Louis, Pirayadi Rouzbeh, and Shrivastava Shashwat, along with past EPFL PhD students Glamocanin Ognjen and Mahmoud Dina. She has supervised dozens of semester and diploma projects focusing on hardware security, FPGAs, design automation, side-channel attacks, and cloud computing. Her service to the academic community includes serving on program committees for FPGA, FCCM, FPL, and DATE conferences, reviewing for multiple IEEE and ACM journals, and acting as associate editor for IEEE ESL and ACM TRETS. As a member of the Parallel Systems Architecture Laboratory at EPFL, Dr. Stojilovic leads research projects investigating security aspects of reconfigurable hardware systems. Her team works at the intersection of computer architecture, electronic design automation, and hardware security, with particular emphasis on vulnerabilities and protections for shared FPGA resources in cloud environments.
Kyle C. Hale is an Associate Professor at Oregon State University's School of Electrical Engineering and Computer Science (College of Engineering). He holds a Ph.D. and M.S. from Northwestern University (2016, 2013) and a B.S. in Computer Science from UT Austin (2010). Prior to joining Oregon State in 2024, he served as an Associate Professor at Illinois Tech in Chicago. His research spans operating systems, high-performance computing (HPC), virtualization, computer architecture, and system security. Current work focuses on specialized system software stacks for emerging computing paradigms like memory disaggregation and parallelism optimization. He leads the HExSA Lab and collaborates with the HiPCastor group. Scientific Awards: NSF CAREER Award (2023-2028) Illinois Tech College of Computing Excellence in Research (2023) Illinois Tech College of Computing Excellence in Teaching (2021) Illinois Tech Department of Computer Science Teacher of the Year (2020) EuroSys '22 Best Artifact Award Recent Research Trends: His publications emphasize compiler techniques for memory-disaggregated systems, optimizing parallel runtimes through hardware-software integration, virtualization at fine granularities, and accelerating machine learning workloads via system-level innovations. Keywords include HPC, virtualization, parallelism, and secure execution contexts. Teaching: Courses taught include Computer Architecture (CS/ECE 472), System Security (CSP 544), Operating Systems (CS 450), and advanced topics in serverless/edge computing. He actively recruits PhD students to the HExSA Lab.
Mehmet Esat Belviranli is an Assistant Professor in the Computer Science Department at the Colorado School of Mines, where he directs the High Performance Systems and Software Lab (HyperSys). His research focuses on increasing resource utilization in heterogeneous architectures through runtime systems, scheduling algorithms, and performance modeling, with publications in top venues including MICRO, PPoPP, and SC. Education: Ph.D. in Computer Science, University of California, Riverside (2016) M.S. in Computer Science, Bilkent University (2009) B.S. in Computer Science, Bilkent University (2006) Belviranli's research spans heterogeneous architectures, runtime systems, performance modeling, parallel programming, autonomous computing, deep learning acceleration, cyber-physical systems, and edge-cloud platforms. His work develops analytical models and programming abstractions to address resource management, scheduling, and security challenges in diversely heterogeneous systems, with applications in edge computing, autonomous systems, and machine learning acceleration. Recent projects emphasize real-world constraints and security implications. His publication trends reveal increasing focus on edge-cloud resource management (e.g., HARNESS), security vulnerabilities in heterogeneous systems (e.g., MC3), and deep learning acceleration under resource constraints. Key themes include memory contention modeling, scheduling for cyber-physical systems, and concurrent DNN execution, reflecting a shift toward practical deployment in security-sensitive edge environments. Scientific Awards: U.S. Air Force Research Lab Summer Faculty Fellowship Award (2022) U.S. Air Force Research Lab Summer Faculty Fellowship Award (2021) Oak Ridge National Laboratory Significant Event Award (2019) Best Paper Finalist, IEEE HPEC 2018 Outstanding Paper Award, DATE 2024 Belviranli mentors Ph.D. students Ismet Dagli (MLCommons Rising Star 2024, CGO'24 SRC finalist) and Justin Davis (DATE'24 Outstanding Paper Award winner). He has secured $2M+ in funding from NSF, DoE, and SRC, including an NSF-SaTC grant on mobile security (2024), a DoE grant on superconductive systems (2023), and an NSF FuSe grant on graphene nanoribbons (2023), often leading multi-institutional teams from Rochester, Virginia, Arizona, and Minnesota. The HyperSys Lab develops ecosystems for high-performance heterogeneous systems, with recent projects including HARNESS for edge-cloud resource management and MC3 for mobile SoC security. The lab has received equipment donations from Google Coral.ai and Xilinx, and collaborates with national labs on security challenges and next-generation semiconductor technologies.
Monica Lam is the Kleiner Perkins, Mayfield, Sequoia Capital Professor in Stanford University's School of Engineering and holds a courtesy professorship in Electrical Engineering. She leads the Stanford Open Virtual Assistant Laboratory and has pioneered work in virtual assistants, privacy protection, and compiler design. Her research includes the Almond virtual assistant, privacy-preserving IoT systems, and the ThingTalk programming language. She co-authored the seminal 'dragon book' on compilers and co-founded Tensilica (now part of Cadence). Education: Bachelor of Science (Honors), Computer Science, University of British Columbia, 1980 Master of Science, Computer Science, Carnegie Mellon University, 1982 Doctor of Philosophy (PhD), Computer Science, Carnegie Mellon University, 1987 Research Interests: Dr. Lam's work focuses on conversational AI with privacy guarantees, compiler optimization for parallel computing, and open-source virtual assistant ecosystems. She is a leader in decentralized systems, having developed frameworks like SociaLite for large-scale graph analysis and Musubi for mobile social networking without centralized platforms. Article Trends: Recent publications emphasize multimodal interactions, multilingual dialogue systems, and LLM-driven applications in areas like question answering, persuasive chatbots, and adaptive assistants. Her work bridges foundational AI research (e.g., semantic parsing) with real-world deployments (e.g., privacy-compliant IoT). Awards & Honors: Member of the National Academy of Engineering ACM Fellow Popular Science's Best of What's New Award (Security, 2019) Advising & Grants: Lam oversees the Open Virtual Assistant Initiative, a collaborative project to build open-source semantic models. Her NSF CNS grant (CNS Core) focuses on federated privacy systems. She has advised over 50 students in AI and systems research, though specific names are not listed in the provided texts. Labs & Teams: Directs the Stanford Open Virtual Assistant Laboratory, collaborates with the Stanford NLP group, and maintains ties to industry through former startup Tensilica's legacy in embedded processors.
Michela Becchi is an Associate Professor in the Department of Electrical and Computer Engineering at North Carolina State University. She specializes in computer architecture, systems software, and applications, with a focus on heterogeneous systems, parallel algorithms, and acceleration techniques for bioinformatics, pattern recognition, and quantum computing. Her work spans multi-core CPUs, GPUs, FPGAs, and distributed clusters, emphasizing the boundary between hardware and software design. Dr. Becchi holds a Ph.D. and Master’s degree in Computer Engineering from Washington University in St. Louis (2009) and a Bachelor’s degree in Computer Engineering from Politecnico di Milano, Italy (2000). Her research has been recognized with prestigious awards, including the NSF CAREER Award (2015) and the University of Missouri System President Award for Early Career Excellence (2016). Her research interests include compiler and runtime techniques for heterogeneous systems, acceleration of bioinformatics algorithms, and high-speed networking applications. She has pioneered frameworks for efficient data transformation, GPU-accelerated compression, and memory-efficient graph algorithms for quantum computing. Her work also explores thread coarsening, mixed-precision auto-tuning, and secure multi-core processor design. Key contributions include the PILOT runtime system for GPU memory management, the GPU-FPtuner auto-tuner for floating-point applications, and innovative approaches to automata processors for genomic analysis. Her publications emphasize reproducible accuracy in scientific simulations and the optimization of irregular applications on many-core platforms.
Natalie Enright Jerger is a Professor in the Department of Electrical and Computer Engineering at the University of Toronto's Faculty of Applied Science and Engineering. She holds the Canada Research Chair in Computer Architecture and serves as Director of the Division of Engineering Science (2023-2028). Previously, she was the Percy Edward Hart Professor (2016-2019). She received her B.S. in Computer Engineering from Purdue University (2002), and M.S./Ph.D. in Electrical Engineering from University of Wisconsin-Madison (2004/2008). Her research focuses on: Multi/many-core architectures and on-chip networks Cache coherence protocols and memory hierarchy optimization Approximate computing and sustainable systems Intermittent computing for energy-harvesting devices Hardware acceleration for machine learning Her publications demonstrate strong emphasis on networks-on-chip (NoC) innovations, including routing algorithms, deadlock handling, power-efficient designs, and topology optimizations. Recent work expands into approximate computing, mobile architectures, and ML-driven hardware design. Major Awards: Fellow of Engineering Institute of Canada (2023) McLean Senior Fellow (2019) IEEE Micro Top Picks (2016) ACM/IEEE Microarchitecture Hall of Fame (2015) Sloan Research Fellowship (2015) Canada Research Chair (current) Distinguished Scientist, ACM Fellow, IEEE She leads the NEJ research group and collaborates with industry partners including Intel, AMD, Qualcomm, and IBM. Her work is funded by NSERC, CFI, and industrial grants. She co-chaired ASPLOS 2023 and HPCA 2014, and actively promotes diversity through WICARCH and ACM initiatives.
Marco Caccamo is a Professor at the Technical University of Munich (TUM) , holding the Chair of Cyber-Physical Systems in Production Engineering within the Faculty of Mechanical Engineering. He is also a Principal Investigator and Professor at the Department of Computer Science, with courtesy appointments in Electrical and Computer Engineering, Coordinated Science Lab (CSL), and Aerospace Engineering at the University of Illinois at Urbana-Champaign (UIUC). His research spans Embedded Systems , Real-Time Systems , and Cyber-Physical Systems (CPS) , focusing on resource management, reinforcement learning architectures, and 6D pose recognition for robotics. University of Pisa (B.Sc., 1997) Scuola Superiore Sant'Anna (Ph.D., 2002) Research highlights include predictable resource management on heterogeneous platforms, security frameworks for AI-based controllers , and UAV testbed development . His work integrates deep learning and real-time constraints in industrial applications like avionics, farming, and automotive systems. His 15 most recent publications emphasize cache optimization , memory bandwidth regulation , and reinforcement learning for CPS , with a focus on multi-core processors and DNN inference . Awards include the IEEE Fellow (2018), Alexander von Humboldt Professorship (2018), and multiple Best Paper Awards at RTSS, RTNS, and RTAS. NSF CAREER Award (2003) IEEE Fellow (2018) Alexander von Humboldt Professorship (2018) Best Paper Awards (RTSS 2024, RTNS 2023, ECRTS 2019) He has advised numerous Ph.D. students and postdocs, with a track record in UAV development and industrial collaborations . His lab, the Real-Time and Embedded System Laboratory , focuses on real-time OS and predictable computing .
Dr. Alessandro Ottaviano is a Researcher affiliated with the Department of Digital Integrated Circuits and Systems at ETH Zürich. His work focuses on advanced computer architecture and embedded systems, particularly in the domains of RISC-V processors, real-time systems, and heterogeneous computing. He contributes to the design of time-predictable virtual memory solutions, mixed-criticality systems, and energy-efficient hardware-software interfaces. Key research areas include modular processor architectures, hardware monitoring for safety-critical applications, and power management in high-performance computing (HPC) systems. His recent projects involve developing controllers for 2.5D systems-in-package and creating open-source networking solutions for mixed-criticality environments. Ottaviano’s work often emphasizes open-source hardware design and scalable system-level approaches to address challenges in autonomous systems and edge computing. He collaborates on advancements in interrupt handling for virtualized systems, peripheral event linking for IoT devices, and FPGA-based thermal emulation for many-core processors. His research bridges theoretical computer architecture principles with practical implementations in embedded and real-time systems.
Timothy Rogers is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University, located in West Lafayette. His research focuses on GPU architecture, parallel processing, and simulation frameworks, with particular emphasis on optimizing hardware acceleration, memory systems, and concurrency management. He holds an office at BHEE 326A and can be reached at timrogers@purdue.edu. His work spans GPU performance modeling, SIMT architecture analysis, and energy-efficient computing. Recent contributions include frameworks like ThreadFuser for MIMD program analysis, CRISP for concurrent rendering, and Simr for data center microservices. He has also contributed to hardware ray tracing units and RISC-V core integration studies. Rogers has been active in conference leadership, serving as General Chair for ISPASS 2024 and securing NSF travel grants for student participation. His research bridges theoretical architecture design with practical implementation, addressing challenges in modern massively parallel systems.
Luca Carloni is a Professor of Computer Science and Department Chair at Columbia University's Columbia Engineering. He leads the System-Level Design Group, focusing on heterogeneous system-on-chip (SoC) architectures, networks-on-chip (NoC), and embedded systems. Carloni holds a Laurea Summa Cum Laude in Electronics Engineering from the University of Bologna and a PhD in Electrical Engineering and Computer Sciences from UC Berkeley. His work emphasizes specialized hardware design, energy-efficient computing, and FPGA-based prototyping. Research interests include system-level design methodologies for SoCs, embedded accelerators, and quantum computing hardware. He has pioneered frameworks like Embedded Scalable Platforms (ESP) and tools like MosaicSim for rapid SoC prototyping. Carloni has received numerous awards, including the NSF CAREER Award (2006), IEEE Fellow (2017), and multiple best paper awards at DATE and CloudCom conferences. He has served on editorial boards of IEEE Transactions on CAD and ACM Transactions on Embedded Computing , and chaired key conferences like EMSOFT and ESWeek. His research addresses challenges in heterogeneous architectures, power management, and the intersection of machine learning with embedded systems. Current projects explore quantum control systems, brain-computer interfaces, and energy-efficient datacenter computing.
Alaa Alameldeen is an Associate Professor in the School of Computing Science at Simon Fraser University (SFU), part of the Faculty of Applied Sciences. Previously, he worked as a Research Scientist at Intel Labs (2006–2020) and held an Adjunct Faculty position at Portland State University (2008–2018). He earned a PhD in Computer Sciences from the University of Wisconsin-Madison (2006), and earlier degrees from Alexandria University, Egypt. His research focuses on computer architecture, including memory systems (processing-in-memory, cache/memory compression, security), energy-efficient architectures, and hardware-software co-design for machine learning. He advises PhD and MSc students in these areas and teaches advanced computing science courses. Key contributions include innovations in memory hierarchies, cache compression techniques, and mitigating hardware vulnerabilities. His work has been published in top conferences (e.g., ISCA, MICRO, HPCA) and patented in areas like near-memory processing and error correction. Alameldeen currently leads a research group exploring secure and high-performance memory architectures. He has supervised multiple graduate students, with many progressing to roles at leading tech companies and academic institutions.
David Wentzlaff is a Professor of Electrical and Computer Engineering at Princeton University, with associated faculty roles in Computer Science and the High Meadows Environmental Institute (HMEI). He leads research in computing architecture, green computing, and sustainable system design. As Director of Undergraduate Studies, he shapes educational programs in his field. Education: Ph.D., Electrical Engineering, MIT (2012) M.S., Electrical Engineering and Computer Science, MIT (2002) B.S., Electrical Engineering, University of Illinois at Urbana-Champaign (2000) Research Focus: Future Computing Systems: Designing manycore architectures, cloud computing infrastructure, and chiplet-based systems for exascale computing. Sustainability: Developing energy-efficient hardware, recyclable computing systems, and eco-friendly decommissioning strategies. Hardware-Software Co-Design: Exploring FPGA integration, in-memory computing, and parallel processing frameworks. Advising & Grants: Advises 8 current graduate students, focusing on topics like chiplet design, neural acceleration, and sustainable computing. Recipient of NSF grants for projects like OpenPiton (open-source manycore research platform) and CAREER awards for energy-efficient architectures. Labs & Collaborations: Leads the Wentzlaff Research Group at Princeton. Develops open-source frameworks like PRGA (FPGA prototyping) and OpenPiton (manycore processor).
