Prof. Srdjan Capkun is a Full Professor in the Department of Computer Science at ETH Zurich and Director of the Zurich Information Security and Privacy Center (ZISC). He holds a Dipl.Ing. from the University of Split (1998) and a Ph.D. from EPFL (2004). His research focuses on system and network security, including wireless security (e.g., secure positioning), trusted computing, blockchain technologies, and privacy-preserving systems. He co-founded 3db Access (acquired by Infineon) and Sound-Proof, addressing secure distance measurement and authentication. Notable achievements include an ERC Consolidator Grant (2016), ACM Fellowship, and IEEE Fellowship. Education: Dipl.Ing., Electrical Engineering / Computer Science, University of Split, 1998 Ph.D., Communication Systems, EPFL, 2004 Research Interests: Wireless security (e.g., UWB, GNSS, cellular) Trusted execution environments (TEEs) Blockchain and cryptocurrency systems Privacy-preserving technologies Awards & Grants: ERC Consolidator Grant (2016) ACM Fellow and IEEE Fellow Leadership of ZISC Advising & Labs: Leads the System Security Group at ETH Zurich Guided postdoctoral researchers and graduate students in security and privacy Companies: 3db Access (secure distance measurement) Futurae (online authentication)
Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology and serves as the Director of the 3D Systems Packaging Research Center. His research focuses on heterogeneous integration of microsystems, including 2.5D and 3D ICs and packaging technologies, with significant contributions to advanced cooling systems, electrical and photonic interconnects, and biosensor integration with CMOS. Dr. Bakir's research interests span heterogeneous microsystem design and integration, advanced cooling and power delivery for emerging architectures, electrical and photonic interconnect technologies, biosensor technologies, and nanofabrication. His work addresses critical challenges in next-generation electronics, enabling polylithic integration that concatenates heterogeneous ICs of various functionalities while mimicking monolithic-like densities. His research particularly focuses on co-design of thermal technologies, power delivery networks, and signaling networks for silicon nanoelectronic systems. His recent publications demonstrate strong trends in fused-silica stitch-chip technology for heterogeneous integration, with particular emphasis on RF and mm-wave applications, power delivery for AI accelerators, and thermal management solutions. His work bridges electrical engineering, materials science, and thermal management to solve critical bottlenecks in computing performance and efficiency. 2013 Intel Early Career Faculty Honor Award 2012 DARPA Young Faculty Award 2011 IEEE CPMT Society Outstanding Young Engineer Award 2012 National Academy of Engineering Frontiers of Engineering Symposium Invited Participant 2015 IEEE CPMT Society Distinguished Lecturer 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology More than 25 conference and student paper awards Twelve issued US Patents Dr. Bakir leads the Integrated 3D Systems Lab (I3DS) at Georgia Tech, which is actively researching advanced packaging, interconnects, electrical and thermal design, and system integration. His team has received significant recognition for their work, including multiple best paper awards from major conferences like ECTC, IITC, and CICC. The lab is currently seeking postdoctoral researchers and research faculty to advance next-generation electronics through collaborative research. His lab focuses on enabling the next phase of Moore's Law through polylithic integration, which concatenates heterogeneous ICs of various functionalities (digital, analog, photonic, and mm-wave) using advanced off-chip '2.5D' and '3D' heterogeneous interconnects and packaging. This work impacts applications in high-performance computing, machine learning, edge intelligence, autonomous vehicles, augmented/virtual reality, and healthcare.
Prof. Hayden Kwok Hay SO is an Associate Professor at the University of Hong Kong (HKU), affiliated with the Department of Electrical and Electronic Engineering. He currently serves as Acting Director of the School of Innovation and previously co-directed the Computer Engineering Program. His research focuses on reconfigurable computing systems, FPGA-based architectures, and their applications in AIoT, medical imaging, and high-performance computing. He holds a B.S., M.S., and Ph.D. in Electrical Engineering and Computer Sciences from UC Berkeley (1998–2007). Prof. So has been recognized with awards such as the IEEE-HKN Teaching Award (2021), Croucher Innovation Award (2013), and multiple teaching excellence awards. He leads the Computer Architecture & System Research Lab (CASR) and co-founded the Joint Lab on Future Cities (JLFC). His work spans FPGA overlay architectures, graph processing systems, and hardware-software co-design for efficient computing. Key research contributions include advancements in FPGA-based reconfigurable systems, sparse dataflow architectures, and medical imaging accelerators. He has secured grants for projects like 'Advanced machine vision guided aquatic surface vehicles' and 'Efficient and Productive Parallel Data Processing in Hybrid FPGA-CPU Clusters.' Prof. So has advised numerous students and researchers, contributing to over 150 peer-reviewed publications. His current projects explore AI hardware acceleration, neuromorphic computing, and FPGA-driven solutions for big data challenges.
Dr. Zhenman Fang is an Associate Professor at the School of Engineering Science , Simon Fraser University (SFU) , where he founded and directs the HiAccel Lab . He also holds an associate membership in the School of Computing Science at SFU. His research focuses on customizable computing with software-defined hardware acceleration , addressing performance, energy-efficiency, and reliability in post-Moore’s law computing across domains like machine learning , big data analytics , quantum chemistry , and precision medicine . Education: Ph.D. in Computer Science from Fudan University (2014), with a visit to University of Minnesota during his studies. Postdoctoral Work: University of California, Los Angeles (UCLA) (2014-2017). Industry Experience: Staff Software Engineer at Xilinx (2017-2019). Dr. Fang’s research spans the entire computing stack , including application characterization , accelerator-rich architecture design , and programming/tool support . He has developed frameworks like HiSpMV , SyncNN , and SQL2FPGA , emphasizing FPGA acceleration for vision transformers , quantum chemistry , and spiking neural networks . His work has been recognized with 3 best paper awards (FPL 2024, TCAD 2019, MEMSYS 2017) and 3 best paper nominees (FCCM 2025, HPCA 2017, ISPASS 2018). Recent publications highlight trends in low-precision machine learning ( ShiftQuant , ESRU ), quantum chemistry acceleration ( SERI ), and vision transformer optimization ( Quasar-ViT ). His HiAccel Lab actively mentors PhD and MASc students , with notable graduates like Alec Lu (PhD 2024, now at Meta) and Philip Stachura (MASc, now with BC Graduate Scholarship). Scientific Awards: Inaugural SFU Research Excellence Award - Horizon Award (2025) FPL 2024 Stamatis Vassiliadis Best Paper NSERC Alliance Award (2020) CFI JELF Award (2019) Xilinx University Program Award (2019) IEEE Senior Member (2023) Grants: NSERC Discovery Grant (2019) CFI JELF Funding (2019) Huawei and Xilinx sponsorships Dr. Fang leads open-source initiatives like SyncNN , PASTA , and SQL2FPGA , and serves as General Chair for ASAP 2025 and Program Co-Chair for RAW 2025 . His lab collaborates globally with institutions such as UCLA , Northeastern University , and Xidian University .
Christina L. Garman is an Assistant Professor in the Department of Computer Science at Purdue University, where she joined in Spring 2018. Her research focuses on practical cryptography and cryptographic automation to make secure system development accessible to non-experts through error-resistant design methodologies. Her educational background includes: Bachelor of Science in Computer Science and Engineering from Bucknell University (2011) Bachelor of Arts in Mathematics from Bucknell University (2011) Master of Science in Engineering in Computer Science from Johns Hopkins University (2013) Doctor of Philosophy in Computer Science from Johns Hopkins University (2017) Professor Garman's work centers on real-world cryptographic system security, spanning protocol analysis (e.g., RC4 in TLS, Apple iMessage flaws), decentralized anonymous systems (Zerocash/ZCash), and cryptographic automation. She pioneered techniques for removing human error in cryptographic deployments through automated tools and frameworks. Her research bridges theoretical cryptography with practical implementation challenges in privacy-preserving technologies and secure infrastructure. Analysis of her 2021-2025 publications reveals expanding research horizons: hardware security vulnerabilities (Rowhammer, SGX), privacy network enhancements (Tor onion services), software supply chain security (SBOM tools), and advanced cryptographic protocols (zkSNARKs, MPC). This evolution demonstrates consistent focus on real-world security impact while diversifying into hardware-software cross-layer threats and formal verification methods for cryptographic implementations. Her major scientific recognitions include: NSF CAREER Award (2021) for cryptographic automation research ACM CCS Best Paper Award (2016) for iMessage security analysis IEEE Test of Time Award (2024) for foundational Zerocash work Professor Garman co-founded ZCash, a privacy-focused cryptocurrency based on her Zerocash protocol, and her NSF CAREER grant supports cryptographic automation development. Her research has received significant media coverage in The Washington Post, Wired, and The New York Times, highlighting real-world relevance. While specific student advising details aren't public, her active publication record indicates ongoing mentorship of graduate researchers in security and cryptography. Her work maintains strong industry connections through ZCash development and Tor network contributions, with recent projects like keyless CDNs demonstrating practical applications of cryptographic automation. She remains a leading voice in cryptographic research communities through conference participation and collaborative projects addressing evolving security challenges.
Vijay Kumar is the Nemirovsky Family Dean of Penn Engineering at the University of Pennsylvania, with faculty appointments in the Departments of Mechanical Engineering, Computer and Information Science, and Electrical and Systems Engineering. He is a leading figure in robotics and computer architecture research. Research Interests include robotics, particularly multi-robot systems and micro aerial vehicles (MAVs), as well as computer architecture innovations for machine learning, GPU acceleration, and datacenter efficiency. His work spans theoretical foundations and practical applications in autonomous systems and hardware optimization. Scientific Awards include: 1991 NSF Presidential Young Investigator Award 1996 Lindback Award for Distinguished Teaching 2012 ASME Mechanisms and Robotics Award 2014 Engelberger Robotics Award 2017 IEEE George Saridis Leadership Award Multiple best paper awards at DARS, ICRA, and RSS conferences Editorial Leadership includes serving as Editor of the ASME Journal of Mechanisms and Robotics and Advisory Board Member of AAAS Science Robotics Journal . His GRASP Lab team developed foundational frameworks for micro UAV testbeds and swarm robotics.
Justine Sherry is the A. Nico Habermann Associate Professor of Computer Science at Carnegie Mellon University, affiliated with the College of Engineering. She holds a PhD (2016) and MS (2012) from UC Berkeley and a BS/BA (2010) from the University of Washington. Her research focuses on networked systems, including middleboxes, cloud computing, congestion control, and hardware acceleration (e.g., SmartNICs/FPGAs). Notable projects include Pigasus (open-source 100Gbps IDS), APLOMB (cloud-based middlebox scaling), and BlindBox (encrypted traffic scanning). Her academic roles include serving on the SIGCOMM CARES Committee, DARPA ISAT Study Group, and ACM CoNEXT Steering Committee. Awards include the Alfred P. Sloan Fellowship, VMware Systems Award, and IETF Applied Networking Prize. She advises over 15 students and collaborates with industry partners like Intel and VMware. Research highlights include radical shifts in datacenter architectures (SmartNIC compute control), fairness in congestion algorithms (BBR analysis), and database-proxy innovations (Tigger with eBPF). Her teaching emphasizes systems as science labs, integrating experimental design and hypothesis testing into projects. Education: PhD UC Berkeley (2016), MS UC Berkeley (2012), BS/BA University of Washington (2010) Labs/Teams: CyLab, SNAP Research Group, CMU Portugal Collaboration Grants: NSF, Intel, Google Faculty Awards
Swiss Federal Institute of Technology in LausanneSwitzerland
Mirjana Stojilovic is a Researcher at École Polytechnique Fédérale de Lausanne (EPFL) in the School of Computer and Communication Sciences (IC), specifically within the Institute of Computer Engineering (IINFCOM) and the Parallel Systems Architecture Laboratory (PARSA). She also serves as a Lecturer in the SSC - Teaching department at EPFL. Her office is located at INJ 235, Station 14, 1015 Lausanne, Switzerland. Mirjana Stojilović received her Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. Her academic journey includes collaborating with the Processor Architecture Laboratory at EPFL as a Guest Researcher from 2010 to 2013, working at the University of Applied Sciences Western Switzerland as a senior researcher from 2013 to 2016, and joining the Parallel Systems Architecture Lab at EPFL in October 2016. Dr. Stojilovic's research spans field-programmable technology, electronic design automation (EDA), and electrical-level attacks and countermeasures for reconfigurable hardware. Her work bridges the gap between hardware design and security, with a particular focus on vulnerability analysis and protection mechanisms for FPGA-based systems in cloud environments. She has made significant contributions to understanding side-channel attacks, fault injection techniques, and secure multi-tenancy solutions for shared hardware resources. Her extensive publication record reveals a clear research trajectory from traditional FPGA design and EDA topics toward increasingly security-focused investigations. Recent work demonstrates deep expertise in power analysis attacks, hardware trojans, and countermeasures for cloud-based FPGA systems, reflecting the growing importance of hardware security in distributed computing environments. Scientific Awards and Recognitions: Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016) Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016) Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012) EPFL School of Computer and Communication Sciences (IC) Teaching Award (2015) Nominated for Best Paper Award at the International Conference on Field-Programmable Technology (FPT) (2020) Dr. Stojilovic has advised numerous PhD students including Coulon Louis, Pirayadi Rouzbeh, and Shrivastava Shashwat, along with past EPFL PhD students Glamocanin Ognjen and Mahmoud Dina. She has supervised dozens of semester and diploma projects focusing on hardware security, FPGAs, design automation, side-channel attacks, and cloud computing. Her service to the academic community includes serving on program committees for FPGA, FCCM, FPL, and DATE conferences, reviewing for multiple IEEE and ACM journals, and acting as associate editor for IEEE ESL and ACM TRETS. As a member of the Parallel Systems Architecture Laboratory at EPFL, Dr. Stojilovic leads research projects investigating security aspects of reconfigurable hardware systems. Her team works at the intersection of computer architecture, electronic design automation, and hardware security, with particular emphasis on vulnerabilities and protections for shared FPGA resources in cloud environments.
Minjie Chen is an Associate Professor of Electrical and Computer Engineering and the Andlinger Center for Energy and the Environment at Princeton University, serving as Acting Associate Director for Research at the Andlinger Center. He leads the Princeton Power Electronics Lab (PowerLab), which focuses on developing fundamental and novel power electronics solutions for a wide range of applications from mW-scale energy harvesting to MW systems in renewable energy integration. Dr. Chen received his Ph.D. in Electrical Engineering and Computer Science from MIT in 2015 and his B.S. in Electrical Engineering from Tsinghua University in 2009. Before joining Princeton as an Assistant Professor in February 2017, he was a postdoctoral associate at MIT Research Laboratory of Electronics. His research spans power electronics, magnetics design, and machine learning applications in energy systems. The PowerLab develops advanced power conversion architectures that enable order-of-magnitude higher power density through high-frequency designs, addressing circuit timing, parasitics, magnetics, and thermal management challenges. Their work targets applications ranging from portable devices to data centers and renewable energy systems. The research group has produced a remarkable series of high-impact publications, with seven IEEE Transactions on Power Electronics Prize Papers in seven consecutive years (2016-2023). Their recent work increasingly integrates machine learning techniques with power electronics, exemplified by the MagNet project which redefines how power magnetics are studied and modeled. NSF CAREER Award, 2019 IEEE PELS Richard M. Bass Outstanding Young Power Electronics Engineer Award, 2023 Power of Associations Silver Award from ASAE for MagNet project, 2024 Multiple IEEE Transactions on Power Electronics Prize Papers (2016-2023) Princeton Engineering Commendation List for Outstanding Teaching (2019, 2020) Dr. Chen advises approximately 15 graduate students who have received numerous awards including the IEEE PELS John G. Kassakian Fellowship, Princeton SEAS Honorific Fellowship, and multiple IEEE conference best paper awards. His research is supported by significant grants from NSF, DOE ARPA-E, Princeton Innovation Fund, C3.ai DTI, and industry partners including Intel, Google, and pSemi. The lab's MagNet project has become a major international initiative with a $60,000 prize pool challenge. The PowerLab maintains strong industry connections and has launched several collaborative projects with Intel, Google, and pSemi. Their MagNet project has evolved into an international challenge with participation from over 40 teams worldwide, demonstrating the growing impact of their approach to machine learning for power magnetics modeling.
Callie Hao is an Assistant Professor in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology since 2021, holding the ON Semiconductor Junior Professorship. Her research bridges hardware efficiency and algorithmic innovation with significant industry and federal recognition. Education: Ph.D. in Electrical Engineering, Waseda University (2017) M.S. and B.S. in Computer Science and Engineering, Shanghai Jiao Tong University Research Focus: Dr. Hao pioneers software/hardware co-design for edge AI, specializing in hardware-efficient machine learning algorithms, FPGA-based reconfigurable computing, graph neural networks, and electronic design automation (EDA). Her work emphasizes neural architecture search, high-level synthesis optimization, and memory-efficient systems for embedded and IoT applications, driven by the philosophy that "1 + 1 > 2" for transformative efficiency gains. Publication Impact: Her 15 most recent publications (2023-2026) reveal a strategic shift toward machine learning-driven EDA tools, with 60% focused on high-level synthesis frameworks and 40% on graph neural network acceleration. Key trends include simulation speed breakthroughs (LightningSim), automated accelerator generation (GNNBuilder), and cryptographic hardware innovations (Cryptonite), predominantly published in top-tier venues like MICRO, ICCAD, and DAC. Awards & Recognition: NSF CAREER Award (2024) and Intel Rising Star Faculty Award (2023) Best Paper Awards at MLCAD 2024 and GLSVLSI 2021 ON Semiconductor Junior Professorship (2025) and Sutterfield Family Early Career Professorship (2022) DAC-SDC competition championships (2018-2020) Mentorship & Funding: Dr. Hao advises 8+ Ph.D. students in the Sharc Lab, with Rishov Sarkar winning the Oscar P. Cleaver Award and Qualcomm Innovation Fellowship. Her research is funded by DARPA (2021) for ultra-light video intelligence systems and supported by industry awards from Amazon and Sony. She actively serves on program committees for DAC, ICCAD, and DATE conferences. Lab Leadership: As director of the Sharc Lab (Software/Hardware Co-design lab), she cultivates interdisciplinary research at the intersection of FPGA design, machine learning, and EDA, requiring expertise in Verilog/HLS, GNNs, and compiler technologies while maintaining strict focus on real-world hardware implementation.
Michela Becchi is an Associate Professor in the Department of Electrical and Computer Engineering at North Carolina State University. She specializes in computer architecture, systems software, and applications, with a focus on heterogeneous systems, parallel algorithms, and acceleration techniques for bioinformatics, pattern recognition, and quantum computing. Her work spans multi-core CPUs, GPUs, FPGAs, and distributed clusters, emphasizing the boundary between hardware and software design. Dr. Becchi holds a Ph.D. and Master’s degree in Computer Engineering from Washington University in St. Louis (2009) and a Bachelor’s degree in Computer Engineering from Politecnico di Milano, Italy (2000). Her research has been recognized with prestigious awards, including the NSF CAREER Award (2015) and the University of Missouri System President Award for Early Career Excellence (2016). Her research interests include compiler and runtime techniques for heterogeneous systems, acceleration of bioinformatics algorithms, and high-speed networking applications. She has pioneered frameworks for efficient data transformation, GPU-accelerated compression, and memory-efficient graph algorithms for quantum computing. Her work also explores thread coarsening, mixed-precision auto-tuning, and secure multi-core processor design. Key contributions include the PILOT runtime system for GPU memory management, the GPU-FPtuner auto-tuner for floating-point applications, and innovative approaches to automata processors for genomic analysis. Her publications emphasize reproducible accuracy in scientific simulations and the optimization of irregular applications on many-core platforms.
Caroline Trippel is an Assistant Professor in the Departments of Computer Science and Electrical Engineering at Stanford University. Her research focuses on ensuring correctness and security in computer systems through formal methods, with particular emphasis on hardware verification, memory consistency models, and mitigating vulnerabilities like Spectre/Meltdown. She previously worked at Facebook’s FAIR SysML group before joining Stanford. Education: PhD in Computer Science, Princeton University BS in Computer Engineering, Purdue University Her work has influenced the RISC-V ISA memory consistency model and produced tools like CheckMate, which automatically synthesizes hardware exploits for security verification. She explores privacy-preserving ML, ML-driven hardware optimizations (e.g., neural recommendation), and datacenter reliability. Her research has earned awards including the 2020 ACM SIGARCH Dissertation Award and NVIDIA Fellowship. Key contributions include: Formal analysis of RISC-V memory models Exploitation synthesis frameworks (CheckMate) Hardware-software contracts for security Defenses against microarchitectural side-channel attacks Current projects include: VeriCoder: LLM-enhanced RTL code verification Multi-μPATH synthesis for security validation Near-data processing (RecSSD) for recommendation systems
Timothy Rogers is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University, located in West Lafayette. His research focuses on GPU architecture, parallel processing, and simulation frameworks, with particular emphasis on optimizing hardware acceleration, memory systems, and concurrency management. He holds an office at BHEE 326A and can be reached at timrogers@purdue.edu. His work spans GPU performance modeling, SIMT architecture analysis, and energy-efficient computing. Recent contributions include frameworks like ThreadFuser for MIMD program analysis, CRISP for concurrent rendering, and Simr for data center microservices. He has also contributed to hardware ray tracing units and RISC-V core integration studies. Rogers has been active in conference leadership, serving as General Chair for ISPASS 2024 and securing NSF travel grants for student participation. His research bridges theoretical architecture design with practical implementation, addressing challenges in modern massively parallel systems.
Abdullah Muzahid is an Associate Professor in the Department of Computer Science and Engineering at Texas A&M University (since August 2024), previously serving as an Assistant Professor there since August 2018. Prior, he held an Assistant Professor role at the University of Texas at San Antonio (2012-2018). He earned his Ph.D. from the University of Illinois at Urbana-Champaign (2012), focusing on architectural support for debugging concurrency bugs under Prof. Josep Torrellas. Education: Ph.D., Computer Science, University of Illinois at Urbana-Champaign (2012) M.S., Computer Science, University of Illinois at Urbana-Champaign (2009) B.S., Computer Science and Engineering, Bangladesh University of Engineering and Technology (2005) Research Interests: His work spans Computer Architecture , Systems , and Artificial Intelligence , with focus on multiprocessor architecture, parallel programming, debugging, and applying machine learning to system optimization. Recent projects include cache indexing via entropy estimation, DNN training acceleration, and hardware-software co-design for security. Awards: NSF CAREER Award (2017) Excellence in Research Award (UTSA, 2015 & 2017) W. J. Poppelbaum Award (UIUC, 2012) Intel Ph.D. Fellowship (2011) Grants & Advising: He leads NSF-funded projects on robust deep learning and stream processing systems. Advised 5 PhD graduates and currently mentors 4 PhD students. Served on program committees for ISCA, HPCA, MICRO, and as NSF panelist. Labs/Teams: Active in Texas A&M’s Computer Architecture group, collaborating on machine programming, hardware security, and AI-driven systems optimization.
Xiaoming Li is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Delaware , focusing on compiler optimization, GPU computing, and hardware-software interaction. His work bridges machine learning with code generation to enhance program efficiency. B.S. and M.E. from Nanjing University (1998, 2001) Ph.D. in Computer Science from University of Illinois at Urbana-Champaign (2006) Research interests include: Compiler optimizations for static and dynamic code transformation Machine learning-driven code generation techniques FFT algorithms for sparse and hybrid systems Non-traditional compilers for SAT solvers and virtual machines GPU acceleration for large-scale computational problems His publications span 15 years , emphasizing: FFT optimization across GPU/CPU architectures Compiler techniques for heterogeneous systems Adaptive scheduling and error resilience Integration of empirical and model-driven approaches Notable awards: NSF CAREER Award (2008) Best Paper Award at ADAPT Workshop (2013) Advising highlights: Current students: Ryan Taylor, Sha Li, Shuo Chen, Yuanfang Chen, Chao Yang, Chaoyu Chen Graduates: Liang Gu (FFT Libraries), Jakob Siegel (GPGPU Frameworks), Murat Bolat (Context-Aware Compilation)
