Dr. Ece Yaprak is a Professor and Chair of the Engineering Technology Division in the College of Engineering at Wayne State University. She earned her BS in Electrical Engineering from the University of Michigan–Dearborn (1980) and MS/PhD in Computer Engineering from Wayne State University (1984/1989). With industry experience at General Electric and Ford Motor Company, her research spans computer networks , wireless communications , and wireless sensor networks , funded by NSF , DOE , NASA , and the U.S. Navy. Research Fellowships : NASA (Glenn, JPL, Ames, Johnson Space Center), Fulbright-Nokia (Finland), U.S. Navy SPAWAR. Leadership Roles : ABET Board of Directors (2023–2026), NSF Program Director (2015–2017). Awards : IEEE Fellow (2025), multiple Excellence in Teaching Awards (2005–2014). Her recent publications focus on wireless network security , telemedicine systems , and engineering education innovations. She co-developed multi-institutional projects with Old Dominion University and NASA, and continues teaching Senior Design Project courses.
Manuel Blum is a renowned computer scientist and winner of the 1995 ACM Turing Award. He holds the title of Bruce Nelson University Professor of Computer Science at Carnegie Mellon University's School of Computer Science. Previously, he was a faculty member at the University of California, Berkeley. His work spans theoretical computer science, computational complexity theory, cryptography, and program checking. He has supervised 35 doctoral students, many of whom are leading figures in computer science. Education: Ph.D. in Mathematics (MIT, 1964), M.S. in Electrical Engineering (MIT, 1961), B.S. in Electrical Engineering (MIT, 1959). Research focuses on foundational aspects of computing, including cryptographic protocols (e.g., CAPTCHA), program correctness mechanisms, and computational complexity. His contributions to secure human-computer interaction and zero-knowledge proofs are particularly influential. Teaching highlights include courses on theoretical cryptography and complexity theory. Awards include the ACM Turing Award, ACM Fellow, and UC Berkeley's Distinguished Teaching Award.
Anthony Goodacre is a Professor of Computer Architectures at the School of Computer Science, holding a part-time role while serving as Director of Technology and Systems at ARM Ltd. in Cambridge. He leads research spanning nanotechnology, hardware design, operating systems, and heterogeneous runtimes, with a focus on scalable, power-efficient systems for embedded, enterprise, and HPC applications. Research interests include: Exascale computing through EU-funded projects like EUROSERVER and ExaNoDe 3D silicon integration and system virtualization for heterogeneous architectures Quantum-classical programming languages (e.g., Quff) Power management techniques like cyclic power-gating Memory models and runtime systems for ARM-based data centers His 15 most recent publications highlight trends in FPGA acceleration, radiation-hardened MPSoC systems, and hybrid quantum-classical programming. Contributions to EU FP7/H2020 projects (e.g., EUROSERVER, ExaNEST) emphasize commercialization of ARM technology for exascale computation. Current collaborations include: KALEAO Limited (CSO/CTO since 2015) ARM Ltd. (Director since 2002) Technology Strategy Board (member since 2015) Academic partnerships in EU H2020 projects He co-supervises two PhD students and contributes to policy discussions, including parliamentary select committee evidence. His work aligns with UN SDGs for energy efficiency and sustainable computing.
Kranitis Nektarios is a Lecturer at the Department of Informatics and Telecommunications, National and Kapodistrian University of Athens. His research focuses on FPGA-based hardware architectures, space-grade computing, and image compression standards like CCSDS, with applications in satellite systems and reliable data processing. Primary affiliation: National and Kapodistrian University of Athens Department: Informatics and Telecommunications Research interests center on space-grade SRAM FPGAs , LDPC encoding , hyperspectral image compression , and software-based self-test methodologies for embedded systems. His work addresses high-speed data processing and fault tolerance in satellite communications. Key trends in his publications include CCSDS standard implementations , hardware accelerators for image compression, resilience to SEUs , and energy-efficient testing techniques for microprocessors. Topics span space systems , parallel computing , and digital circuit design .
Dr. Irina Zeleneva is an Associate Professor at the Department of Computer Systems and Networks, Faculty of Computer Science and Technologies, Zaporizhzhia Polytechnic National University. With a Ph.D. in Computers, Systems, and Networks, she has 15+ years of academic experience since joining the university in 2003. Specializes in FPGA-based digital system design Focuses on hardware acceleration and reliability optimization Teaches advanced topics in microprocessor architecture Her research includes: Development of energy-efficient FPGA systems Hardware-software co-design Neural network text classification accelerators Reliable embedded control architectures Recent publications analyze FPGA implementation of floating-point multipliers, finite state machines with elementary state chains, and AI-enhanced educational frameworks . Her work frequently appears in international conferences like IDAACS and PIC S&T, with multiple Scopus/WoS indexed articles. Dr. Zeleneva's contributions: Co-author of two monographs on FPGA acceleration PI in multiple university research projects Active participant in annual "Week of Science" conferences
Sofiène Tahar is a Professor and Tier I Concordia Research Chair in the Department of Electrical and Computer Engineering at Concordia University. His academic career focuses on formal methods for hardware and system verification. Education: Ph.D. from the University of Karlsruhe (1994) Research Interests: Formal methods and theorem proving Hardware verification (digital, analog, and mixed-signal systems) Cyber-physical systems analysis Reliability, probabilistic, and statistical modeling Scientific Recognition: Tier I Concordia Research Chair Teaching Activities: COEN311: Computer Organization and Software COEN6741: Computer Architecture and Design COEN6551: Formal Hardware Verification Thesis Supervision: Currently supervising PhD students in Electrical and Computer Engineering.
George Papadimitriou is an Assistant Professor in the Computer Engineering & Informatics Department at the University of Patras , Greece, hosted within the School of Engineering . His primary affiliation lies with the Computer Hardware and Architecture division, where he leads research and teaching activities focused on dependable, energy-efficient computer architectures. Education: PhD in Computer Science, Department of Informatics & Telecommunications, National and Kapodistrian University of Athens (2019) Post-doctoral researcher, Computer Architecture Lab, National and Kapodistrian University of Athens Research Interests: Dr Papadimitriou’s research lies at the intersection of computer architecture , energy efficiency , and microprocessor reliability . His work specifically targets: Robust and energy-efficient CPU/GPU/accelerator architectures Post-silicon validation techniques for catching elusive hardware bugs Silent data corruption detection and mitigation across the compute stack Characterization of voltage margins and power consumption in modern microprocessors Modeling and simulation of domain-specific accelerators for low-power, dependable operation More recently, his team has been extending these methodologies to RISC-V and neuromorphic photonic accelerators within large European consortia. Scientific Awards & Recognition: Eight HiPEAC Paper Awards for top-tier conference publications (MICRO, HPCA, ISCA) between 2017–2024 IEEE Transactions on Computers 2022 Best Paper Award for the article “Anatomy of On-Chip Memory Hardware Fault Effects Across the Layers” TTTC/ITC Gerald W. Gordon Student Award 2023 Research Funding & Projects: Dr Papadimitriou is principal investigator or key technical contributor in multiple Horizon Europe and industry-backed projects that collectively exceed €50 M in funding. Current leadership roles include: DARE (Digital Autonomy for RISC-V in Europe) NEUROPULS (Neuromorphic Energy-Efficient Secure Accelerators) REBECCA (Reconfigurable Heterogeneous Highly Parallel Processing Platform) Vitamin-V (Virtual Environment & Tool-boxing for Trustworthy RISC-V Cloud Services) Intel, IBM, and Thales bilateral research contracts on energy-efficient and resilient microarchitectures Laboratory & Team: He leads the Energy-Efficient and Dependable Architectures (EEDA) research group at University of Patras, operating laboratory facilities for silicon measurement, FPGA emulation, and full-system simulation (gem5, MARSS, custom tools). The team currently comprises 3 PhD candidates, 2 post-docs, and several MSc thesis students collaborating with European and US partners.
Dimitrios Soudris is a Professor at the School of Electrical and Computer Engineering, National Technical University of Athens (NTUA), leading the Microprocessor and Digital Systems Lab (MicroLab). Previously, he served as Lecturer, Assistant, and Associate Professor at Democritus University of Thrace from 1995 to 2008. Diploma in Electrical Engineering (1987), University of Patras PhD in Electrical Engineering (1992), University of Patras His research focuses on Embedded Systems , Reconfigurable Architectures (FPGAs) , Hardware Accelerators for data centers/space/cloud, Edge Computing , and Low Power VLSI Design . Recent publications highlight trends in: AI/ML acceleration for edge and space applications Secure FPGA architectures for 6G networks Energy-efficient heterogeneous memory systems Approximate computing techniques Transformer optimization for low-power contexts Scientific Awards: INTEL and IBM awards (project LPGD #25256) HiPEAC, DAC, and ISCA awards (2010–2024) XILINX Open Hardware Design Contest (2017, 2019, 2021) He has coordinated >70 R&D projects funded by the European Commission, ENIAC-JU, ESA, and industry partners. As Associate Editor of ACM TODAES and conference chair (PATMOS, VLSI-SOC), he contributes to academic leadership. His lab, MicroLab, specializes in hardware-software co-design for emerging computing paradigms.
Professor Luca Fanucci is a Full Professor of Electronics at the Department of Information Engineering , University of Pisa. He serves as Rector's Delegate for Inclusion of Students with Disabilities and leads research in integrated circuits, embedded systems, and assistive technologies . Institutional roles include membership in the National University Conference of Delegates for Disability (CNUDD) and leadership in the PhD program in Information Engineering. Born: Montecatini Terme (1965) Education: Laurea in Electronic Engineering (1992), PhD in Information Engineering (1996), University of Pisa Professional Journey: ESA research (1992-1996), CNR researcher (1996-2004), University of Pisa faculty (2004-present) His research focuses on: System-level design of integrated circuits and embedded systems Hardware-software co-design for low power consumption Spacecraft and satellite communication systems Medical devices and telemonitoring platforms Assistive technologies for disabilities Recent publications highlight AI in space applications and telemedicine systems . Key projects include the Ingeniars spin-off for satellite communications and the AsTech National Laboratory for assistive technologies. Scientific Recognition : IEEE Fellow (2019) 40+ patents H-index 34 (5000+ citations) He coordinates international conferences (DATE, HiPEAC, Spacewire) and serves as Associate Editor for Technology and Disability and Microprocessors and Microsystems journals.
Subhasish Mitra is a Professor in the Department of Electrical Engineering and by courtesy in Computer Science at Stanford University’s School of Engineering. His pioneering work focuses on creating robust, error-tolerant hardware systems through the Resilient Silicon paradigm, addressing critical challenges in modern microprocessors and memory design. Education Ph.D. in Electrical Engineering, Stanford University, 1999 B.Tech. in Electrical Engineering, Indian Institute of Technology Kharagpur, 1994 His research spans Computer Architecture , VLSI Design , and Hardware Security , with breakthroughs in defect-tolerant circuits and aging-induced error mitigation. Mitra’s work bridges theoretical innovation and industrial adoption, notably in Intel’s high-volume manufacturing processes. Key recognitions include: IEEE Fellow (2015) for “contributions to design and test of robust microprocessors” ACM Fellow (2015) for foundational reliability frameworks Phil Kaufman Award (2020), EDA’s highest honor He leads Stanford’s Robust Systems Group with sustained funding from NSF, DARPA, and semiconductor industry partners, driving next-generation secure hardware for AI accelerators and IoT devices.
Stefano Di Carlo is a Full Professor at the Department of Control and Computer Science (DAUIN) at Politecnico di Torino. He is the Coordinator of the Doctoral School in Artificial Intelligence and a member of the PolitoBIOMed Lab and the Doctoral School Council. His research spans Artificial Intelligence , Computer Architecture , Bioinformatics , and Cybersecurity , with a focus on 3D bioprinting , hardware security , and reliability analysis . Research Interests : Approximate computing systems Cybersecurity for connected vehicles Spiking neural networks and neuromorphic hardware Multicellular synthetic biological systems Hardware-based malware detection Biomedical simulation tools Article Trends : His recent publications address approximate computing (7/15), cybersecurity (6/15), and bioinformatics (4/15). Key subtopics include RISC-V security , gradient inversion attacks , photonic computing , and real-time fault injection . Scientific Awards : Best Paper Awards at IEEE AQTR (2010, 2012), IEEE DDECS (2013), and BIOINFORMATICS/BIOSTEC (2014) IEEE Computer Society Golden Core Award (2006), Meritorious Service Award (2010) IEEE Fellow (2011-) and Senior Member Advising & Grants : He supervises 14 PhD students and leads projects like Vitamin-V (RISC-V cloud services), APROPOS (approximate computing), and SERICS (cybersecurity). His lab, SMILIES, focuses on resilient computer architectures and bioinformatics . Labs & Teams : Lab 6 - Research Laboratory (DAUIN) SMILIES - Resilient computer architectures and life sciences PolitoBIOMed Lab - Biomedical engineering
Prof. Dr.-Ing. habil. Jan Richling serves as a Professor in the Department of Electrical Engineering and Information Technology at South Westphalia University of Applied Sciences in Hagen, Germany. Based in Room H.318 at Haldener Straße 182 (58095 Hagen), he maintains active academic engagement with consultation hours by appointment and can be contacted via phone (+49 2331 9330-6219) or email (richling.jan@fh-swf.de). His research expertise spans critical domains in computer engineering, with particular focus on: Microprocessor architecture and design Embedded system optimization Real-time operating environments Network protocol implementation Energy-efficient computing solutions Fail-safe system reliability These interconnected fields address modern challenges in efficient, robust computing infrastructure. Prof. Richling's teaching portfolio includes foundational and advanced courses such as Microcontroller Systems, Computer Organization, Operating Systems, IP Networks Programming, and Fail-safe Systems (a compulsory elective), directly reflecting his research specializations. No information regarding scientific awards, graduate student supervision, research grants, or laboratory facilities was provided in the source material.
