Lingjia Tang is an Assistant Professor in Computer Science with expertise in artificial intelligence, machine learning, big data, and no-code automation. Her research focuses on developing machine learning algorithms for medical data analysis and advancing no-code automation tools to democratize technology access. Research Interests Artificial Intelligence & Machine Learning Big Data Analytics & Graph-Based Retrieval No-Code Automation & User-Centric Systems Data Quality & Ethical AI Considerations Scientific Contributions With over 20 publications in prestigious journals, Dr. Tang's recent work explores: Graph-based retrieval frameworks (GraphRunner, TOBUGraph) LLM calibration and evaluation (SLMEval) Memory subsystem optimization in datacenters Meaning-typed programming paradigms Multi-agent conversational AI systems Awards 2023 Award for contribution to machine learning technologies Teaching Dr. Tang teaches courses in artificial intelligence, algorithms, and computational theory with a dynamic interactive approach. Current Projects Machine learning algorithms for medical diagnosis No-code automation tools for non-technical users
Prof. Dr.-Ing. Guillermo Payá Vayá leads the Chair for Chip Design for Embedded Computing at Technical University of Braunschweig's Faculty of Electrical Engineering, Information Technology, and Physics. His research focuses on processor architecture design, FPGA/ASIC implementations, and optimization techniques for embedded systems, particularly in high-performance, low-power, and radiation-hardened computing domains. Primary research interests include: Application-Specific Instruction Set Processors (ASIPs) and compiler co-design Radiation effects characterization and fault-tolerant hardware Ultra-low-power processor architectures for embedded AI Hardware acceleration of neural networks and computer vision algorithms Memory subsystem optimization and parallel computing techniques Recent publications demonstrate strong emphasis on radiation-hardened electronics (35% of recent works), AI accelerator design (27%), and ultra-low-power systems (20%), with growing interest in biomedical applications. Experimental validation through FPGA prototyping and semiconductor testing is a consistent methodology across research domains. Leads research team investigating: Radiation-tolerant FPGA architectures (Trumann, Weide-Zaage) Vector processor optimization (Gesper, Thieu) Nano-scale controller design (Weißbrich) AI-hardware co-design (Kautz, Beyer)
Javier Picorel is a former researcher at École Polytechnique Fédérale de Lausanne (EPFL), affiliated with the Parallel Systems Architecture Lab (Parsa). His work focuses on computer architecture, distributed systems, and cloud computing, with an emphasis on optimizing storage systems, near-data processing, and high-performance computing. Picorel has contributed to advancements in scalable serverless computing, secure data center architectures, and accelerator design. His research interests include storage-class memory hierarchies, virtual machine performance optimization, and software-defined systems. Key projects include BlockNDP for block-storage acceleration, IndiLog for stateful serverless systems, and SPARTA for accelerator address translation. He has collaborated extensively with the Parsa group and published widely in top conferences such as ISCA, MICRO, and PACT.
Dr. Hung Le is an Instructional Associate Professor at the University of Houston's Cullen College of Engineering, Department of Electrical and Computer Engineering. He holds IEEE Life Senior Member and Senior Member of the National Academy of Inventors statuses. With over 30 years of industry experience in computer, telecom, and oil/gas sectors, his expertise spans embedded systems, IoT, reconfigurable systems, and memory controller design. Education: M.Sc., Electrical Engineering, University of Alberta Ph.D., Electrical Engineering, University of Houston Research Interests: Embedded Systems & IoT Reconfigurable Systems (ASIC/FPGA) Memory Controllers Machine Learning His work emphasizes hardware-software co-design, adaptive systems, and secure memory architectures. Publications highlight advancements in memory subsystems, dynamic buffer mechanisms, and secure embedded systems. Over 20 patents underscore his contributions to memory management, password security, and low-power device communication. Advising focuses on graduate instruction, with no listed advisees. Professional experience includes adjunct roles (2005-2008) and current instructional professorship since 2017. No specific labs or teams explicitly mentioned, though his patents indicate involvement in interdisciplinary hardware research.
Steve Blackburn is a Professor of Computer Science at the Australian National University (ANU), affiliated with the ANU College of Systems & Society. His research focuses on programming language implementation, garbage collection algorithms, performance analysis, and high-performance runtime systems. He leads key projects like the DaCapo benchmark suite and the MMTk memory management framework. **Education & Background**: No specific education details provided, but his career spans decades with extensive contributions to computer science research. **Research Interests**: Blackburn prioritizes garbage collection innovation, memory management optimization, and empirical performance evaluation. His work bridges theory and practice, addressing challenges in managed runtimes, just-in-time compilation, and hardware-software co-design. He emphasizes reproducible research through shared infrastructure. **Recent Article Trends**: His 2020–2025 publications emphasize low-latency garbage collection, memory management in distributed systems (e.g., Mako collector for datacenters), and novel approaches to Java/JVM performance analysis. He also explores hardware features like transactional memory and their impact on runtime systems. **Awards**: ACM Fellow (2020+). **Grants & Leadership**: Served as Associate Dean for Diversity & Inclusion in ANU’s College of Engineering and Computer Science (2014–2019). Editorial roles include ACM TOPLAS Associate Editor (2017–2020) and program chairs for top conferences like PLDI (2015) and ISMM (2008). **Labs & Projects**: Leads the MMTk and DaCapo initiatives, foundational tools for memory management and benchmarking in academia and industry.
Alberto Ros Bardisa is a Professor at the Department of Computer Engineering and Technology within the Faculty of Informatics at the University of Murcia. He holds a Doctorate from the same university, completing his thesis on Efficient and Scalable Cache Coherence for Many-Core Chip Multiprocessors in 2009. His research focuses on computer architecture , with particular emphasis on cache coherence protocols , hardware transactional memory , speculative execution , and many-core systems . He has contributed to optimizing memory subsystems, concurrency management, and scalability in parallel computing environments. His work often bridges hardware-software co-design to enhance performance and security in modern architectures. Dr. Ros Bardisa is affiliated with the Computer Architecture and Parallel Systems research group and previously contributed to the Architecture and Parallel Computing group. His publications (over 130+ listed) reflect a sustained focus on advancing cache efficiency, transactional memory systems, and speculative execution techniques. His current work explores innovative solutions for fine-grain coherence , secure prefetching , and atomic operation optimization , with recent contributions in 2025 addressing novel protocols like WoperTM and MASCOT.
Nat Tantivasadakarn is a Sherman Fairchild Postdoctoral Scholar and Research Associate in Theoretical Physics at the California Institute of Technology (Caltech), affiliated with the Division of Physics, Mathematics and Astronomy. His research focuses on topological phases of matter, quantum computing architectures, and non-Abelian anyon systems. He explores theoretical frameworks to engineer topological order through gauging procedures, symmetry-enriched phases, and measurement-based protocols. Research areas include non-invertible symmetries, fracton models, and fault-tolerant quantum computation leveraging topological codes. He investigates protocols for creating anyons in trapped ion systems and developing scalable quantum error correction strategies. His work bridges abstract algebraic structures (e.g., cohomology invariants) with experimental realizations in quantum hardware. Key contributions involve constructing tensor networks for higher-dimensional topological phases and analyzing Nishimori transitions in quantum circuits. His research also addresses the interplay between measurement-driven dynamics and long-range entanglement, particularly in symmetry-protected topological systems. Tantivasadakarn collaborates with institutions like the Institute for Quantum Information and Matter (IQIM) at Caltech. No scientific awards are explicitly listed. His advising roles and grant details remain unspecified in available texts.
Peter M. Chen is the Arthur F. Thurnau Professor in the Department of Electrical Engineering and Computer Science (EECS) at the University of Michigan, part of the College of Engineering. He leads research in operating systems, distributed systems, and persistent memory technologies. His work includes foundational contributions to virtualization (e.g., ReVirt), reliable memory systems (Rio), and non-volatile memory semantics. He is a member of the Software Systems Lab and collaborates with the Computer Engineering Lab. Education and affiliations: Ph.D. in Computer Science (implied through career trajectory), affiliated with EECS and multiple labs at U-M. His research interests span speculative execution, security in distributed systems, and high-performance storage. He has advised over 20 graduate students, many of whom have contributed to seminal papers in systems research. Awards include the Arthur F. Thurnau Professorship and multiple best paper awards at top conferences like OSDI and SOSP. His work on ReVirt pioneered virtual machine logging for intrusion analysis, and Rio revolutionized reliable memory caching. Current projects focus on persistent memory programming models and wear management in NVM technologies. Key grants and teams: Active in NSF-funded projects on persistent memory systems and security. Collaborates with industry through partnerships in cloud computing and mobile systems optimization. His lab develops open-source tools like Rio and Vista, emphasizing practical system implementations alongside theoretical contributions.
Samira Mirbagher Ajorpaz is an Assistant Professor in the Department of Electrical and Computer Engineering at North Carolina State University. Her work focuses on the intersection of computer architecture, systems security, and machine learning, with an emphasis on designing secure, energy-efficient microarchitectures and optimizing hardware for machine learning models. She has held a postdoctoral fellowship at UC San Diego and was recognized as an MIT ECE Rising Star. Education: PhD in Computer Science, Texas A&M University (2019) BS in Computer Engineering, University of Isfahan (2014) Her research addresses pre-silicon security verification of microarchitectural designs, adversarial machine learning attacks, and dynamic hardware adaptation using generative AI. Key areas include mitigating timing side channels, enhancing processor efficiency, and developing formal frameworks for secure computing. Recent work explores attacks on speculative vectorization and Intel AMX-based vulnerabilities. Publications highlight contributions to cache performance optimization, instruction prefetching, and proactive adaptive architectures balancing performance and security. No grants or advising roles are explicitly detailed in the provided information.
Dr. Michael Schwarz is a tenured faculty member at the CISPA Helmholtz Center for Information Security in Saarbrücken, Germany, where he leads the RootSec research group. Since 2020 he has been investigating microarchitectural side-channel attacks, system security, CPU security, transient-execution vulnerabilities, and corresponding defense mechanisms. He previously served as a post-doctoral researcher (2019–2020) and PhD student (2016–2019) at Graz University of Technology, after earning two master’s degrees in computer science and software engineering with a security focus. Education PhD, Graz University of Technology, 2019 — “Software-based Side-Channel Attacks and Defenses in Restricted Environments” (Advisor: Daniel Gruss) MSc, Computer Science, Graz University of Technology MSc, Software Engineering, Graz University of Technology Research Interests Dr. Schwarz’s work centers on microarchitectural side-channel attacks and system security , spanning: CPU security and transient-execution vulnerabilities (Meltdown, Spectre, Fallout, LVI, ZombieLoad, ÆPIC Leak, CacheWarp) Detection, mitigation, and formal guarantees against microarchitectural leakage Hardware–software co-design for secure operating systems and trusted execution environments Reverse engineering of CPU internals, cache architectures, and prefetchers Browser and web-platform security, including sandbox bypasses and fingerprinting Compiler security and constant-time programming enforcement Scientific Awards & Recognition 2022 Busy Beaver Award for “Foundations of Cybersecurity II” 2021 Busy Beaver Award for “Side-Channel Attacks and Defenses” 2020 EuroSys Roger Needham PhD Award 2019 IEEE S&P Distinguished Paper Award (Spectre) 2019 NSA Best Scientific Cybersecurity Paper Competition Honorable Mention (Meltdown) 2019 Open Exploit Award (Meltdown & Spectre) 2018 CSAW Best Paper Award (Meltdown) 2018 Pwnie Awards: Best Privilege Escalation Bug & Most Innovative Research 2023 USENIX Security Noteworthy Reviewer Award 2023 WOOT Best Paper Award (CustomProcessingUnit) 2022 Pwnie Award for Best Desktop Bug (ÆPIC) 2022 AI 2000 Security & Privacy Honorable Mention 2021 CCSW Best Paper Award & CSAW Best Paper 3rd Place Advising & Collaborations Dr. Schwarz currently mentors numerous PhD students and post-docs within the RootSec group. His collaborations extend across CISPA, Graz University of Technology, and an international network visible through extensive multi-author publications at top-tier venues including USENIX Security, IEEE S&P, ACM CCS, NDSS, ESORICS, DIMVA, ASPLOS, WWW, FC, and specialized microarchitecture security conferences. Labs & Teams He heads the RootSec Research Group at CISPA, whose core mission is to uncover, analyze, and mitigate microarchitectural and system-level security threats. The group maintains close links with industry partners, open-source communities, and policy makers to ensure that research findings are rapidly translated into practical defenses deployed in modern operating systems and processors.
Jan-Åke Larsson is a Professor and Head of Department at the Department of Electrical Engineering (ISY) at Linköping University, Sweden. His academic career spans over two decades, with positions progressing from PhD student to Professor and department leadership. He has made significant contributions to quantum information science, particularly in quantum cryptography, quantum computing foundations, and Bell inequality tests. PhD in Applied Mathematics, Linköping University (2000) Docent in Applied Mathematics, Linköping University (2003) Professor Larsson's research primarily focuses on quantum technology, quantum information theory, and the foundations of quantum mechanics. His work explores the resources available to quantum computers that enable quantum advantage, the security of quantum cryptography systems (particularly classical subsystems), and fundamental questions of locality and contextuality in quantum mechanics. He has pioneered research in loophole-free Bell tests and developed theoretical frameworks for understanding quantum contextuality. His recent publications demonstrate a continued focus on foundational aspects of quantum mechanics while expanding into quantum computing algorithms and resource optimization. There's a clear trend toward addressing practical challenges in quantum computing implementation while maintaining a strong theoretical foundation in quantum information science. Contributed to Nobel Prize-winning research on quantum entanglement (2022 Physics Nobel) Key contributor to the "Big Bell Test" experiment published in Nature (2018) Significant contributions to loophole-free Bell inequality tests Professor Larsson has supervised multiple PhD students to completion, including Niklas Johansson (2022), Jonathan Jogenfors (2017), and Aysajan Abidin (2013), with Christoffer Hindlycke currently completing his PhD. His research has been supported by grants from the Swedish Research Council and other national and international funding bodies. He has collaborated extensively with leading quantum research groups worldwide, including those led by Nobel Laureate Anton Zeilinger. As Head of Department at ISY, Professor Larsson oversees one of Sweden's leading electrical engineering research and education units. He is actively involved in the Information Coding (ICG) research group, which focuses on quantum information, cryptography, and communication theory.
Mark Horowitz holds the Fortinet Founders Chair in Electrical Engineering and is the Yahoo! Founders Professor in Stanford University's School of Engineering. He also serves as Professor of Computer Science. His career spans over four decades, with foundational contributions to microprocessor design, high-speed link architectures, and computational photography innovations like the Lytro camera. Education: PhD in Electrical Engineering, Stanford University (1984) MS in Electrical Engineering, MIT (1978) BS in Electrical Engineering, MIT (1978) Research Interests: His work bridges EE and CS with interdisciplinary focus on: Agile hardware design methodologies for VLSI systems High-speed signaling and memory interfaces (e.g., Rambus technology) Reconfigurable computing architectures (e.g., CGRA-based accelerators) Applications in computational biology and molecular systems Recent Directions: Recent publications emphasize energy-efficient accelerators for machine learning, memory subsystem innovations, and compiler-driven hardware design frameworks like AHA! His work on Onyx and Opal architectures demonstrates leadership in sparse tensor computation hardware. Labs & Teams: Leads the Stanford VLSI Research Group and AHA! initiative. Collaborations include work with Prof. Marc Levoy on computational imaging and partnerships with industry on memory interface standards.
Elizabeth Varki is an Associate Professor and Graduate Program Coordinator in the Department of Computer Science at the University of New Hampshire's College of Engineering and Physical Sciences. Her research focuses on computer operating systems, simulation/modeling, and systems analysis. She holds a Ph.D. in Computer Science from Vanderbilt University and multiple advanced degrees from the University of Delhi and Villanova University. Her work emphasizes performance evaluation of computing systems, storage optimization, and parallel systems design. Key research contributions include innovative approaches to storage positioning (GPSonflow), RAID systems (RAIDX), and cache prefetching techniques. Her teaching spans courses like Operating System Fundamentals, Database Systems, and Distributed Systems. Varki's publications span ACM Transactions, IEEE journals, and major conferences in performance evaluation and storage systems. Her advising and grants focus on advancing storage and distributed systems research, though specific grant details are not provided here. She is affiliated with the UNH's Computer Science department and contributes to interdisciplinary efforts in computational performance analysis.
Xin Xin is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida since 2023, specializing in computer architecture with emphasis on memory systems and reliable hardware. Her educational background includes: Ph.D. in Electrical and Computer Engineering from University of Pittsburgh (2023) Master's degree from Tsinghua University (2016) Bachelor's degree from Lanzhou University (2013) Research focuses on resilient memory subsystems, domain-specific architectures, and hardware/software reliability. Key areas include processing-in-memory designs for databases, chip-kill ECC schemes, hybrid NVM-DRAM systems, and neural network accelerator reliability. Her work bridges computer architecture with IC design and semiconductor devices. Recent publications (2019-2022) demonstrate consistent contributions to memory hierarchy optimization across top conferences (MICRO, DAC, HPCA), featuring techniques for DRAM latency reduction, cache security, and in-memory processing. The research shows progression toward energy-efficient, fault-tolerant memory systems applicable to databases and AI workloads. She actively recruits PhD students for computer architecture research and serves as a journal reviewer for IEEE Computer Architecture Letters and Transactions on Embedded Computing Systems. Current projects include low-cost processing-in-memory for in-memory databases and reliable neural network accelerators.
Ivy Peng is an Associate Professor of Computer Science at KTH Royal Institute of Technology’s School of Electrical Engineering and Computer Science (EECS), where she leads the Scalable Computing Laboratory (ScaLab). She also holds a Docent title in Parallel Computing and is affiliated with the Digital Futures Faculty and the Cooperate Working Group. Prior to Sweden, she worked at the Lawrence Livermore National Laboratory (LLNL) as a Computer Scientist and as a post-doctoral fellow at Oak Ridge National Laboratory (ORNL) in the USA. Her research focuses on large-scale parallel systems, system-level optimization through workload and architecture awareness, performance modeling and analysis, and memory subsystem optimization. Key areas include converged HPC and cloud computing, heterogeneous accelerators (e.g., GPUs, RISC-V Vector units, QPUs, DPUs), and heterogeneous memories (e.g., persistent memory, HBM). She also explores disaggregated resources to enhance computing efficiency and scalability. Ivy Peng coordinates the EU Horizon 2022 Project OpenCUBE, which develops open-source cloud-based services for EPI systems, and leads the Swedish Research Council (VR) Grant on Disaggregated Memory for Emerging Parallel Systems. She actively contributes to technical committees and review boards for journals like IEEE TPDS and conferences including SC, ICS, HPDC, and IPDPS. She advises Ph.D. students Jacob Wahlgren, Gabin Schieffer, Ruimin Shi, and Daniel Medeiros, while co-supervising Jeremy Williams and Måns Andersson. Her academic leadership extends to multiple courses at KTH, including Applied GPU Programming, Introduction to High Performance Computing, and Quantum Computing for Computer Scientists.
