Aman Arora is an Assistant Professor at Arizona State University's Ira A. Fulton Schools of Engineering, specializing in the School of Computing and Augmented Intelligence. His research focuses on reconfigurable computing, hardware acceleration of machine learning, and non-traditional computing paradigms like Processing-In-Memory. With over a decade of semiconductor industry experience, he bridges academic research and industrial applications. PhD in Computer Science from The University of Texas at Austin Research interests emphasize domain-specific acceleration through FPGA optimization , compute-in-memory architectures , and machine learning for CAD/EDA . His work addresses critical challenges in energy efficiency and throughput for AI workloads. Recent publications demonstrate trends toward compute-in-memory systems , FPGA-based deep learning acceleration , and sustainable hardware design . Key contributions include frameworks like SAF, CSR, and GAMA for dynamic hardware optimization. Laboratory Website: ADVENT Lab Teaching includes courses on digital hardware design (CSE 320) and advanced topics in machine learning acceleration (CEN 524/CSE 524). Industry experience informs his practical approach to research and education.
Boris Murmann is Professor at Stanford University, specializing in integrated circuit design, mixed-signal computing, and energy-efficient AI hardware. His research advances neural interface technologies, analog design automation, and tinyML systems. Recent work develops ultra-low-power neural recording ICs for brain-computer interfaces, RRAM-based memory systems, and open-source semiconductor design frameworks. Publications demonstrate innovations in compressive sensing for neural data, hardware-algorithm co-design, and reinforcement learning for analog circuit synthesis. Significant contributions include Medusa (TinyML processor), EMBER (RRAM macro), and methodologies for coarsely-quantized computer vision and analog design automation.
Sara Vinco is an Associate Professor at the Department of Control and Computer Engineering (DAUIN), Politecnico di Torino, Italy. She specializes in battery simulation, digital twins, and energy-efficient design automation for heterogeneous embedded systems, aligning with Industrial and Information Engineering (Area 0009) and ERC sectors including Computer Architecture and Machine Learning . Her research focuses on advancing cyber-physical systems through simulation frameworks like SystemC-AMS, enabling holistic modeling of analog, digital, and thermal domains. Key projects include data-driven digital twins for EV batteries and low-area digital circuits in industrial/medical applications, supported by commercial contracts such as C-based virtual prototyping. Her recent publications (2022-2023) emphasize machine learning for battery SOH/SOC estimation , energy monitoring in production lines , and multi-domain fault modeling . These works span journals like IEEE Transactions and conferences including DATE and ISLPED. Awarded the FFABR 2017 grant and IEEE FDL Best Paper Award 2011 , she also chairs editorial boards for IEEE Transactions on CAD and DATE Conference. She supervises PhD students Giovanni Pollo (Digital Circuits) and Khaled Alamin (EV Battery Twins), reflecting her leadership in smart systems design.
Kwantae Kim is an Assistant Professor at the Department of Electronics and Nanoengineering within Aalto University's School of Electrical Engineering . He leads the Tiny Systems and Circuits (TSirc) Group , focusing on power-efficient analog/mixed-signal ICs for biomedical and neuromorphic sensor systems. IEEE Senior Member (2025) Collaborates with institutions across Europe, Asia, and America Specializes in ultra-low-power AI-embedded IoT platforms His research emphasizes Tiny, Sensory, Intelligent, and Wireless IoT systems through: Development of energy-efficient IC architectures Democratizing access to advanced chip design Hardware-software co-design for edge computing Recent publications highlight innovations in: Spoken-language-understanding SoCs Temporal-sparsity-aware keyword spotting Open-source silicon frameworks Awards include: 2025 IEEE Senior Member 2023 Best Poster Award (AICAS) 2019 Samsung HumanTech Silver Award Research partnerships span: Prof. Tobi Delbruck (UZH/ETH Zurich) Prof. Hoi-Jun Yoo (KAIST) Prof. Shih-Chii Liu (UZH) Prof. Sohmyung Ha (NYU Abu Dhabi)
John Wawrzynek is a Professor of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He is affiliated with the Department of Electrical Engineering and Computer Sciences in the College of Engineering and serves as Co-Director of the Berkeley Wireless Research Center and Co-PI of the CONIX Research Center, one of the six centers in the Joint University Microelectronics Program sponsored by DARPA. Dr. Wawrzynek received his B.S. in Electrical Engineering from SUNY, Buffalo (1977), M.S. in EE from the University of Illinois, Urbana/Champaign (1979), and Ph.D. in Computer Science from Caltech (1987). Before joining the Berkeley faculty in 1988, he worked as a consultant at Schlumberger Palo Alto Research. His research focuses on Computer Architecture, Reconfigurable Computing, Wireless Systems, and Integrated Circuit and System Design . His work spans both theoretical foundations and practical implementations, with particular emphasis on FPGA-based computing systems, reconfigurable architectures, and wireless communication systems. His research group has made significant contributions to the field of reconfigurable computing, including the development of the Garp architecture and various tools for reconfigurable computing systems. Analysis of his recent publications (2022-2025) reveals continued focus on reconfigurable computing, FPGA design, wireless networking, and formal methods for hardware verification. His work shows an evolution from traditional computer architecture towards specialized hardware acceleration, machine learning for EDA, and wireless systems research, with particular emphasis on SAT sampling, differentiable computing, and efficient FPGA implementation of neural networks. DAC's Most Influential Paper Award (2025) NSF Presidential Young Investigator (PYI) (1989) Charles Lee Powell Fellowship (1985) NASA Certificate of Recognition (1983) Rensselaer Engineering and Science Medal (1975) Professor Wawrzynek has advised numerous graduate students throughout his career, many of whom have gone on to prominent positions in both industry and academia including Google, Xilinx, and MIT Lincoln Laboratory. His research has been supported by various grants from NSF, DARPA, and industry partners. He leads the Berkeley Wireless Research Center, which focuses on next-generation wireless communication systems and technologies, and is actively involved in the CONIX Research Center which explores connected intelligence at the network's edge.
Ningyuan Cao is an Assistant Professor in the Department of Electrical Engineering at the University of Notre Dame, College of Engineering. He leads the Circuit and System Intelligence Research Lab , focusing on the intersection of advanced hardware design and real-time/low-power machine learning applications. Education : Ph.D., Electrical and Electronics Engineering, Georgia Institute of Technology (2020) M.S., Electrical Engineering, Columbia University (2015) B.S., Electrical and Electronics Engineering, Shanghai Jiao Tong University (2013) His research investigates custom analog/mixed-signal circuits , digital architecture , and micro-system design for machine learning acceleration, distributed intelligence, and data-driven IC design automation. Key application domains include Internet-of-Everything, tactile internet, and mixed reality systems. Recent publications highlight work on Bayesian neural networks , privacy-preserving bio-signal encoders , transformer-based surrogate models , and compute-in-memory architectures . Technical themes span neuromorphic computing, uncertainty quantification, and hardware security.
Dr.-Ing. Thomas Wild serves as an Academic Director at the Technical University of Munich (TUM), working within the TUM School of Computation, Information and Technology at the Chair of Integrated Systems. He maintains an active research and teaching role at the institution, with his office located in Building N1 (Theresienstr. 90), Room N2136 in Munich, Germany. Dr. Wild's research focuses on advanced computing architectures, with particular emphasis on manycore system on chip (SoC) architectures, network processor (NPU) architectures, on-chip communication architectures including networks on chip (NoC), and system level design methodologies. His work bridges theoretical research with practical implementation, often exploring design space exploration techniques to optimize system performance. The evolution of his research over two decades demonstrates a consistent focus on improving communication architectures and system-level design for embedded and high-performance computing platforms. His recent publications (2023-2025) reveal a growing integration of machine learning techniques with traditional hardware design, particularly in optimizing power-performance tradeoffs in embedded systems. There's a clear trend toward hardware-software co-design approaches, with significant work on SmartNICs, Linux system optimization, and network processing acceleration. His research shows strong interdisciplinary connections between computer architecture, networking, and machine learning. EUROPRACTICE representative for TUM city campus, facilitating access to commercial EDA tools for academic purposes Active collaborator with Professor Andreas Herkersdorf and other researchers at TUM Focus on practical implementations with FPGA-based prototyping and real system modifications Dr. Wild teaches several hardware design courses including VHDL Lab, SystemC Lab, and HW/SW Codesign, contributing to the education of next-generation computer engineers. His teaching directly complements his research in system design and hardware acceleration, providing students with hands-on experience in cutting-edge technologies.
David Zhigang Pan is a Professor in the Department of Electrical & Computer Engineering at The University of Texas at Austin. He also holds the Silicon Laboratories Endowed Chair. Prior to joining UT Austin, he was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. His academic journey began with a B.S. from Peking University, followed by M.S. and Ph.D. degrees from UCLA. Research Areas: Electronic Design Automation (EDA), Machine Learning Hardware, FPGA Prototyping, Optical Computing, Hardware Security, and CAD for Emerging Technologies Academic Timeline: Assistant Professor (2003-2008), Associate Professor (2008-2013), Full Professor (2013-present) His research focuses on design automation for mixed-signal circuits , GPU-accelerated EDA tools , and hardware-software co-design for AI . Recent work explores FFT-based optical neural networks and deobfuscation techniques for integrated circuits , reflecting his interdisciplinary approach at the intersection of machine learning , computer architecture , and semiconductor manufacturing . Key publication trends reveal expertise in: VLSI design , lithography optimization , and deep learning applications for EDA tools. His work has been recognized with multiple Best Paper Awards at top conferences including DAC , ASP-DAC , and HOST . Awards: IEEE Fellow (2014), SPIE Fellow (2017), ACM SRC Graduate Category Honors for students Patents: 8 U.S. Patents in electronic design and hardware optimization Prof. Pan has mentored 40 PhDs and postdocs who now hold key positions in academia and industry. He leads research initiatives involving GPU acceleration frameworks and optical computing architectures . His lab focuses on vertical integration of architecture, CAD tools, and fabrication technologies for next-generation hardware solutions.
Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.
Lisa Wu Wills is an Assistant Professor in the Department of Computer Science and Electrical and Computer Engineering at Duke University, leading the APEX Lab (Application-driven Programmable Efficient Accelerated Systems Lab). Her research focuses on hardware acceleration for big data analytics in genomics, graphs, and databases to advance healthcare and natural sciences. Education: Ph.D. in Computer Science, Columbia University, 2014 Research Interests: Dr. Wills pioneers computer architecture and hardware-software co-design to create efficient accelerators for emerging applications. Her work targets genomics , graph analytics , and database systems , emphasizing simplified hardware deployment and energy efficiency for scientific breakthroughs in healthcare and AI. Publication Trends: Her 2022-2025 publications reveal a strong focus on open-source frameworks (Beethoven, PyTFHE) for accelerator development, hardware acceleration in privacy-preserving computing, and optimization for large language models. Key themes include transfer learning for EDA, domain-specific architectures for genomics, and energy-efficient image processing. Scientific Awards: Google ML and Systems Junior Faculty Award (2025) Advising and Grants: Dr. Wills mentors three PhD students: Chris Kjellqvist (Beethoven framework architect), Mason Ma (PyTFHE lead for FHE applications), and Mansi Choudhary (COCOSSim simulator creator). Her 2025 Google award funds research on accelerating vector databases and retrieval-augmented generation for LLMs. Labs and Teams: She directs the APEX Lab at Duke, developing tools like Beethoven (open-source accelerator composer) and PyTFHE for hardware-software integration, enabling domain scientists to leverage custom acceleration with minimal hardware expertise.
Patrick H. Madden is an Associate Professor and Director of the MS Information Systems program at the School of Computing, Binghamton University. His research focuses on combinatorial optimization, VLSI physical design automation, and algorithmic solutions for NP-Hard problems. He is also involved in interdisciplinary work in cryptography and biology-related optimization. Education: BS and MS from New Mexico Institute of Mining and Technology PhD from University of California, Los Angeles (UCLA) Professional Roles: Chair of ACM/SIGDA (Design Automation Special Interest Group) Chair of Design Automation Conference (DAC) Sponsors Committee Advisor to Binghamton ACM Student Chapter Coach for ICPC Programming Contest Teams Member of Watson School Graduation Committee Research Contributions: Leads the Optimality Research Group, developing optimization algorithms for VLSI CAD and medical software applications. Notable contributions include the Feng Shui placement tool and medical reference apps for iOS/Android platforms. Awards: SUNY Chancellor's Award for Excellence in Professional Service (2015) Grants & Collaborations: Collaborates with Prof. Monte McCollum (Cinema Department) on hybrid cinema projects and Dr. Joshua Steinberg (Physician) on medical software. Active in ACM committees and EDA conferences (DAC, ICCAD, ISPD). Labs/Teams: Directs the Optimality Research Group and oversees medical software collaborations through CS441/580 projects.
Jiannan Wang is an Associate Professor in the School of Computing Science at Simon Fraser University (SFU). He holds a Ph.D. from Tsinghua University (2013) and a B.Sc. from Harbin Institute of Technology (2008). His research focuses on database systems, data management, and data science, with particular emphasis on data cleaning, crowdsourcing, and big data technologies. He leads the SFU Data Science Research Group, aiming to accelerate data science workflows through innovative tools like DataPrep and ConnectorX. Education: Ph.D. in Computer Science and Technology, Tsinghua University, China (2013) B.Sc. in Computer Science and Technology, Harbin Institute of Technology, China (2008) Research Interests: Dr. Wang's work spans database systems, data cleaning, crowdsourcing, and big data education. He develops open-source tools for data scientists to streamline data preparation and analysis. His lab's mission is to make data science more efficient through technologies like DataPrep and ConnectorX . Awards: IEEE TCDE Rising Star Award (2018) CS-Can|Info-Can Outstanding Early Career Researcher Award (2020) VLDB Best Experiments, Analysis & Benchmark Paper Award (2021) PVLDB Distinguished Review Board Member Award (2020) Advising & Leadership: Director of SFU's Professional Master's Program in Big Data and Visual Computing. Supervised over 20 graduate and undergraduate students, many of whom have gone on to roles at top companies like Google, Amazon, and Huawei. Lab & Teams: Part of the SFU Data Science Research Group and the SFU Big Data Academic Advisory Committee. His lab collaborates with industry partners and contributes to open-source projects in data management and machine learning.
Dr. Yiran Chen is the John Cocke Distinguished Professor at Duke University's Department of Electrical and Computer Engineering, leading the NSF AI Institute for Edge Computing (Athena) and the Duke Center for Computational Evolutionary Intelligence (DCEI). A global leader in neuromorphic computing, emerging memory systems, and edge AI, he holds prestigious roles including IEEE Fellow and Editor-in-Chief of IEEE Transactions on Circuits and Systems for AI. His research spans machine learning accelerators, security-hardened hardware, and co-design of EDA tools with LLMs. With over 700 publications and 96 patents, he has been awarded 15 paper awards and 17 nominations, including rare Technical Achievement Awards from IEEE societies. He advises over 60 PhD students and 4 postdocs, many of whom hold academic positions worldwide. His work bridges academia and industry, contributing to startups and venture capital through his board roles. Education: B.S. (Tsinghua, 1998) → M.S. (Tsinghua, 2001) → Ph.D. (Purdue, 2005). Career path: Assistant/Associate Professor at University of Pittsburgh (2010–2014) → Duke since 2014. Awards include the ACM SIGDA Outstanding New Faculty Award (2014), NSF CAREER Award (2013), and the Stansell Family Distinguished Research Award (2022). Research focuses on innovations in: (1) Non-volatile memory architectures for AI acceleration, (2) Hardware-software co-design for edge computing, (3) Security in neuromorphic systems, and (4) Large-scale ML for EDA. His group pioneered ReRAM-based accelerators like ReBNN and MARC, and introduced novel edge AI frameworks like Ecco and Prosperity. These works address scalability, energy efficiency, and real-time performance challenges. Key initiatives include the NSF IUCRC for Alternative Sustainable & Intelligent Computing (ASIC), advancing sustainable computing through novel materials and architectures. His leadership in standard-setting bodies like the IEEE Circuits and Systems Society ensures cutting-edge research translates into industry practices. Grants: Lead PIs for multiple NSF AI Institutes and industry partnerships. Labs: Directs the Athena Institute and DCEI, fostering collaboration between academia and industry. Current projects include quantum computing placement algorithms (QPlacer), federated learning frameworks (FedGPT), and neuro-symbolic architectures.
Georges Gielen is Full Professor in the Department of Electrical Engineering (ESAT) at KU Leuven, Belgium, and part-time Research Director at imec. He has held multiple leadership roles including Chair of ESAT Department (2012-2013, 2020-2024) and Vice-Rector for Science, Engineering & Technology (2013-2017). His academic career spans over 30 years at KU Leuven, progressing from Assistant to Full Professor. His research focuses on analog and mixed-signal integrated circuit design automation , with expertise in CAD tools, design optimization, sensor interfaces, and neuromorphic systems. His work bridges hardware design with machine learning, particularly in hardware-efficient AI implementations and biomedical applications. He has pioneered techniques for automated analog circuit sizing, topology synthesis, and reliability-aware design in nanometer CMOS. Gielen has received numerous accolades including the IEEE CAS Mac Van Valkenburg Award (2015), IEEE CAS Charles Desoer Award (2020), and EDAA Achievement Award (2021). He holds an ERC Advanced Grant AnalogCreate and is an IEEE Fellow since 2002. As a prolific scholar, he has chaired major conferences including DATE (2006), ICCAD (2007), and ESSCIRC (2017). He has graduated over 55 PhD students through the MICAS research group at KU Leuven, currently supervising 13 doctoral candidates. His research team collaborates extensively with imec and industry partners on cutting-edge projects in carbon-aware AI accelerators, uncertainty-aware design, and neuromorphic sensor interfaces.
Farinaz Koushanfar is a Professor in the Department of Electrical and Computer Engineering at the Jacobs School of Engineering, University of California San Diego (UCSD) . She holds the Siavouche Nemat-Nasser Endowed Chair and serves as Founding Co-Director of the Center for Machine-Intelligence, Computing and Security . Her affiliations include NSF Trust-Hub (Co-PI) and NSF TILOS AI Institute . She also serves on the Editorial Board of The Proceedings of the IEEE . Research Focus: Prof. Koushanfar leads research in secure and efficient computing , including robust/safe AI , hardware/system security , AI-based optimization , and cryptographically secure privacy-preserving computing . Her work pioneered logic obfuscation/locking for chip security, automated co-design of AI systems , watermarking/tracing of deep learning models , and physical proofs of provenance . She explores co-design with cryptographic constructs for privacy preservation and manages nonlinearities in ciphertext domains. Article Trends: Recent publications show expertise in neural watermarking (deepfakes, media authentication), zero-knowledge proof frameworks , Trojan attack defenses in ML models, secure federated learning , and hardware acceleration of cryptographic protocols . Her work combines machine learning , cryptography , and physical design security across 2022-2025 publications. Scientific Awards: Fellow of ACM Fellow of IEEE Fellow of National Academy of Inventors (NAI) Fellow of Kavli Foundation of NAS Inducted to NAI 2024 Fellows Advising & Leadership: She has advised multiple PhD students who became faculty at top universities (e.g., Stanford, Purdue). She chairs conferences like ACM WiSec 2024 and co-led the NSF SaTC decadal review. Her lab ( ACES Lab ) produces award-winning graduates like Bita Rouhani (DAC Under-40 Innovators) and Shehzeen Hussain (UCSD Best Dissertation Award).
