Professor Jacob Savir is a distinguished academic in the Department of Electrical and Computer Engineering at the New Jersey Institute of Technology . He specializes in testability, built-in self-test (BIST), and fault detection for digital and analog circuits. His work focuses on improving integrated circuit testing methodologies, including BIST pretesting, defect level analysis, and reliability optimization in safety-critical systems. His research interests span BIST architectures, delay fault analysis, analog circuit testing, and power-constrained test synthesis . He has contributed extensively to the development of testing algorithms for embedded memories, scan designs, and fault diagnosis in complex systems. Notable contributions include studies on the impact of BIST pretesting on IC defect levels and yield optimization. His work bridges theoretical advancements with practical applications in aerospace and industrial electronics. Despite no awards listed, his substantial citation count (1,897) and h-index (22) reflect his influential contributions to the field. Prof. Savir has collaborated on 114 research outputs since 1977, with a focus on enhancing circuit testability and reliability across domains like FPGA-based systems and embedded memory diagnostics. His research emphasizes both academic rigor and industrial relevance, addressing challenges in modern VLSI design and testing.
