Boris Murmann is Professor at Stanford University, specializing in integrated circuit design, mixed-signal computing, and energy-efficient AI hardware. His research advances neural interface technologies, analog design automation, and tinyML systems. Recent work develops ultra-low-power neural recording ICs for brain-computer interfaces, RRAM-based memory systems, and open-source semiconductor design frameworks. Publications demonstrate innovations in compressive sensing for neural data, hardware-algorithm co-design, and reinforcement learning for analog circuit synthesis. Significant contributions include Medusa (TinyML processor), EMBER (RRAM macro), and methodologies for coarsely-quantized computer vision and analog design automation.
Steven Swanson is a Professor in the Department of Computer Science and Engineering at the University of California, San Diego, within the Jacobs School of Engineering. He is the Director of the Non-Volatile Systems Laboratory (NVSL), where he leads cutting-edge research in non-volatile memory, storage systems, and hardware-software co-design. His work bridges computer architecture, systems, and software to develop efficient, reliable, and secure computing platforms. Ph.D., University of Washington, 2006 B.S., University of Puget Sound, 1999 Dr. Swanson's research centers on non-volatile and persistent memory systems , exploring how next-generation storage technologies can transform computing. His lab develops full-stack solutions including file systems like NOVA and Orion , programming models such as NV-Heaps , and hardware prototypes like Moneta and Onyx . The team also works on low-power co-processors (e.g., GreenDroid ) and tools for debugging and verifying persistent memory programs. Research spans system reliability, security, energy efficiency, and performance optimization. His recent publications reveal a strong focus on persistent memory safety , zero-copy I/O , RDMA-based distributed file systems , and real-world characterization of Intel Optane . These works appear in top venues including ASPLOS, FAST, MICRO, and USENIX ATC, demonstrating sustained innovation in storage and systems research. Scientific honors include: NSF CAREER Award Google Faculty Award Facebook Faculty Award NetApp Faculty Fellow Dr. Swanson has advised 15 PhD students and 4 postdocs , many now faculty or senior engineers at Google, Microsoft, Intel, and other leading tech firms. He has secured significant research funding and leads major community initiatives such as the annual Non-Volatile Memories Workshop and Persistent Programming In Real Life (PIRL) . His educational efforts include innovative courses on robotic system design, quadcopter building, and modern storage systems, emphasizing hands-on learning and real-world implementation. The Non-Volatile Systems Laboratory (NVSL) under his leadership fosters a collaborative, international research environment, hosting visitors and postdocs from around the world. The lab is recognized globally as a pioneer in storage systems research and a key contributor to the adoption of persistent memory technologies in industry.
Austin Rovinski is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University’s Tandon School of Engineering. He specializes in chip design, electronic design automation (EDA), and open-source hardware methodologies. His research focuses on VLSI design, domain-specific accelerators, and chiplet-based systems. Prior to NYU, he held a postdoctoral position at Cornell University and earned all his degrees (Ph.D., M.S., and B.S.) from the University of Michigan. Education: Ph.D., Electrical Engineering, University of Michigan - Ann Arbor Master’s, Electrical Engineering, University of Michigan - Ann Arbor Bachelor’s, Electrical Engineering, University of Michigan - Ann Arbor Research Focus: Developing open-source EDA frameworks like OpenROAD Optoelectronic interconnect systems for 2.5D packaging Agile hardware design methodologies Reconfigurable sparse matrix accelerators RISC-V-based manycore processors (e.g., Celerity project) Key Contributions: Austin led the development of the OpenROAD RTL-to-GDS flow and contributed to the Sirius and Celerity projects. His work emphasizes reproducibility, democratizing chip design through open-source tools. Awards: IEEE Micro Top Picks (2015) Michigan EECS Outstanding Research Award (2016) NSF Graduate Research Fellowship Honorable Mention (2017, 2018) Advising & Grants: Actively mentors graduate students in chip design and EDA. His research is supported by NYU’s Tandon School of Engineering and collaborations with industry partners. Labs & Teams: Core contributor to the OpenROAD project, part of NYU’s hardware design and EDA initiatives, and collaborator on the Celerity manycore processor project.
Uzi Vishkin is a Professor at the University of Maryland's Institute for Advanced Computer Studies (UMIACS) and Department of Electrical and Computer Engineering, with additional affiliation in the Department of Computer Science. His work focuses on parallel computing, including the PRAM-On-Chip vision to bridge parallel algorithms and hardware. He holds a D.Sc. from Technion (1981), M.Sc. and B.Sc. in Mathematics from Hebrew University (1975/1974). Research interests span parallel algorithms, PRAM (Parallel Random Access Machine) architecture, machine learning applications, and pattern matching. His PRAM-On-Chip project aims to create a coherent computing stack for many-core processors. Vishkin has contributed to theoretical foundations and practical implementations, including the XMT architecture and compiler. He has been recognized with ACM Fellow (1996), Highly Cited Researcher (2003), and National Academy of Inventors Fellow (2024). Awards highlight his pioneering work in parallel algorithms and computing systems. Teaching spans courses like Parallel Algorithms and Mathematical Foundations for Computer Engineering. He emphasizes parallel algorithmic thinking in education and has developed teaching materials for high school and university levels. Key projects include the XMT architecture, simulations, and tools for parallel programming. His work integrates algorithmic theory with hardware design to address programming challenges in many-core systems.
Michael Ferdman is an Associate Professor in the Department of Computer Science at Stony Brook University, where he leads research in computer architecture and systems. His office is located in Room 343 at Stony Brook, NY 11794-2424, and he can be contacted via phone (631-632-8449) or email. Ferdman directs the Computer Architecture and Systems Laboratory (compas.cs.stonybrook.edu), focusing on next-generation server infrastructure. Ferdman's research spans the entire computing stack with emphasis on: FPGA integration for server environments (Intel HARP, Microsoft Catapult) Machine learning accelerators for convolutional neural networks Server systems optimization in the post-Moore era Network processing and software-defined networking Programming models for emerging memory technologies (HBM, 3D XPoint) Reconfigurable hardware and high-level synthesis His work addresses both performance and security challenges in modern computing infrastructure. Analysis of his 15 most recent publications (2022-2025) reveals consistent focus on: Hardware acceleration techniques (FPGAs, specialized processors) Memory hierarchy optimization and cache management Security vulnerabilities in web applications and systems Post-Moore computing architectures Parallel processing and distributed systems His research shows strong emphasis on practical implementations bridging hardware and software layers. Awards recognizing his contributions include: Graduate Teaching Award (2014) Best Paper Award at ASPLOS XVII Best Paper Finalist at HPCA XVII Three IEEE Micro Top Picks selections (2009, 2012) He teaches advanced courses including CSE 502, CSE 602, and CSE 506 at Stony Brook University.
Dr. Alessandro Ottaviano is a Researcher affiliated with the Department of Digital Integrated Circuits and Systems at ETH Zürich. His work focuses on advanced computer architecture and embedded systems, particularly in the domains of RISC-V processors, real-time systems, and heterogeneous computing. He contributes to the design of time-predictable virtual memory solutions, mixed-criticality systems, and energy-efficient hardware-software interfaces. Key research areas include modular processor architectures, hardware monitoring for safety-critical applications, and power management in high-performance computing (HPC) systems. His recent projects involve developing controllers for 2.5D systems-in-package and creating open-source networking solutions for mixed-criticality environments. Ottaviano’s work often emphasizes open-source hardware design and scalable system-level approaches to address challenges in autonomous systems and edge computing. He collaborates on advancements in interrupt handling for virtualized systems, peripheral event linking for IoT devices, and FPGA-based thermal emulation for many-core processors. His research bridges theoretical computer architecture principles with practical implementations in embedded and real-time systems.
Timothy Rogers is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University, located in West Lafayette. His research focuses on GPU architecture, parallel processing, and simulation frameworks, with particular emphasis on optimizing hardware acceleration, memory systems, and concurrency management. He holds an office at BHEE 326A and can be reached at timrogers@purdue.edu. His work spans GPU performance modeling, SIMT architecture analysis, and energy-efficient computing. Recent contributions include frameworks like ThreadFuser for MIMD program analysis, CRISP for concurrent rendering, and Simr for data center microservices. He has also contributed to hardware ray tracing units and RISC-V core integration studies. Rogers has been active in conference leadership, serving as General Chair for ISPASS 2024 and securing NSF travel grants for student participation. His research bridges theoretical architecture design with practical implementation, addressing challenges in modern massively parallel systems.
Eby G. Friedman is a Professor in the Department of Electrical and Computer Engineering at the University of Rochester, where he has served since 1991 as director of the High Performance VLSI/IC Design and Analysis Laboratory. He concurrently holds a visiting professor position at the Technion - Israel Institute of Technology, directing the Technion Advanced Circuits Research Center (ACRC). His research specializes in high performance synchronous digital and mixed-signal microelectronic design with applications in high-speed portable processors and low-power wireless communications. Core focus areas include CMOS circuit design, clock/power distribution networks, interconnect synthesis, substrate noise mitigation, pipelining techniques, and 3-D integration methodologies. His work bridges theoretical frameworks with practical implementations in VLSI systems. Scientific Awards and Honors IEEE Fellow Distinguished Lecturer of the IEEE CAS Society Dr. Friedman has authored or edited 16 books and nearly 500 publications, establishing foundational contributions in clock distribution and power delivery networks. He maintains significant editorial leadership as Editor-in-Chief of the Microelectronics Journal, past Editor-in-Chief of IEEE Transactions on VLSI Systems, and serves on the editorial boards of the Journal of Low Power Electronics, Journal of VLSI Signal Processing, Journal of Low Power Application and Circuits, and Proceedings of the IEEE. His laboratory directs cutting-edge research in high-speed circuit design and 3-D integration architectures.
Dr. Scott Chen is an Assistant Professor in the Department of Electrical & Computer Engineering at McMaster University, where he focuses on teaching and research in embedded systems, RF technologies, and biomedical sensors. He previously held roles as a lecturer at the University of Waterloo and program coordinator at Conestoga College, alongside industry experience in embedded systems engineering and sensor development. Education: B.A.Sc. (Simon Fraser University, 2007) and Ph.D. (University of Waterloo, 2015), followed by a MITAC postdoctoral fellowship. His industry experience includes roles at Thalmic Labs/North, Sober Steering Sensors, and Equustek Solutions. Research interests span embedded systems for IoT, RF biomedical sensors, cleanroom micro/nano-fabrication, and game design in Unity. Notable achievements include a 2018 US patent for ethanol sensing technologies and a 2021 teaching award nomination. Current courses taught include Principles of Programming (COMPENG 2SH4), Data Structures and Algorithms (COMPENG 2SI3), and Introduction to Electrical Engineering (ELECENG 2CI4). Awards: US Patent 9,958,444B2 (2018), nominated for Aubrey Hagar Distinguished Teaching Award (2021). His work bridges academia and industry, emphasizing practical applications in wearable sensors, quantum computing components, and interdisciplinary engineering solutions.
Kevin P. O'Brien is an Associate Professor in the Department of Electrical Engineering and Computer Science (EECS) at the Massachusetts Institute of Technology (MIT), affiliated with the Research Laboratory of Electronics (RLE). He leads the Quantum Coherent Electronics (QCE) group, focusing on advancing superconducting quantum computing, microwave quantum optics, and quantum metamaterials. His research explores nonlinear and quantum-mechanical light-matter interactions using superconducting circuits, aiming to improve quantum technologies like qubits and amplifiers. Education: B.S. in Physics from Purdue University, Ph.D. in Physics from UC Berkeley, and postdoctoral research at UC Berkeley developing superconducting quantum processors. His group collaborates with MIT Lincoln Laboratory and institutions nationwide. Research Interests: Quantum computing hardware, superconducting circuits, parametric amplifiers, qubit measurement systems, and metamaterials for quantum applications. His work emphasizes scalable architecture design, noise reduction, and novel device concepts. Key projects include directional qubit readout resonators, Floquet-mode amplifiers, and quarton couplers for ultrafast readout. The group actively engages in training graduate students and postdocs, emphasizing open collaboration and problem-solving in quantum technologies. Advising & Grants: Supervises a dynamic team of graduate students and postdocs. Students like Bright Ye and Kaidong Peng have contributed to award-winning projects. The group receives support through fellowships (e.g., Jin Au Kong, NSF GRFP) and industry partnerships. Labs/Teams: Quantum Coherent Electronics Group at MIT, collaborating on quantum device fabrication, theoretical modeling, and experimental validation of quantum systems.
Melissa C. Smith is a Professor of Electrical and Computer Engineering and Associate Dean for Graduate Studies at Clemson University. She holds a Ph.D. from the University of Tennessee and degrees from Florida State University. Her research focuses on machine learning, reconfigurable computing, and high-performance systems, with applications in embedded systems and interdisciplinary scientific advancements. Before joining Clemson in 2006, she was a research associate at Oak Ridge National Laboratory (ORNL), contributing to projects like the Spallation Neutron Source and PHENIX experiments. Education: Ph.D., Electrical and Computer Engineering, University of Tennessee M.S., Electrical Engineering, Florida State University B.S., Electrical Engineering, Florida State University Research Interests: Machine Learning and AI High-Performance and Reconfigurable Computing System Performance Modeling Embedded Systems Articles Summary: Her recent work spans machine learning applications, GPU/FPGA architectures, speech enhancement, and medical systems. Key themes include optimizing heterogeneous computing for real-time and scientific workloads, and advancing interdisciplinary solutions through architecture-application co-design. Lab & Collaborations: Leads the Future Computing Technologies Lab and collaborates with ORNL and national labs on projects like GEMmaker and HPC-enabled medical systems.
Alaa Alameldeen is an Associate Professor in the School of Computing Science at Simon Fraser University (SFU), part of the Faculty of Applied Sciences. Previously, he worked as a Research Scientist at Intel Labs (2006–2020) and held an Adjunct Faculty position at Portland State University (2008–2018). He earned a PhD in Computer Sciences from the University of Wisconsin-Madison (2006), and earlier degrees from Alexandria University, Egypt. His research focuses on computer architecture, including memory systems (processing-in-memory, cache/memory compression, security), energy-efficient architectures, and hardware-software co-design for machine learning. He advises PhD and MSc students in these areas and teaches advanced computing science courses. Key contributions include innovations in memory hierarchies, cache compression techniques, and mitigating hardware vulnerabilities. His work has been published in top conferences (e.g., ISCA, MICRO, HPCA) and patented in areas like near-memory processing and error correction. Alameldeen currently leads a research group exploring secure and high-performance memory architectures. He has supervised multiple graduate students, with many progressing to roles at leading tech companies and academic institutions.
Professor David Thomas holds the position of Professor in Computer Engineering at the University of Southampton's Electronics and Computer Science Department. His research focuses on the intersection of software and hardware, particularly leveraging FPGAs for novel digital architectures and event-driven computing. He has a notable academic trajectory, having previously served as a Lecturer and Senior Lecturer at Imperial College London before joining Southampton in 2021. Dr. Thomas is actively involved in supervising PhD students and contributes to interdisciplinary research projects funded by the EPSRC, such as the SONNETS initiative exploring scalable event-triggered systems. Education: BSc in Computer Science (Imperial College London), PhD in Digital Architectures (Imperial College London). Postdoctoral roles included Research Associate and Research Fellow at Imperial's Department of Computing. Research Interests: Event-driven computing, FPGA-based systems, high-level synthesis, and high-performance computing. His work emphasizes practical implementations of theoretical models, such as custom processors and application-specific accelerators. Current projects include optimizing random number generation for FPGAs and exploring meta-programming techniques for hardware design. Advising and Grants: Supervises multiple PhD students in areas like neuromorphic computing and algorithm optimization. Active in securing funding for distributed system architectures and FPGA-based solutions. Labs/Teams: Member of the Cyber Physical Systems research group. Collaborates with interdisciplinary teams on projects like POETS (Partially Ordered Event-Triggered Systems) for large-scale parallel computing.
Garnet K. Chan is the Bren Professor of Chemistry and Director of the Rudolph A. Marcus Center for Theoretical Chemistry at the California Institute of Technology. He received his B.S. from the University of Cambridge in 1996 and his M.A. and Ph.D. from the University of Cambridge in 2000. Dr. Chan's research lies at the interface of theoretical chemistry, condensed matter physics, and quantum information theory, focusing on quantum many-particle phenomena and the numerical methods to simulate them. His group has developed numerous methodologies including density matrix renormalization and tensor network algorithms, canonical transformation-based down-foldings, local quantum chemistry methods, quantum embeddings, and new quantum Monte Carlo algorithms. His work addresses problems that appear naively exponentially hard but where understanding of physics, particularly entanglement structure, allows for calculations of polynomial cost. Analysis of his recent publications reveals a strong focus on quantum simulation techniques, particularly tensor network methods applied to strongly correlated systems. His research spans fundamental theoretical developments to practical applications in quantum computing, molecular simulation, and materials science, with increasing integration of machine learning techniques and GPU acceleration in computational chemistry frameworks. Dr. Chan leads an active research group at Caltech dedicated to simulating chemical and physical systems at the level of many-particle quantum mechanics. His group has welcomed numerous researchers including Kasra Hejazi, Zuxin Jin, Zhihao Cui, Ke Liao, Henrik Larsson, and Wenyuan Liu. He teaches courses in Physical Chemistry (Ch 21 abc) and Advanced Quantum Chemistry (Ch 225), contributing significantly to theoretical chemistry education at Caltech.
Chang Hyun Park is an Assistant Professor at the Department of Information Technology, Uppsala University, where he is part of the Uppsala Architecture Research Team. His research focuses on computer architecture with emphasis on memory systems, virtualization, and system software optimization. Dr. Park completed his doctoral studies at KAIST (Korea Advanced Institute of Science and Technology) in South Korea, where he was advised by Professor Jaehyuk Huh. Prior to his current position, he served as a post-doctoral researcher at Uppsala University working with Professor David Black-Schaffer. Dr. Park's research spans several critical areas in computer architecture and systems: Virtual memory systems and address translation mechanisms Cache hierarchy optimization and memory systems design Support for non-volatile memory and heterogeneous memory systems Virtualization technology and optimizations for cloud environments High-speed I/O device integration and accelerator support His publication record demonstrates a consistent focus on improving memory system performance, particularly in virtualized environments. Over the past decade, his work has evolved from fundamental virtual memory optimizations to addressing challenges in emerging memory technologies and large-scale system architectures. Recent publications show increasing emphasis on heterogeneous memory systems, graph processing workloads, and hardware-software co-design approaches. Dr. Park actively collaborates with researchers at Uppsala University, particularly with Professor David Black-Schaffer, and maintains connections with his alma mater KAIST. His work appears regularly in top-tier computer architecture conferences including ISCA, MICRO, ASPLOS, and MEMSYS.
