جست‌وجوی استاد و پژوهشگر

William M. Jones Jr.مشاهده پروفایل

استاد

• High Performance Computing (HPC)
• Fault Tolerance
• Resilience Engineering
• +۵ مورد دیگر

Dr. William M. Jones Jr. is a Professor in the Department of Computing Sciences at Coastal Carolina University (CCU) since 2017. He concurrently serves as a Guest Scientist at Los Alamos National Laboratory (LANL) and is the founder of the LANL-CCU Collaboration initiative, established in 2007. His roles include HPC Visiting Scholar/Sabbatical at LANL (2025–present) and Guest Scientist at LANL (2023–present). Former positions include Department Chair of Computing Sciences at CCU (2012–2018) and Assistant Professor at the U.S. Naval Academy (2006–2008). Education: Ph.D. & M.S. in Computer Engineering (2005, 2000, Clemson University); B.S. in Computer Engineering (1999, Clemson University); B.A. in Spanish (2017, Coastal Carolina University). Research focuses on resilience and fault tolerance in HPC systems, including soft error mitigation, parallel computing optimization, and applied machine learning. He leads collaborative projects with LANL, emphasizing high-performance computing and student research engagement. Key contributions include the LANL-CCU partnership, yielding numerous publications and external funding since 2007. Articles highlight advancements in HPC resilience, machine learning applications, and fault tolerance, with recent trends emphasizing spatio-temporal modeling and statistical frameworks for system reliability. His work also extends to language pedagogy, with contributions to Spanish as a foreign language teaching methodologies. Advising and grants: Directs student researchers through the LANL-CCU initiative and has secured external funding for collaborative projects. Grants and partnerships focus on advancing HPC resilience and educational outreach in STEM. Labs/Teams: Co-leads the LANL-CCU Collaboration, fostering interdisciplinary research between academia and national labs. Active in the Ultrascale Systems Research Center (since 2014) and previously in the National Security Education Center at LANL (2019–2023).

Salim Ullahمشاهده پروفایل

پژوهشگر

• Approximate Computing
• FPGA-Based Hardware Accelerators
• Embedded Systems Design
• +۳ مورد دیگر

Salim Ullah is a researcher in the Department of Embedded Systems at Ruhr University Bochum. His work focuses on FPGA-based approximate computing, hardware accelerators, and embedded systems design. He leads the Embedded Systems Team, contributing to advancements in reconfigurable logic and neuromorphic computing. Research Interests: Approximate arithmetic circuits, FPGA design methodologies, neural network implementation on FPGAs Key Projects: AxOCS (approximate operator scaling), AxOMaP (mathematical programming for arithmetic operators), AxOSpike (spiking neural networks for operator design) Publications (2024-2020) highlight innovations in error resilience, quantization techniques, and hardware-software co-design. Collaborations include work on RISC-V emulation (NvMISC), energy-efficient multipliers, and embedded AI acceleration frameworks.

Sotirios Xydisمشاهده پروفایل

استادیار

• Hardware/Software Co-design
• High Level Synthesis
• Hardware Accelerators
• +۷ مورد دیگر

Sotirios Xydis is an Assistant Professor in the Division of Computer Science at the School of Electrical and Computer Engineering, National Technical University of Athens (NTUA), with prior faculty appointment at Harokopion University of Athens (2020-2023). He maintains ongoing collaboration with the Institute of Communication and Computer Systems (ICCS) since 2014 and previously served as an engineer at HEDNO (2015-2018) and postdoctoral researcher at Politecnico di Milano (2011-2013). His academic credentials include: BSc in Electrical and Computer Engineering, NTUA (2005) MSc in Techno-Economic Systems, NTUA (2011) PhD in Electrical and Computer Engineering, NTUA (2011) Dr. Xydis specializes in hardware/software co-design , energy-efficient hardware acceleration , and memory management for embedded and cloud-edge systems. His research bridges low-power circuit design , heterogeneous architecture optimization , and resource management frameworks , with particular emphasis on AI workloads and serverless infrastructures. Current projects target Edge AI accelerators (CONVOLVE), disaggregated memory systems, and LLM inference optimization through hardware-aware algorithms. Analysis of his 2023-2025 publications reveals three dominant trends: (1) Energy-efficient hardware accelerators for Edge AI using approximate computing techniques, (2) Memory/resource management innovations for disaggregated serverless environments, and (3) GPU/FPGA optimization for LLM inference through dynamic frequency scaling and predictive throttling. These works consistently address the power-performance tradeoffs in heterogeneous computing systems. His scientific recognition includes: Best Paper Award, IEEE/NASA/ESA AHS (2007) Best Paper Award, ACM PARMA (2013) Best Paper Award, ACM Computing Frontiers (2020) Hipeac Award at DAC (2019, 2020) Dr. Xydis has secured over 15 European/national research grants as Principal Investigator and Technical Coordinator, focusing on hardware acceleration frameworks and energy-efficient computing. His advising encompasses graduate research in hardware design and optimization, though specific student names aren't publicly listed. Current projects include CONVOLVE for Edge AI and CollectiveHLS for collaborative hardware synthesis. He is a core member of NTUA's Microelectronics Laboratory (Microlab) and collaborates with ICCS on hardware acceleration projects. His team develops frameworks like CollectiveHLS and throttLL'eM, with active participation in DATE, DAC, and ISCA conference communities.

Sriram Krishnamoorthyمشاهده پروفایل

استاد پژوهشی

• Parallel Programming Models
• Fault Tolerance
• High-Performance Computing
• +۶ مورد دیگر

Sriram Krishnamoorthy is a Research Professor at Washington State University's School of Electrical Engineering & Computer Science and a research scientist at Pacific Northwest National Laboratory (PNNL), where he serves as the System Software and Applications Team Leader in PNNL's High Performance Computing group. Dr. Krishnamoorthy earned his B.E. from the College of Engineering, Guindy in Chennai, India, and his M.S. and Ph.D. degrees from The Ohio State University. He is a senior member of the Institute of Electrical and Electronics Engineers. His research focuses on parallel programming models, fault tolerance, and compile-time/runtime optimizations for high-performance computing. He has made significant contributions in areas including: Fault tolerance techniques that minimize rollback during failures Dynamic load balancing for irregular parallel applications Compiler and runtime optimizations for HPC applications GPU programming and heterogeneous computing Quantum chemistry simulations and quantum computing Dr. Krishnamoorthy's publications span computational science, high-performance computing, and quantum chemistry. His recent work shows strong trends toward quantum computing applications, fault tolerance in large-scale systems, and optimization of computational chemistry methods. He has developed techniques for density matrix quantum circuit simulation, floating-point error analysis, and scalable execution of coupled-cluster models. His scientific achievements have been recognized with several prestigious awards: Best Paper Award at International Conference on High Performance Computing (HiPC'03) Best Paper Award at International Parallel and Distributed Processing Symposium (IPDPS'04) U.S. Department of Energy Early Career award (2013) PNNL's Ronald L. Brodzinski Award for Early Career Exceptional Achievement (2013) The Ohio State University's Outstanding Researcher award (2008) Dr. Krishnamoorthy has advised numerous graduate students and collaborated extensively with researchers across computational science domains. His work on the NWChem project demonstrates significant grant funding and large-scale collaborative research efforts in computational chemistry. He leads research efforts in PNNL's High Performance Computing group, focusing on system software and applications development for next-generation supercomputing platforms.

• Synaptic transmission
• Optical Microscopy
• Computational neuroscience
• +۵ مورد دیگر

Robin Angus Silver is Professor of Neuroscience at University College London (UCL), a Wellcome Trust Principal Research Fellow, and Fellow of the Royal Society. He has held leadership roles since 2011 and is renowned for groundbreaking work in synaptic transmission, neural computation, and neuroinformatics. Education: B.Sc. in Physical Sciences (1st Class Hons), Coventry Polytechnic (1986) Ph.D. in Physiology, UCL (1990) Dr. Silver's research focuses on information processing in cerebellar and neocortical circuits. He discovered fundamental properties of central excitatory synapses, elucidated how neurons perform arithmetic operations, and pioneered tools like NeuroConstruct and NeuroML for 3D neuronal modeling. His development of high-speed two-photon microscopy with acousto-optic lenses revolutionized in vivo imaging. His work spans synaptic physiology, computational modeling, and neuroinformatics infrastructure. He has contributed to open-source platforms like OpenSourceBrain, enabling browser-based visualization and simulation of neural models. Awards include Royal Society Fellowship (2017), Wellcome Trust Principal Research Fellowships (2011, 2016), and ERC Advanced Investigator Award (2011). Scientific Awards Fellow of the Royal Society (2017) Wellcome Trust Principal Research Fellowship (2011, 2016 renewal) European Research Council Advanced Investigator Award (2011) Hungarian Academy of Sciences Distinguished Guest Scientist Fellowship (2012) Multiple Wellcome Trust Senior/Principal Research Fellowships Wellcome Trust Research Career Development Fellowship (1996) Dr. Silver has organized international workshops including OpenSourceBrain meetings and INCF Congress events. He serves on steering committees for neuroinformatics initiatives and evaluation panels for funding bodies like the Wellcome Trust and US BRAIN Initiative.

• Digital Signal Processing (DSP)
• Field-Programmable Gate Arrays (FPGA)
• Machine Learning Hardware Acceleration
• +۱۳ مورد دیگر

Gian Carlo Cardarilli is a researcher specializing in digital hardware design and machine learning acceleration. His work focuses on FPGA implementations, Residue Number System (RNS) architectures, and reconfigurable computing for applications in wireless communication, edge AI, and fault-tolerant systems. Key collaborations with institutions like IEEE and ACM through publications. Active in translating theoretical algorithms into practical hardware solutions for real-time systems. Research interests include: Optimizing deep learning models for heterogeneous platforms. Developing radiation-hardened memory systems. Creating energy-efficient signal processing architectures. Advancing reconfigurable functional units for embedded processors. His article analyses span fields like Quantum Cellular Automata , Variable Fractional Delay Filters , and RNS-Based Position Estimation , reflecting a trend toward adaptive, low-power, and domain-specific hardware.

Ramtin Zandمشاهده پروفایل

استادیار

• Hardware Design for Machine Learning Systems
• Neuromorphic Computing
• Emerging Nanoscale Electronics
• +۷ مورد دیگر

Ramtin Zand is an Assistant Professor in the Department of Computer Science and Engineering at the University of South Carolina's Molinaroli College of Engineering and Computing. His research focuses on hardware design for machine learning systems, neuromorphic computing, emerging nanoscale electronics (e.g., spintronic devices), and energy-efficient VLSI circuits. He leads the ICAS Lab, which explores reconfigurable architectures and low-power computing solutions. Education: Ph.D., Computer Engineering, University of Central Florida (2019) M.S., Electrical Engineering, Sharif University of Technology (2012) Research Interests: Dr. Zand’s work spans hardware-software co-design for AI, neuromorphic systems, and novel devices like MRAM and memristors. He emphasizes practical applications such as manufacturing anomaly detection, edge computing, and energy-efficient neural network deployment. Recent Trends in Articles: His publications emphasize hybrid PIM architectures, LLM-driven hardware design, and neuromorphic edge systems. Themes include optimizing communication efficiency, leveraging memristive crossbars, and bridging vision transformers with embedded platforms. Grants/Funding: Funded by AFRL for smart manufacturing projects ONR grants for perception systems research NSF support for in-memory computing Labs/Teams: The ICAS Lab collaborates on projects such as neuromorphic accelerators and low-power sensor systems. Recent milestones include DAC 2025 awards and CVPR 2025 demonstrations.

Chunhong Chenمشاهده پروفایل

استاد

• Digital Integrated Circuit Synthesis
• VLSI Computer-Aided Design
• High-Performance Low-Power Systems
• +۱ مورد دیگر

Dr. Chunhong Chen is a Professor in the Department of Electrical and Computer Engineering at the University of Windsor's Faculty of Engineering. He holds a PhD from Fudan University and is a P. Eng of Ontario and IEEE Senior Member. His research focuses on digital integrated circuit synthesis, VLSI CAD, high-performance low-power systems, and nanoelectronic circuit design. Education: PhD, Fudan University Recent work includes hybrid signal probability estimation methods, statistical delay modeling for nanoelectronics, and area-efficient cryptographic circuit design using hybrid SET-MOS technology. His research emphasizes practical applications in low-power systems and nanoscale device optimization. Dr. Chen's publications demonstrate expertise in both foundational theory and applied engineering solutions. He leads the Research Centre for Integrated Microsystems (RCIM), focusing on advanced microsystem integration challenges.

Michael Huangمشاهده پروفایل

استاد

• High-Performance Computer Architecture
• Processor Microarchitecture
• Non-Von Neumann Computing
• +۴ مورد دیگر

Michael Huang is a Professor in the Department of Electrical and Computer Engineering and Computer Science at the University of Rochester's Hajim School of Engineering & Applied Sciences. He holds a PhD from the University of Illinois at Urbana-Champaign (2002) and has been faculty since 2002. His research focuses on high-performance computing, including processor microarchitecture, energy-efficient design, and non-von Neumann systems like Ising machines. He has received the NSF CAREER Award and is a member of ISCA/HPCA Hall of Fame. Education: BS (Tsinghua University, 1994), MS/PhD (UIUC, 1999/2002). Research emphasizes co-design of device, circuit, and system technologies. Notable projects include multi-chip Ising machine architectures and optical interconnects. Collaborates with IBM Research on future processor concepts. Active in top conferences like ISCA, HPCA, and ICLR. Key achievements include pioneering work on Ising machines for combinatorial optimization, energy-efficient architectures, and secure branch predictors. His work bridges traditional computer architecture with emerging technologies like optics and mixed-signal circuits.

• Field Programmable Gate Arrays
• Computer Architecture
• Artificial Intelligence hardware design
• +۳ مورد دیگر

Dr. Zainab Aizaz is a Research Fellow at the School of Engineering and Informatics , University of Sussex, specializing in Artificial Intelligence hardware design and Field Programmable Gate Arrays (FPGA) . Her work focuses on creating energy-efficient and high-performance hardware solutions for AI applications, particularly through innovative pipelined vector processor architectures extending RISC-V open-source frameworks. Her research interests include: Approximate computing for neural networks Hardware acceleration of machine learning Computer architecture optimization Energy-efficient FPGA design Medical imaging applications using AI Signal integrity in nanoscale circuits Dr. Aizaz's recent publications highlight her work on: Spiking neural network acceleration (2025) Approximate multiplier architectures (2022-2024) Hardware-software co-design for edge computing (2023) Cognitive radio antenna optimization (2016) Contact: Z.Aizaz@sussex.ac.uk

Mark Horowitzمشاهده پروفایل

استاد

• High-Performance Digital Systems
• VLSI Circuit Design
• Microprocessor Architecture
• +۷ مورد دیگر

Mark Horowitz holds the Fortinet Founders Chair in Electrical Engineering and is the Yahoo! Founders Professor in Stanford University's School of Engineering. He also serves as Professor of Computer Science. His career spans over four decades, with foundational contributions to microprocessor design, high-speed link architectures, and computational photography innovations like the Lytro camera. Education: PhD in Electrical Engineering, Stanford University (1984) MS in Electrical Engineering, MIT (1978) BS in Electrical Engineering, MIT (1978) Research Interests: His work bridges EE and CS with interdisciplinary focus on: Agile hardware design methodologies for VLSI systems High-speed signaling and memory interfaces (e.g., Rambus technology) Reconfigurable computing architectures (e.g., CGRA-based accelerators) Applications in computational biology and molecular systems Recent Directions: Recent publications emphasize energy-efficient accelerators for machine learning, memory subsystem innovations, and compiler-driven hardware design frameworks like AHA! His work on Onyx and Opal architectures demonstrates leadership in sparse tensor computation hardware. Labs & Teams: Leads the Stanford VLSI Research Group and AHA! initiative. Collaborations include work with Prof. Marc Levoy on computational imaging and partnerships with industry on memory interface standards.

Gwan Choiمشاهده پروفایل

دانشیار

• Fault-tolerance
• Verification simulation
• High-performance VLSI circuits
• +۷ مورد دیگر

Gwan Choi is an Associate Professor in the Department of Electrical and Computer Engineering at Texas A&M University, affiliated with the College of Engineering. His research focuses on fault-tolerance, verification simulation, high-performance VLSI circuits, radiation testing, design for dependability, and software engineering. He holds a Ph.D., M.S., and B.S. in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign (1988–1994). Education: Ph.D., Electrical and Computer Engineering, University of Illinois at Urbana-Champaign (1994) M.S., Electrical and Computer Engineering, University of Illinois at Urbana-Champaign (1989) B.S., Electrical and Computer Engineering, University of Illinois at Urbana-Champaign (1988) Research Interests: Dr. Choi’s work spans fault-tolerant computing, radiation-hard electronics, and high-performance VLSI design. He has contributed to LDPC decoding architectures, MIMO communication systems, and energy-efficient circuit designs. His research emphasizes practical implementations in aerospace and embedded systems. Awards: National Science Foundation (NSF) Career Award (1997) Labs & Activities: He has collaborated with NASA Langley Research Center as a visiting scientist and contributed to industry through roles at Cray Research and Tandem Computers. His work bridges academic research with real-world applications in fault tolerance and low-power systems.

• Computational Science
• Atmospheric Modeling
• High-Performance Computing
• +۳ مورد دیگر

Maynard Christopher is a researcher affiliated with the University of Reading, contributing significantly to computational science and atmospheric modeling. His work focuses on advancing numerical methods for weather and climate models, particularly through the LFRic project, and exploring quantum computing applications. He has collaborated on projects addressing high-performance computing challenges, scalability, and reproducibility in scientific workflows. Research interests include atmospheric dynamics, mixed-precision arithmetic optimization, and exascale computing strategies for climate simulations. His publications emphasize improving the efficiency and portability of dynamical cores in numerical weather prediction models. Recent work includes contributions to benchmarking standards for HPC systems and acceleration techniques for hybrid multi-core architectures. While no formal awards are listed, his impactful publications highlight leadership in computational climate science and quantum algorithm development.

• Photonic Integrated Circuits
• Silicon Photonics
• Nanophotonics
• +۴ مورد دیگر

Zheng Wang is an Associate Professor at the State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences (since May 2023). Previously, he held roles including Assistant Professor (2022–2023), Deputy Director (2021–2022), and R&D Project Leader at IMEC (2018–2021). He earned his Ph.D. in Materials Science and Engineering from The University of Texas at Austin (2017) and a B.S. in Mathematics and Physics from Tsinghua University (2012). His research focuses on Photonic Integrated Circuits , Silicon Photonics , and Nanophotonics , with emphasis on graphene-based devices, optical interconnects, and photonic computing. Key areas include graphene electro-absorption modulators, silicon nitride frequency comb lasers, and optical logic circuits using microdisk resonators. Recent work highlights include: Development of high-efficiency graphene modulators for visible wavelengths Creation of ultra-dense III-V-on-silicon nitride frequency comb lasers Design of microdisk-based optical full adders for photonic computing Zheng Wang has authored over 40 publications in high-impact journals like IEEE J. Quantum Electronics , Advanced Functional Materials , and Optics Letters . His research bridges nanophotonics with practical applications in optical communications and computing.

Alexandru Palerمشاهده پروفایل

دانشیار

• Quantum Computing
• Quantum Software
• Quantum Circuit Compilation
• +۲ مورد دیگر

Alexandru Paler serves as an Associate Professor in the Department of Computer Science at Aalto University, Finland, where he leads research in quantum software development. His work focuses on designing compilers and optimization frameworks for quantum circuits, with emphasis on quantum error correction implementation and fault-tolerant quantum computing systems. Based in Espoo at Konemiehentie 2, he maintains active research collaborations through the university's quantum computing initiatives. Dr. Paler's research spans quantum circuit compilation, quantum error correction (particularly surface codes and QLDPC codes), and quantum software optimization. His team develops high-performance quantum compilers for neutral atom architectures and modular superconducting systems, addressing critical challenges in resource estimation and fault tolerance. The Quantum Operating Systems (QUANTUM) research group he contributes to explores scalable quantum software frameworks that bridge theoretical algorithms with practical hardware constraints, with significant work on graph-state compilation and reinforcement learning for circuit optimization. Analysis of his 15 most recent publications (2023-2025) reveals concentrated efforts in quantum compiler design, error correction scalability, and hardware-aware quantum software. Key trends include machine learning applications for decoder optimization, novel approaches to measurement-free error correction, and queuing theory models for fault-tolerant circuit analysis. His work consistently addresses the practical barriers to large-scale quantum computing through compiler innovations and resource-efficient circuit design. Dr. Paler actively participates in the Quantum Operating Systems (QUANTUM) research group within Aalto's Department of Computer Science, focusing on Algorithms and Theoretical Computer Science. This team develops quantum software infrastructure for next-generation quantum hardware, with current projects including Pandora (ultra-large-scale circuit compilation), quantum circuit caching mechanisms, and standardized cell approaches for neutral atom systems. Their research directly supports the transition from theoretical quantum algorithms to executable, error-resilient quantum programs.