Nima Honarmand is an Assistant Professor in the Department of Computer Science at Stony Brook University, where he co-directs the Computer Architecture Stony Brook (COMPAS) Lab . His research focuses on computer system design , particularly parallel computer architecture and operating systems . Education : Ph.D. in Computer Science from University of Illinois at Urbana-Champaign under Josep Torrellas. His work addresses challenges in deterministic replay of parallel programs to simplify debugging on multi-processor systems. Current research explores memory fencing, consistency models, and architectural extensions for reproducibility. Recent publications span conferences like ASPLOS, ISCA, PACT, and POPL, with emphasis on parallelism constraints , memory hierarchy optimization , and fault-tolerant systems . Awards include Best Paper at PACT 2011 and Best Paper Candidate at VTS 2007 . Teaching : Courses include Computer Architecture (CSE 502) and Operating Systems (CSE 306/CSE 506). Email : nhonarmand@cs.stonybrook.edu
Antonio Calomarde Palomino is an Associate Professor at the Department of Electronic Engineering, Polytechnic University of Catalonia (UPC), located at the Higher Technical School of Industrial Engineering of Barcelona. He holds a B.S. in Telecommunications Engineering (UPC, 1986), an M.S. in Electronic Engineering (Universitat Autònoma de Barcelona, 1993), and a Ph.D. in Electronic Engineering (UPC, 2007) with honors. His research focuses on low-power/high-performance digital circuits and soft-error resilient designs, addressing challenges in semiconductor technology and radiation-hardened electronics. Key research areas include FinFET-based memory cells, RRAM modeling, and radiation mitigation strategies for advanced nanoelectronics. He contributes to the High Performance Integrated Circuits and Systems Design (HIPICS) Group, advancing circuit design methodologies and educational initiatives such as integrating autonomous vehicle systems into undergraduate curricula. His work bridges theoretical advancements with practical applications in automotive electronics and embedded systems. Publications span topics from memristor-based associative memory to approximation techniques in object detection systems, reflecting a balance between fundamental research and applied engineering. His recent work emphasizes variability-aware design and energy-efficient architectures, as seen in 2023-2024 studies on RRAM models and automotive case studies. Calomarde actively organizes academic events like the 2022 ETS conference and develops educational materials for digital electronics and audiovisual systems courses. His contributions to both technical research and pedagogical innovation solidify his role as a key figure in electronic engineering education and innovation.
Dr Tomasz Kazmierski is an Associate Professor in the Department of Electronics and Electrical Engineering at the University of Southampton. His research focuses on hardware security, VLSI design, and energy-efficient computing. He leads projects such as the EPSRC-funded 'Next Generation Energy-Harvesting Electronics' and 'Event-based parallel computing (POETS)'. Current Projects: Event-based parallel computing (EPSRC) Next Generation Energy-Harvesting Electronics (EPSRC) Supervision: PhD students Peiyao Sun, Xuan Ji, and Haosen Yu Research Interests: Hardware Security & Trojan Resilience Approximate Computing Ultra-Low Power Circuits Neural Network Accelerators Recent work emphasizes secure design of neural network hardware, optimization of VLSI interconnects, and aging-aware circuit techniques. His publications span conferences like IEEE ISCAS and IEEE AsianHOST, addressing topics from fault-tolerant signal processing to energy-harvesting systems.
Dr. Chang Y Choo is a Professor of Electrical Engineering at San José State University, where he also serves as Director of the AI/ML FPGA/DSP Systems Laboratory. His academic career spans over three decades, with previous positions at Worcester Polytechnic Institute and industry experience at Altera Corp. (now Intel). Dr. Choo maintains an active research program focusing on hardware acceleration for AI and signal processing applications, with particular emphasis on FPGA-based implementations for real-world systems. Dr. Choo's educational background includes: Ph.D. in Computer and Systems Engineering, Rensselaer Polytechnic Institute (1986) M.S. in Operations Research and Statistics, Rensselaer Polytechnic Institute (1982) B.S./M.S. in Engineering, Seoul National University, Korea Dr. Choo's research interests center on the intersection of hardware design and artificial intelligence. His work focuses on implementing computer vision, deep learning, and digital signal processing algorithms on specialized hardware platforms including FPGAs, GPUs, and custom ASICs. Current projects include developing real-time illumination/view-independent object recognition systems for autonomous vehicles, wideband acoustic echo cancellation for wearable technology, and FPGA-based accelerators for medical imaging applications. His research bridges theoretical algorithm development with practical hardware implementation constraints. Analysis of Dr. Choo's recent publications reveals a clear trajectory toward increasingly sophisticated hardware-accelerated AI systems. His work has evolved from foundational research in digital signal processing and image compression to cutting-edge applications of deep learning on specialized hardware. Recent publications demonstrate expertise in implementing CNN architectures on FPGAs, developing metabolic syndrome prediction models, and creating food object detection systems using transformer models. This progression reflects the broader field's shift toward hardware-aware AI development. Dr. Choo's significant scientific contributions include multiple patents that have advanced the state of the art in several domains: U.S. Patent No. 9,025,763 (2015): 'Apparatus and Method for cancelling wideband acoustic echo' U.S. Patent Nos. 7,058,675 (2006) and 7,124,161 (2006): 'Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices' U.S. Patent Nos. 5,943,096 (1999) and 6,621,864 (2003): 'Motion vector based frame insertion process' U.S. Patent Nos. 5,832,131 (1998) and 5,991,455 (1999): 'Hashing-based vector quantization' U.S. Patent No. 5,587,710 (1997): 'Syntax based arithmetic coder and decoder' Throughout his career, Dr. Choo has been actively involved in both academic and industry collaborations. He has served as a technical consultant for numerous Silicon Valley companies including National Semiconductor (now Texas Instruments), Philips Semiconductor, Skybox Imaging (acquired by Google), Novariant (now AgJunction), and Ricoh Innovations. His industry experience informs his teaching approach, which emphasizes practical implementation considerations alongside theoretical foundations. Dr. Choo has also served as an expert witness in intellectual property court cases involving audio and video compression algorithms and FPGA hardware. Dr. Choo directs the FPGA/DSP AI/DL Laboratory at San José State University, which focuses on developing hardware-accelerated solutions for real-time AI applications. The lab maintains strong connections with Silicon Valley technology companies and provides students with hands-on experience in cutting-edge hardware design methodologies. Current research directions include autonomous vehicle navigation systems, medical imaging applications, and edge AI deployment strategies.
Jari Nurmi is a Full Professor at Tampere University's Faculty of Information Technology and Communication Sciences, Department of Electrical Engineering. With over 30 years of experience in academia and industry, he specializes in communications engineering, positioning technologies, embedded systems, and reconfigurable computing. His roles include Director of the national DELTA doctoral training network, head of the European Joint Doctorate A-WEAR program, and coordinator of APROPOS MSCA ITN. He has supervised 32 PhD dissertations and over 160 MSc theses. His research focuses on embedded processor systems, reconfigurable computing, approximate computing, and positioning technologies (especially GNSS receiver architectures). He is actively involved in organizing international conferences like IEEE Nordic Circuits and Systems Conference and serves on editorial boards of three journals. His recent work includes advancements in neural network inference on FPGAs, 5G NR localization, and energy-efficient edge AI for autonomous systems. Nurmi has been recognized for his contributions to conference organization and innovation. His publications span topics such as FPGA optimization, GNSS error modeling, and machine learning for healthcare applications. He leads initiatives like the EWOk dataset compression framework and the Hard SyDR benchmarking environment for GNSS algorithms.
Mikhail Dorojevets is an Associate Professor in the Department of Electrical and Computer Engineering at Stony Brook University , New York. His research focuses on parallel computer architecture, high-performance systems design, and superconductor processors . He has contributed extensively to RSFQ (Rapid Single Flux Quantum) and RQL (Resonator Quantum Logic) technologies for ultra-high-speed computing systems. Key areas of expertise include: Superconducting electronics for energy-efficient computing High-frequency (GHz-scale) processor design Architectures for parallel and wave-pipelined systems FPGA-based hardware acceleration for network processing His work spans both theoretical and applied aspects, including: Design of RSFQ arithmetic logic units (ALUs) and multipliers Development of 20+ GHz microprocessor prototypes Optimization of energy consumption in superconductor-based systems Publications emphasize advancements in: Superconductor VLSI implementation High-performance storage architectures Multi-port register file designs Integration of satisfiability solvers with hardware
Christos Papachristou, PhD is a Professor in the Department of Electrical, Computer, and Systems Engineering at the Case School of Engineering , Case Western Reserve University. His academic career spans over four decades since earning his PhD in Electrical Engineering & Computer Science from Johns Hopkins University in 1975. Prof. Papachristou's research focuses on Embedded Systems Design , Quantum Computing Architectures , Reconfigurable Systems/FPGAs , and Hardware Security . His work addresses critical challenges in fault-tolerant systems , secure system design , and high-level synthesis . Notable contributions include innovations in radiation-hardened SRAM designs , hardware trojan detection , and quantum computing infrastructure . Key Achievements: Recipient of the Albert Nelson Marquis Lifetime Achievement Award (2019) IEEE Best Paper Award for Cognitive Communications for Aerospace Applications (2019) Invited NATO Summer School Lecturer (2008) in Spain/UK and Cleveland His publications reflect expertise in circuit reliability , embedded system security , and quantum computing . Recent work emphasizes electromigration mitigation and reconfigurable architecture kernels . Prof. Papachristou collaborates extensively on projects funded by NSF, DoD, and industry partners. Teaching specialties include Parallel Computer Architectures , Configurable Devices , and Quantum Computing , reflecting his dual focus on theoretical innovation and practical implementation in advanced technologies.
Miljana L. Milić is a Full Professor at the Faculty of Electronics, University of Niš, Serbia, Department of Electronics. She has been an integral part of this institution since earning her degrees and advancing through academic ranks, culminating in her appointment as full professor in 2024. Education: PhD in Electronics, Faculty of Electronics, University of Niš (2009) Master’s in Electronics, Faculty of Electronics, University of Niš (2005) Bachelor’s in Electronics, Faculty of Electronics, University of Niš (2001) Her research interests span a broad spectrum of electronics engineering, with emphasis on VLSI design, analog and digital circuit diagnosis, cryptographic hardware security, timing analysis under aging, and performance optimization in neural prediction systems. She applies simulation, statistical methods, and AI techniques to solve complex problems in electronic systems design and reliability. The analysis of her recent publications reveals a strong focus on hardware-level innovation, including secure cryptographic cells, fault diagnosis in analog circuits, performance modeling under fading and shadowing, and timing degradation in VLSI systems. Her work bridges theoretical analysis with practical implementation in electronic design and communication systems. She leads the Laboratory for Design of Electronic Processes, Circuits and Automatic Control Systems, and is currently involved in one national research project. Her contributions include over 10 journal publications in high-impact venues. Scientific Contributions: Head of Laboratory for Design of Electronic Processes, Circuits and Automatic Control Systems Active participant in national research projects Author/co-author of 10+ journal papers with impact factor She mentors students through research supervision and contributes to academic leadership within her department. Her work continues to influence both academic research and practical applications in electronic systems engineering.
Dr. Teresa Maria Canavarro Menéres Mendes de Almeida is an Assistant Professor at the Department of Electrical and Computer Engineering, Instituto Superior Técnico (University of Lisbon), and a researcher at INESC-ID. She specializes in circuit theory, signal processing, and biosensor technologies. Her teaching focuses on core electrical engineering courses such as Circuit Analysis, Analog/Digital Filters, and Electronics fundamentals, for which she has received multiple teaching excellence awards from the IST Pedagogical Council (2013-2019). Her research interests span resistive circuits, magnetoresistive biosensors, and biochip-based microsystems. She has developed educational materials like problem sets and lecture slides on filters and circuits, alongside applied work in biomedical embedded systems and sensor modeling. Collaborations include projects on portable biosensing platforms and noise analysis in biochip elements. Notable achievements include a series of teaching excellence awards highlighted for courses like 'Circuit Theory and Fundamentals of Electronics' and 'Analog and Digital Filters.' Her work bridges theoretical circuit analysis with practical applications in biomedical engineering and digital signal processing.
Stefania Perri is an Associate Professor of Electronics at the Department of Mechanical, Energy and Management Engineering (University of Calabria, Italy). She holds a PhD in Electronics Engineering from the University of Reggio Calabria and has been actively involved in research and teaching since 1996. Research Interests include: Quantum-Dot Cellular Automata (QCA) - Invented an efficient QCA adder design methodology with three theorems. Image Processing - Developed memory architectures for aerospace applications and stereovision systems on FPGA. Low-Power Circuits - Designed novel SRAM cells and validated sub-threshold logic models. High-Speed Arithmetic - Holds US Patent 7,016,932 B2 for carry propagation optimization. Scientific Contributions: Over 120 publications including 58 journal papers, 48 conference proceedings, 3 patents International Collaborations with University of Rochester (USA) and Idaho State University Awards: Best Paper Awards at CENICS 2016 and CENICS 2010 Bronze Leaf Certificate at IEEE PRIME'06 Multiple Invited Paper recognitions
Kimmo Järvinen serves as a Visiting Professor in the Department of Electronics and Nanoengineering at Aalto University, actively contributing to the Adjunct Professor Asokan N. research group. His institutional affiliation centers on advancing cryptographic solutions for modern security challenges within the university's engineering ecosystem. His research spans cutting-edge cryptography with emphases on hardware security, embedded systems protection, and efficient algorithm design. Järvinen specializes in elliptic curve cryptography implementations, side-channel attack countermeasures, and hardware acceleration techniques for resource-constrained environments like IoT devices. His work bridges theoretical cryptographic constructs with practical hardware deployment, prioritizing both security robustness and computational efficiency in real-world applications. Analysis of his 2014-2018 publications reveals consistent innovation in finite field arithmetic optimization, scalar multiplication efficiency, and physical attack resistance. His research trajectory demonstrates increasing focus on IoT security integration, with significant contributions to FPGA-based cryptographic accelerators and lightweight implementations for constrained devices. Key thematic threads include endomorphism exploitation for performance gains, binary field operation optimization, and protocol-level privacy enhancements for mobile networks. Dr. Järvinen operates within Adjunct Professor Asokan's cybersecurity research collective, which explores hardware-software co-design approaches to cryptographic system vulnerabilities. This team environment fosters cross-disciplinary collaboration on securing next-generation communication infrastructures and embedded platforms.
Dr. Silviu Filip is a Chargé de Recherche (junior researcher) at INRIA Rennes - Bretagne Atlantique, affiliated with the Taran team since October 2018. Previously, he held postdoctoral positions at INRIA (2018) and the University of Oxford's Numerical Analysis group (2017-2018). He obtained his PhD in Computer Science from École Normale Supérieure de Lyon in 2016, focusing on algorithmic aspects of digital filter design. His research spans: Approximation theory and numerical computations Computer arithmetic and hardware acceleration Convex/integer optimization Efficient deep learning computations Digital filter design and FPGA implementations Research trends from publications show consistent focus on numerical optimization techniques applied to hardware-efficient deep learning, including mixed-precision training (70% of recent papers), FPGA acceleration (40%), and novel quantization methods (30%). Awards: Best Paper Award at IEEE Symposium on Computer Arithmetic (ARITH-30, 2023) PhD Supervision: Cédric Gernigon (2020-present) Léo Pradels (2020-present) Sami Ben Ali (2022-present) Software Development: Leads multiple open-source projects including firpm (FIR filter design), MPTorch (mixed-precision training), srfloat (stochastic rounding), and contributes to Chebfun (numerical computing).
Professor Vincent Gaudet is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. He holds a Ph.D. (2003) and M.A.Sc. (1997) from the University of Toronto and a B.Sc. (1995) from the University of Manitoba. His research focuses on high-performance microelectronic circuits for information processing, including stochastic computing, error-correcting codes (LDPC/Turbo), and biomedical applications such as neural recording systems. He has held visiting roles at Tohoku University and Northeastern University, and has served as Chair of the IEEE Technical Committee on Multiple-Valued Logic (2016-2017). Education: B.Sc. (1995), M.A.Sc. (1997), Ph.D. (2003) in Electrical Engineering Editorial Roles: IEEE Transactions on Circuits and Systems, ISSCC Technical Editor His research interests span VLSI design, low-power circuits, biomedical instrumentation, and machine learning applications in medical imaging. He has pioneered FPGA implementations of stochastic decoders and AI-driven diagnostic tools for PET imaging. Notable awards include the Petro Canada Young Innovator Award (2009) and Engineering Society Teaching Excellence Award (2015). Teaching focuses on digital/analog circuit design (ECE 240/340/445/637), with contributions to the 8th edition of the textbook Microelectronic Circuits . He has held leadership roles including Department Chair (2016-2020) and Associate Chair for Undergraduate Studies (2013-2016). Grants & Labs: Active in microsystems design and biomedical engineering research groups Patents: Includes circuit design innovations for LDPC decoders and biomedical instrumentation
Andrew Boutros is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. His research focuses on reconfigurable computing architectures, FPGA design, and domain-specific acceleration for deep learning and datacenter workloads. He holds a PhD from the University of Toronto (2024) and has worked at Intel Labs and MangoBoost. Education: PhD, Electrical and Computer Engineering, University of Toronto, Canada (2024) MASc, Electrical and Computer Engineering, University of Toronto, Canada (2018) BSc, Electronics Engineering, German University in Cairo, Egypt (2016) Research Interests: Developing efficient FPGA architectures and CAD tools for reconfigurable hardware, domain-specific acceleration, and application/hardware co-design. Specific areas include 3D-stacked acceleration devices, graph neural network acceleration, and FPGA-based smart NICs for AI training. Publications: Over 30 papers in top venues like IEEE FPL, FCCM, and FPGA conferences, with 4 best paper awards. Recent work includes 3D-stacked architectures, graph neural network inference, and FPGA optimization for deep learning. Awards: Best Paper Award (FPT 2023) Best Paper Award (ICM 2021) Stamatis Vassiliadis Best Paper Award (FPL 2018) Advising/Grants: Currently accepting graduate students. Collaborations include 84 co-authors and industry partnerships with Intel and MangoBoost.
Dr. William M. Jones Jr. is a Professor in the Department of Computing Sciences at Coastal Carolina University (CCU) since 2017. He concurrently serves as a Guest Scientist at Los Alamos National Laboratory (LANL) and is the founder of the LANL-CCU Collaboration initiative, established in 2007. His roles include HPC Visiting Scholar/Sabbatical at LANL (2025–present) and Guest Scientist at LANL (2023–present). Former positions include Department Chair of Computing Sciences at CCU (2012–2018) and Assistant Professor at the U.S. Naval Academy (2006–2008). Education: Ph.D. & M.S. in Computer Engineering (2005, 2000, Clemson University); B.S. in Computer Engineering (1999, Clemson University); B.A. in Spanish (2017, Coastal Carolina University). Research focuses on resilience and fault tolerance in HPC systems, including soft error mitigation, parallel computing optimization, and applied machine learning. He leads collaborative projects with LANL, emphasizing high-performance computing and student research engagement. Key contributions include the LANL-CCU partnership, yielding numerous publications and external funding since 2007. Articles highlight advancements in HPC resilience, machine learning applications, and fault tolerance, with recent trends emphasizing spatio-temporal modeling and statistical frameworks for system reliability. His work also extends to language pedagogy, with contributions to Spanish as a foreign language teaching methodologies. Advising and grants: Directs student researchers through the LANL-CCU initiative and has secured external funding for collaborative projects. Grants and partnerships focus on advancing HPC resilience and educational outreach in STEM. Labs/Teams: Co-leads the LANL-CCU Collaboration, fostering interdisciplinary research between academia and national labs. Active in the Ultrascale Systems Research Center (since 2014) and previously in the National Security Education Center at LANL (2019–2023).
