جستجوی استاد راهنمای دانشگاهی

Gauri Joshiمشاهده پروفایل

دانشیار

• Distributed Machine Learning
• Federated Learning
• Stochastic Modeling
• +۷ مورد دیگر

Gauri Joshi is an Associate Professor in the Electrical and Computer Engineering (ECE) department at Carnegie Mellon University, with affiliate appointments in the Machine Learning Department and Robotics Institute. Her work focuses on system-aware algorithms for distributed machine learning, combining optimization, probability, and coding theory to address communication and computational constraints in edge networks. MIT Ph.D. in EECS (2016) IIT Bombay B.Tech/M.Tech in Electrical Engineering (2010) Research themes include federated learning with communication efficiency, erasure coding for non-linear computations, and reinforcement learning for heterogeneous queueing systems. She leads the Optimization, Probability and Learning (OPAL) lab , affiliated with the Parallel Data Lab (PDL), CyLab, and FLAME Center. Recent publications highlight advances in: federated fine-tuning with low-rank adaptation, robust PCA for model aggregation, privacy-preserving prediction mechanisms, and adaptive reinforcement learning for job dispatching systems. Her group has received 15+ paper awards across SIGMETRICS, MobiHoc, and NeurIPS workshops. Scientific recognition includes: IEEE Goldsmith Lecturer (2025), MIT Technology Review '35 Innovators Under 35' (2022), ONR Young Investigator Award (2023), NSF CAREER (2021), and ACM SIGMETRICS Best Paper (2020). She has advised 20+ graduate students, many now at tech giants like Google, Apple, and Meta. Service contributions span program co-chair roles (MLSys 2025), associate editorships (IEEE/ACM Transactions on Networking), and workshop organization (ICML, NeurIPS). Her NSF AI-EDGE Institute leadership (2021-present) drives next-generation intelligent edge networks for robotics and aerospace applications.

Khuzaima Daudjeeمشاهده پروفایل

استاد

• Distributed Systems
• Database Management
• Cloud Computing
• +۳ مورد دیگر

Khuzaima Daudjee is a Professor and David R. Cheriton Faculty Fellow in the Cheriton School of Computer Science at the University of Waterloo. His research focuses on systems-oriented problems at the intersection of systems and data management, particularly building large-scale systems, storage infrastructure in the cloud, and modern hardware applications. He leads projects in distributed database systems, elastic scaling, and resource optimization. His recent work includes Caerus (geo-replicated transactions), Tiresias (predictive storage), and MorphoSys (automatic physical design metamorphosis). Daudjee has chaired major conferences including ICDE 2026 and serves on editorial boards for VLDB, SIGMOD, and IEEE TKDE journals. His awards include ACM Distinguished Scientist and multiple best paper awards. Educational initiatives include developing distributed systems teaching materials and supervising graduate students across database and distributed systems domains. His industry collaborations involve cloud infrastructure optimization and scalable data processing frameworks.

• Computer Architecture
• Datacenter Systems
• Cloud-Native Server Architecture
• +۷ مورد دیگر

Babak Falsafi is a Full Professor at the School of Computer and Communication Sciences (IC) at EPFL, leading the Parallel Systems Architecture Laboratory (PARSA). He is a renowned expert in computer architecture, datacenter systems, and cloud-native server design. His research focuses on post-Moore era computing, emphasizing heterogeneous architectures, energy efficiency, and scalable IT infrastructure. Falsafi is the founder of EcoCloud, an EC-sponsored industrial-academic consortium investigating sustainable information technology. He holds ACM and IEEE fellowships, a Sloan Research Fellowship, and has contributed to major projects like Optimus Prime (data transformation acceleration), AstriFlash (flash-based online service systems), and Midgard (virtual memory re-design). His work spans hardware-software co-design, memory systems, and security. Falsafi advises numerous PhD students and collaborates with industry partners such as Google and Cavium. Key achievements include pioneering scalable multiprocessor architectures, snoop filters in IBM BlueGene, and spatial memory streaming in ARM cores. His lab develops open-source tools like QFlex for server simulation. He frequently presents at top conferences (HPCA, ISCA, MICRO) and chairs workshops on post-Moore infrastructure. Teaching roles include leading courses in computer architecture and parallel systems across multiple EPFL departments (SIN, EDIC, SSC, SMA). His work addresses datacenter challenges like the 'data tax' and mitigating latency through specialized accelerators.

Yang Zhouمشاهده پروفایل

دانشیار

• Big Data Algorithms
• Data Mining
• Machine Learning
• +۵ مورد دیگر

Yang Zhou is an Associate Professor in the Department of Computer Science and Software Engineering at Auburn University, part of the Samuel Ginn College of Engineering. His research focuses on big data algorithms, machine learning, data mining, and distributed computing. He has contributed to advancements in federated learning frameworks, graph mining tools, and spatial machine learning for environmental applications like flood mapping. Education includes a Ph.D. in Computer Science from Georgia Tech (2021), M.E. in Computer Application Technology from Chongqing University (2016), and B.E. in Engineering from Jiangnan University (2014). His work emphasizes scalable algorithms for large-scale systems, with tools like DirDense for dense subgraph mining and FedASMU for federated learning optimization. Recent publications explore adversarial robustness, blockchain strategies in IoT, and curriculum-based learning for large language models. He advises on interdisciplinary projects at the intersection of AI and environmental science.

Geng Yuanمشاهده پروفایل

استادیار

• Artificial Intelligence Systems
• Energy-Efficient Deep Learning
• Model Compression
• +۵ مورد دیگر

Geng Yuan is an Assistant Professor at the University of Georgia's School of Computing, specializing in AI systems, energy-efficient deep learning, and hardware-software co-design. His work bridges machine learning algorithms with emerging hardware technologies like superconducting circuits and ReRAM. He holds a Ph.D. in Computer Engineering from Northeastern University (2023) and a Master's in Electrical & Computer Engineering from Syracuse University (2016). Doctor of Philosophy (Ph.D.) in Computer Engineering, Northeastern University (2023) Master of Science (M.S.) in Electrical & Computer Engineering, Syracuse University (2016) Bachelor of Science (B.S.) in Electrical Engineering, Beijing University of Technology (2014) His research focuses on optimizing deep learning systems for edge computing and mobile platforms through techniques like model compression, sparse training, and hardware-aware neural architecture search. Recent projects include adapting large language models via hybrid-grained pruning and developing ultra-low-power AQFP circuits for binary networks. Geng Yuan's publications span top venues like NeurIPS, CVPR, ICML, ICLR, ISCA, and DAC, with notable awards including a Best Paper Award at ICLR Workshop 2021, Spotlight Papers at ICLR 2023 and NeurIPS 2021, and a Design Contest 1st Place at ISLPED 2020. Best Paper Award (ICLR Workshop'21) Spotlight Paper Award (ICLR'23, NeurIPS'21) Design Contest 1st Place (ISLPED'20) Best Paper Nomination (DATE'21, ISQED'18) He actively recruits Ph.D., Master's students, and interns to his research group, focusing on advancing AI systems through interdisciplinary approaches combining machine learning, computer architecture, and electronic design automation.

Andre DeHonمشاهده پروفایل

استاد

• Reconfigurable Computing
• FPGA Architecture
• Interconnect Design
• +۶ مورد دیگر

André DeHon is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering at the University of Pennsylvania, with affiliations in the Electrical and Systems Engineering (ESE) and Computer and Information Science (CIS) departments. He founded the Penn Computer Engineering (CMPE) program and directs the DARPA-sponsored CyberSavvy Security Center. His research spans reconfigurable computing, FPGA architecture, interconnect design, hardware security, and energy efficiency, with a focus on adapting to fabrication imperfections and runtime variability. His work explores programmable substrates (e.g., CMOS VLSI, molecular electronics) and algorithmic mappings to create resilient, efficient systems. Current projects include runtime feedback mechanisms (REFINE), partial reconfiguration (ExHiPR), and security frameworks like SCALPEL and μSCOPE. Recent publications highlight advancements in FPGA compilation (PLD, HiPR), security (SCALPEL, μSCOPE), and interconnect optimization (Asymmetry in NoC). These studies intersect computer architecture, security, and embedded systems. Scientific awards and recognitions: 2023 IEEE Fellow 2020 IEEE Mary Kenneth Keller Teaching Award 2018 ACM Fellow TCFPGA Hall of Fame (2019) Best Paper at ICFPT 2015 Academic leadership: He chairs the ACM/SIGDA Technical Committee on FPGAs and Reconfigurable Computing, previously held faculty roles at Caltech (1999–2006), and was a postdoc at UC Berkeley (1996–1999). Education includes MIT SB (1990), SM (1993), and PhD (1996) in Electrical Engineering and Computer Science.

Zhonghai Luمشاهده پروفایل

استاد

• Computer Architecture
• Embedded Systems
• Network-on-Chip (NoC)
• +۷ مورد دیگر

Zhonghai Lu is a Professor of Electronic Systems Design (specializing in Dependable and Autonomous Systems) at KTH Royal Institute of Technology, part of the Department of Electrical Engineering in the School of Electrical Engineering and Computer Science (EECS). He serves as Program Director for KTH's Embedded Systems master's program and Director of Studies at the Division of Electronics and Embedded Systems. His research focuses on Network-on-Chip (NoC), computer architecture, embedded systems, and Prognostics and Health Management (PHM) of power electronics. He leads a research group exploring in-network processing and embedded intelligence, transforming passive networks into active computational frameworks. Lu holds a BSc from Beijing Normal University (1989), MSc and PhD from KTH (2002, 2007), and an MBA in Innovation and Growth from the University of Turku (2012). He has authored over 240 scientific papers, including journal articles and peer-reviewed conferences, with notable recognitions such as Best Paper Awards at NOCS’2015 and EU HiPEAC, and a Featured Paper in IEEE Transactions on Computers (2020). He serves as Associate Editor for ACM Transactions on Architecture and Code Optimization (TACO) and has chaired major conferences like HiPEAC’2017 and NOCS’2018. His research group’s recent work includes integrating AI into hardware acceleration, fault-tolerant neural networks, and RUL estimation for power electronics using recurrent neural networks. Lu has secured grants from the Swedish Research Council and Intel Corporation and developed courses like IL2230 (Hardware Architectures for Deep Learning) and IL2233 (Embedded Intelligence), pioneering embedded AI education at KTH. Education: BSc (Beijing Normal University), MSc/PhD (KTH), MBA (University of Turku) Awards: Best Paper Awards (NOCS, EU HiPEAC), Swedish Research Council Grants, Intel Research Gifts Labs/Teams: Research Group on In-Network Processing and Embedded Intelligence

Rashmi Vinayakمشاهده پروفایل

دانشیار

• Computer Systems
• Networked Systems
• Information Theory
• +۵ مورد دیگر

Rashmi Vinayak is an Associate Professor in the Computer Science Department at Carnegie Mellon University, with a courtesy appointment in the Electrical and Computer Engineering Department. She is a member of both the Systems group and Theory group at CMU and leads TheSys research group. She is also affiliated with the Parallel Data Lab (PDL). Her educational background includes a Ph.D. from UC Berkeley in 2016, followed by postdoctoral studies at the same institution. Rashmi's research spans the intersection of computer/networked systems and information/coding theory. Her current focus is on robustness and resource efficiency in data systems across storage, communication, and computation. Key thrusts include storage systems, caching systems, and systems for machine learning. Her work on SIEVE, a cache eviction algorithm, has been widely adopted by industry including VMware, Google, Redpanda, and numerous open source libraries. Her recent publications demonstrate a strong trend toward practical systems research with theoretical foundations, particularly in caching algorithms, storage systems, and machine learning infrastructure. Many of her papers have received best paper awards and industry adoption. Notable awards include: Sloan Research Fellowship (2023) IEEE Information Theory Society Goldsmith Lecturer (2023) NSF CAREER Award (2020) Multiple USENIX NSDI Community (Best Paper) Awards VMware Systems Research Award (2021) Facebook and Google Research Awards Rashmi has supervised numerous PhD, Master's, and undergraduate students, many of whom have gone on to prestigious positions at Harvard, Google, Meta, and other leading institutions. Her research has been generously funded by NSF, Sloan Foundation, Open Compute Project, Google, Facebook/Meta, VMware, and Amazon Web Services. She actively collaborates with industry partners including Google, Microsoft, NetApp, Facebook, Cisco, Intel and Cloudera. She leads TheSys research group which focuses on designing next-generation data systems that are robust, efficient, and performant. The group takes a multi-disciplinary approach spanning computer systems, information theory, and machine learning.

Zhenman Fangمشاهده پروفایل

دانشیار

• Customizable Computing
• Heterogeneous Computing
• FPGA Acceleration
• +۸ مورد دیگر

Dr. Zhenman Fang is an Associate Professor at the School of Engineering Science , Simon Fraser University (SFU) , where he founded and directs the HiAccel Lab . He also holds an associate membership in the School of Computing Science at SFU. His research focuses on customizable computing with software-defined hardware acceleration , addressing performance, energy-efficiency, and reliability in post-Moore’s law computing across domains like machine learning , big data analytics , quantum chemistry , and precision medicine . Education: Ph.D. in Computer Science from Fudan University (2014), with a visit to University of Minnesota during his studies. Postdoctoral Work: University of California, Los Angeles (UCLA) (2014-2017). Industry Experience: Staff Software Engineer at Xilinx (2017-2019). Dr. Fang’s research spans the entire computing stack , including application characterization , accelerator-rich architecture design , and programming/tool support . He has developed frameworks like HiSpMV , SyncNN , and SQL2FPGA , emphasizing FPGA acceleration for vision transformers , quantum chemistry , and spiking neural networks . His work has been recognized with 3 best paper awards (FPL 2024, TCAD 2019, MEMSYS 2017) and 3 best paper nominees (FCCM 2025, HPCA 2017, ISPASS 2018). Recent publications highlight trends in low-precision machine learning ( ShiftQuant , ESRU ), quantum chemistry acceleration ( SERI ), and vision transformer optimization ( Quasar-ViT ). His HiAccel Lab actively mentors PhD and MASc students , with notable graduates like Alec Lu (PhD 2024, now at Meta) and Philip Stachura (MASc, now with BC Graduate Scholarship). Scientific Awards: Inaugural SFU Research Excellence Award - Horizon Award (2025) FPL 2024 Stamatis Vassiliadis Best Paper NSERC Alliance Award (2020) CFI JELF Award (2019) Xilinx University Program Award (2019) IEEE Senior Member (2023) Grants: NSERC Discovery Grant (2019) CFI JELF Funding (2019) Huawei and Xilinx sponsorships Dr. Fang leads open-source initiatives like SyncNN , PASTA , and SQL2FPGA , and serves as General Chair for ASAP 2025 and Program Co-Chair for RAW 2025 . His lab collaborates globally with institutions such as UCLA , Northeastern University , and Xidian University .

José F. Martínezمشاهده پروفایل

استاد

• Computer Architecture
• Microprocessor Design
• Multiprocessor and Multicore Architectures
• +۵ مورد دیگر

José F. Martínez holds the Lee Teng-hui Professorship of Engineering at Cornell University's College of Engineering, where he leads research in computer architecture and systems. His roles include Vice Chair of ACM SIGARCH, IEEE Fellow, and past leadership roles in ISCA, MICRO, and IEEE Computer Society journals. He has received prestigious awards such as the NSF CAREER Award, IBM/Qualcomm Faculty Awards, and multiple teaching accolades including Tau Beta Pi Professor of the Year (2011). Education: Licenciado en Informática de Sistemas (1996), Universidad Politécnica de Valencia M.S. (1999) and Ph.D. (2002) in Computer Science, University of Illinois at Urbana-Champaign His research focuses on computer architecture , including microprocessors, multiprocessors, memory subsystems, embedded systems, and processing-in-memory (PIM) innovations. He co-leads the DARPA/SRC ACE Center for Evolvable Computing and NSF's CROPPS Center, and previously co-founded Cornell's Institute for Digital Agriculture (CIDA). His work bridges hardware-software co-design and sustainable computing. Key Contributions: Advancing energy-efficient multiprocessor architectures Developing PIM frameworks like PUMICE and Membrane Market-based resource allocation systems (e.g., XChange, ReBudget) His advising spans over 15 graduate students and has guided Merrill Presidential Scholars. Current research explores evolvable computing paradigms and AI hardware acceleration, reflecting his dual focus on foundational architecture and applied systems innovation.

Cao Jiannongمشاهده پروفایل

دانشگاهی

• Cloud and edge computing
• Parallel and distributed computing
• Big data analytics
• +۲ مورد دیگر

Cao Jiannong is currently a Chair Professor and Director of the University Research Facility in Big Data Analytics at Hong Kong Polytechnic University . He has held academic roles including Assistant Professor at City University of Hong Kong and University Lecturer at the University of Adelaide and James Cook University. His research spans Cloud and Edge Computing , Parallel and Distributed Systems , Big Data Analytics , and Wireless Sensing . Ph.D. in Computer Science, Washington State University (1990) MSc in Computer Science, Washington State University (1986) BSc in Computer Science, Nanjing University, China (1982) His work focuses on solving theoretical and practical challenges in distributed computing , mobile cloud systems , and wireless sensor networks . Recent projects include coupled network embedding models for heterogeneous networks and SDN architectures for vehicular communication. His research also pioneers WiFi-based non-invasive health monitoring and fault-tolerant sensor deployment for structural health applications. Dr. Cao's publications highlight advancements in network embedding , edge computing , and WSN optimization . Key papers address multi-user computation partitioning , energy-efficient SHM systems , and consensus protocols for mobile networks. These works have been cited over 15,000 times, with an h-index of 60. Ministry of Education (China) Natural Science Award (2018) Distinguished Member, ACM (2017) Fellow, IEEE (2014) Best Paper Awards at IEEE DSAA, SMARTCOMP, and WCNC Dr. Cao has advised multiple PhD students, including Linchuan Xu and Weigang Wu , whose research on WSN-based SHM and coupled network embedding has practical impact. His leadership includes directing Hong Kong Polytechnic University's Big Data Research Facility and serving on technical committees for IEEE INFOCOM and ACM/IEEE conferences.

Marco Platznerمشاهده پروفایل

استاد

• Reconfigurable Computing
• Approximate Computing
• Self-Aware Computing
• +۷ مورد دیگر

Marco Platzner is a Professor for Computer Engineering at Paderborn University , Germany. He serves as the Dean of Research for the Faculty of Computer Science, Electrical Engineering and Mathematics and heads the Department of Computer Science. Previously, he held research positions at ETH Zurich, Stanford University, GMD (now Fraunhofer IAIS), and Graz University of Technology. Education: Diploma and PhD in Telematics (Graz University of Technology, 1991 and 1996), Habilitation in Hardware-Software Co-Design (ETH Zurich, 2002) Research Interests focus on reconfigurable computing, approximate computing, self-* computing, and embedded systems. His work addresses hardware security, FPGA design, and sustainable AI in data centers. Current projects include energy-efficient AI through deep neural network approximation for FPGAs (EKI-App) and lifecycle sustainability of socio-technical systems (SAIL). Publication Trends show expertise in FPGA security, approximate circuit synthesis, robotics, and hardware acceleration. Collaborations span robotics (ROS 2 integration), AI (transformer optimization), and cybersecurity (Trojan detection). Scientific Awards: ACM SIGDA Hall of Fame (2020) Significant Paper Award (FPL 2015) Best Paper Awards at IEEE ISVLSI (2024), ARC (2018), IEEE ReConFig (2015), and others Weierstraß Prize for Teaching (2008) Leadership Roles include membership in the board of Paderborn Center for Parallel Computing (PC2) and the Jenny Aloni Centre for Early Career Researchers. He has contributed to EU FP7 FET project EPiCS and German priority programs on embedded systems and organic computing.

Yannis Chronisمشاهده پروفایل

استادیار

• Database Systems
• Hardware-Software Co-design
• Data Processing Efficiency
• +۳ مورد دیگر

Yannis Chronis is an incoming Assistant Professor at the Department of Computer Science , ETH Zurich (starting August 2025), where he will join the ETH Systems Group . Prior to this, he spent 3 years as a Systems Researcher at Google's Systems Research Group in Sunnyvale, USA. He holds a Ph.D. in Computer Science from the University of Wisconsin-Madison (advised by Prof. Jignesh Patel) and a Bachelor's/Master's from the University of Athens, Greece (advised by Prof. Yannis Ioannidis). His research focuses on optimizing databases and data processing for modern hardware through software-hardware co-design. Key areas include database efficiency in memory-centric architectures, learned query optimizers, and cloud resource management. His work is supported by a Facebook Fellowship and has been recognized with the EDBT 2016 Medal for best paper. Teaching: Taught CS 564 - Database Management Systems at UW-Madison (Spring 2022). Service: Served on program committees for SIGMOD, VLDB, CIDR, and others, and chairs the CIDR Proceedings Committee. Key Publications: His recent work includes studies on memory-centric computing for databases, cardinality estimation benchmarks, and adaptive query processing techniques.

• Reconfigurable Computing
• Field-Programmable Gate Arrays (FPGA)
• High-Level Synthesis
• +۳ مورد دیگر

Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.

• Computer Architecture
• Machine Learning
• Cloud Computing
• +۴ مورد دیگر

Chita R. Das is a Professor at Pennsylvania State University, known for extensive contributions in computer architecture, machine learning, and high-performance computing. Their research focuses on optimizing hardware-software co-design for edge computing, cloud infrastructure, and energy-efficient systems. Key areas include FPGA acceleration, GPU optimization, and serverless computing frameworks. Das collaborates frequently with institutions like AMD and Intel, addressing challenges in parallel computing and distributed systems. Their work bridges theoretical advancements with practical applications in recommendation systems, bioinformatics, and real-time video processing. Research interests span across hardware acceleration techniques, cloud resource management, and sustainable computing. Notable projects include adaptive training frameworks for intermittent power environments and neural-augmented game streaming for mobile platforms. Das's publications often address performance bottlenecks in modern architectures and propose novel solutions for latency and energy efficiency. Recent articles highlight innovations in serverless computing cost optimization, low-bandwidth VR streaming, and FPGA-based bioinformatics tools. Their contributions are characterized by interdisciplinary approaches combining computer architecture with machine learning and embedded systems.