Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.
Giacomo Indiveri is a dual Professor at the Faculty of Science of the University of Zurich and the Department of Information Technology and Electrical Engineering of ETH Zurich . He serves as the Director of the Institute of Neuroinformatics at both institutions. Indiveri holds an M.Sc. in Electrical Engineering (1992) from the University of Genoa and a Ph.D. in Computer Science (2004) from the same university. Primary Affiliation: University of Zurich (Faculty of Science, Institute of Neuroinformatics) Secondary Affiliation: ETH Zurich (Department of Information Technology and Electrical Engineering) Indiveri's research bridges neuroscience , computer science , and machine learning to develop neuromorphic cognitive systems . His work focuses on spike-based learning , recurrent neural networks , and analog/digital circuit design for real-time sensory-motor systems . He integrates emerging memory technologies into fault-tolerant event-based architectures, enabling brain-inspired computing paradigms in applications like robotics and medical monitoring. His recent publications emphasize neuromorphic hardware for epileptic seizure detection , spiking neural networks in robotic painting , and scalable processors with on-chip learning . These works explore biologically plausible neurons , delay lines , and memory arrays for temporal processing, with applications in healthcare , edge computing , and adaptive control . Scientific Awards & Recognitions: 2021 IEEE Biomedical Circuits and Systems Best Paper Award Senior Member of IEEE Society ERC Fellow with three European Research Council grants Indiveri's group at the Institute of Neuroinformatics develops event-based systems for real-world validation of brain-inspired computing. His work includes multi-core processors , feedback optimizers , and dynamic routing architectures , supported by grants for advancing neuromorphic technologies .
Kyle C. Hale is an Associate Professor at Oregon State University's School of Electrical Engineering and Computer Science (College of Engineering). He holds a Ph.D. and M.S. from Northwestern University (2016, 2013) and a B.S. in Computer Science from UT Austin (2010). Prior to joining Oregon State in 2024, he served as an Associate Professor at Illinois Tech in Chicago. His research spans operating systems, high-performance computing (HPC), virtualization, computer architecture, and system security. Current work focuses on specialized system software stacks for emerging computing paradigms like memory disaggregation and parallelism optimization. He leads the HExSA Lab and collaborates with the HiPCastor group. Scientific Awards: NSF CAREER Award (2023-2028) Illinois Tech College of Computing Excellence in Research (2023) Illinois Tech College of Computing Excellence in Teaching (2021) Illinois Tech Department of Computer Science Teacher of the Year (2020) EuroSys '22 Best Artifact Award Recent Research Trends: His publications emphasize compiler techniques for memory-disaggregated systems, optimizing parallel runtimes through hardware-software integration, virtualization at fine granularities, and accelerating machine learning workloads via system-level innovations. Keywords include HPC, virtualization, parallelism, and secure execution contexts. Teaching: Courses taught include Computer Architecture (CS/ECE 472), System Security (CSP 544), Operating Systems (CS 450), and advanced topics in serverless/edge computing. He actively recruits PhD students to the HExSA Lab.
Mehmet Esat Belviranli is an Assistant Professor in the Computer Science Department at the Colorado School of Mines, where he directs the High Performance Systems and Software Lab (HyperSys). His research focuses on increasing resource utilization in heterogeneous architectures through runtime systems, scheduling algorithms, and performance modeling, with publications in top venues including MICRO, PPoPP, and SC. Education: Ph.D. in Computer Science, University of California, Riverside (2016) M.S. in Computer Science, Bilkent University (2009) B.S. in Computer Science, Bilkent University (2006) Belviranli's research spans heterogeneous architectures, runtime systems, performance modeling, parallel programming, autonomous computing, deep learning acceleration, cyber-physical systems, and edge-cloud platforms. His work develops analytical models and programming abstractions to address resource management, scheduling, and security challenges in diversely heterogeneous systems, with applications in edge computing, autonomous systems, and machine learning acceleration. Recent projects emphasize real-world constraints and security implications. His publication trends reveal increasing focus on edge-cloud resource management (e.g., HARNESS), security vulnerabilities in heterogeneous systems (e.g., MC3), and deep learning acceleration under resource constraints. Key themes include memory contention modeling, scheduling for cyber-physical systems, and concurrent DNN execution, reflecting a shift toward practical deployment in security-sensitive edge environments. Scientific Awards: U.S. Air Force Research Lab Summer Faculty Fellowship Award (2022) U.S. Air Force Research Lab Summer Faculty Fellowship Award (2021) Oak Ridge National Laboratory Significant Event Award (2019) Best Paper Finalist, IEEE HPEC 2018 Outstanding Paper Award, DATE 2024 Belviranli mentors Ph.D. students Ismet Dagli (MLCommons Rising Star 2024, CGO'24 SRC finalist) and Justin Davis (DATE'24 Outstanding Paper Award winner). He has secured $2M+ in funding from NSF, DoE, and SRC, including an NSF-SaTC grant on mobile security (2024), a DoE grant on superconductive systems (2023), and an NSF FuSe grant on graphene nanoribbons (2023), often leading multi-institutional teams from Rochester, Virginia, Arizona, and Minnesota. The HyperSys Lab develops ecosystems for high-performance heterogeneous systems, with recent projects including HARNESS for edge-cloud resource management and MC3 for mobile SoC security. The lab has received equipment donations from Google Coral.ai and Xilinx, and collaborates with national labs on security challenges and next-generation semiconductor technologies.
Monica Lam is the Kleiner Perkins, Mayfield, Sequoia Capital Professor in Stanford University's School of Engineering and holds a courtesy professorship in Electrical Engineering. She leads the Stanford Open Virtual Assistant Laboratory and has pioneered work in virtual assistants, privacy protection, and compiler design. Her research includes the Almond virtual assistant, privacy-preserving IoT systems, and the ThingTalk programming language. She co-authored the seminal 'dragon book' on compilers and co-founded Tensilica (now part of Cadence). Education: Bachelor of Science (Honors), Computer Science, University of British Columbia, 1980 Master of Science, Computer Science, Carnegie Mellon University, 1982 Doctor of Philosophy (PhD), Computer Science, Carnegie Mellon University, 1987 Research Interests: Dr. Lam's work focuses on conversational AI with privacy guarantees, compiler optimization for parallel computing, and open-source virtual assistant ecosystems. She is a leader in decentralized systems, having developed frameworks like SociaLite for large-scale graph analysis and Musubi for mobile social networking without centralized platforms. Article Trends: Recent publications emphasize multimodal interactions, multilingual dialogue systems, and LLM-driven applications in areas like question answering, persuasive chatbots, and adaptive assistants. Her work bridges foundational AI research (e.g., semantic parsing) with real-world deployments (e.g., privacy-compliant IoT). Awards & Honors: Member of the National Academy of Engineering ACM Fellow Popular Science's Best of What's New Award (Security, 2019) Advising & Grants: Lam oversees the Open Virtual Assistant Initiative, a collaborative project to build open-source semantic models. Her NSF CNS grant (CNS Core) focuses on federated privacy systems. She has advised over 50 students in AI and systems research, though specific names are not listed in the provided texts. Labs & Teams: Directs the Stanford Open Virtual Assistant Laboratory, collaborates with the Stanford NLP group, and maintains ties to industry through former startup Tensilica's legacy in embedded processors.
Michela Becchi is an Associate Professor in the Department of Electrical and Computer Engineering at North Carolina State University. She specializes in computer architecture, systems software, and applications, with a focus on heterogeneous systems, parallel algorithms, and acceleration techniques for bioinformatics, pattern recognition, and quantum computing. Her work spans multi-core CPUs, GPUs, FPGAs, and distributed clusters, emphasizing the boundary between hardware and software design. Dr. Becchi holds a Ph.D. and Master’s degree in Computer Engineering from Washington University in St. Louis (2009) and a Bachelor’s degree in Computer Engineering from Politecnico di Milano, Italy (2000). Her research has been recognized with prestigious awards, including the NSF CAREER Award (2015) and the University of Missouri System President Award for Early Career Excellence (2016). Her research interests include compiler and runtime techniques for heterogeneous systems, acceleration of bioinformatics algorithms, and high-speed networking applications. She has pioneered frameworks for efficient data transformation, GPU-accelerated compression, and memory-efficient graph algorithms for quantum computing. Her work also explores thread coarsening, mixed-precision auto-tuning, and secure multi-core processor design. Key contributions include the PILOT runtime system for GPU memory management, the GPU-FPtuner auto-tuner for floating-point applications, and innovative approaches to automata processors for genomic analysis. Her publications emphasize reproducible accuracy in scientific simulations and the optimization of irregular applications on many-core platforms.
Marco Caccamo is a Professor at the Technical University of Munich (TUM) , holding the Chair of Cyber-Physical Systems in Production Engineering within the Faculty of Mechanical Engineering. He is also a Principal Investigator and Professor at the Department of Computer Science, with courtesy appointments in Electrical and Computer Engineering, Coordinated Science Lab (CSL), and Aerospace Engineering at the University of Illinois at Urbana-Champaign (UIUC). His research spans Embedded Systems , Real-Time Systems , and Cyber-Physical Systems (CPS) , focusing on resource management, reinforcement learning architectures, and 6D pose recognition for robotics. University of Pisa (B.Sc., 1997) Scuola Superiore Sant'Anna (Ph.D., 2002) Research highlights include predictable resource management on heterogeneous platforms, security frameworks for AI-based controllers , and UAV testbed development . His work integrates deep learning and real-time constraints in industrial applications like avionics, farming, and automotive systems. His 15 most recent publications emphasize cache optimization , memory bandwidth regulation , and reinforcement learning for CPS , with a focus on multi-core processors and DNN inference . Awards include the IEEE Fellow (2018), Alexander von Humboldt Professorship (2018), and multiple Best Paper Awards at RTSS, RTNS, and RTAS. NSF CAREER Award (2003) IEEE Fellow (2018) Alexander von Humboldt Professorship (2018) Best Paper Awards (RTSS 2024, RTNS 2023, ECRTS 2019) He has advised numerous Ph.D. students and postdocs, with a track record in UAV development and industrial collaborations . His lab, the Real-Time and Embedded System Laboratory , focuses on real-time OS and predictable computing .
Dr. Alessandro Ottaviano is a Researcher affiliated with the Department of Digital Integrated Circuits and Systems at ETH Zürich. His work focuses on advanced computer architecture and embedded systems, particularly in the domains of RISC-V processors, real-time systems, and heterogeneous computing. He contributes to the design of time-predictable virtual memory solutions, mixed-criticality systems, and energy-efficient hardware-software interfaces. Key research areas include modular processor architectures, hardware monitoring for safety-critical applications, and power management in high-performance computing (HPC) systems. His recent projects involve developing controllers for 2.5D systems-in-package and creating open-source networking solutions for mixed-criticality environments. Ottaviano’s work often emphasizes open-source hardware design and scalable system-level approaches to address challenges in autonomous systems and edge computing. He collaborates on advancements in interrupt handling for virtualized systems, peripheral event linking for IoT devices, and FPGA-based thermal emulation for many-core processors. His research bridges theoretical computer architecture principles with practical implementations in embedded and real-time systems.
Luca Carloni is a Professor of Computer Science and Department Chair at Columbia University's Columbia Engineering. He leads the System-Level Design Group, focusing on heterogeneous system-on-chip (SoC) architectures, networks-on-chip (NoC), and embedded systems. Carloni holds a Laurea Summa Cum Laude in Electronics Engineering from the University of Bologna and a PhD in Electrical Engineering and Computer Sciences from UC Berkeley. His work emphasizes specialized hardware design, energy-efficient computing, and FPGA-based prototyping. Research interests include system-level design methodologies for SoCs, embedded accelerators, and quantum computing hardware. He has pioneered frameworks like Embedded Scalable Platforms (ESP) and tools like MosaicSim for rapid SoC prototyping. Carloni has received numerous awards, including the NSF CAREER Award (2006), IEEE Fellow (2017), and multiple best paper awards at DATE and CloudCom conferences. He has served on editorial boards of IEEE Transactions on CAD and ACM Transactions on Embedded Computing , and chaired key conferences like EMSOFT and ESWeek. His research addresses challenges in heterogeneous architectures, power management, and the intersection of machine learning with embedded systems. Current projects explore quantum control systems, brain-computer interfaces, and energy-efficient datacenter computing.
Alaa Alameldeen is an Associate Professor in the School of Computing Science at Simon Fraser University (SFU), part of the Faculty of Applied Sciences. Previously, he worked as a Research Scientist at Intel Labs (2006–2020) and held an Adjunct Faculty position at Portland State University (2008–2018). He earned a PhD in Computer Sciences from the University of Wisconsin-Madison (2006), and earlier degrees from Alexandria University, Egypt. His research focuses on computer architecture, including memory systems (processing-in-memory, cache/memory compression, security), energy-efficient architectures, and hardware-software co-design for machine learning. He advises PhD and MSc students in these areas and teaches advanced computing science courses. Key contributions include innovations in memory hierarchies, cache compression techniques, and mitigating hardware vulnerabilities. His work has been published in top conferences (e.g., ISCA, MICRO, HPCA) and patented in areas like near-memory processing and error correction. Alameldeen currently leads a research group exploring secure and high-performance memory architectures. He has supervised multiple graduate students, with many progressing to roles at leading tech companies and academic institutions.
David Wentzlaff is a Professor of Electrical and Computer Engineering at Princeton University, with associated faculty roles in Computer Science and the High Meadows Environmental Institute (HMEI). He leads research in computing architecture, green computing, and sustainable system design. As Director of Undergraduate Studies, he shapes educational programs in his field. Education: Ph.D., Electrical Engineering, MIT (2012) M.S., Electrical Engineering and Computer Science, MIT (2002) B.S., Electrical Engineering, University of Illinois at Urbana-Champaign (2000) Research Focus: Future Computing Systems: Designing manycore architectures, cloud computing infrastructure, and chiplet-based systems for exascale computing. Sustainability: Developing energy-efficient hardware, recyclable computing systems, and eco-friendly decommissioning strategies. Hardware-Software Co-Design: Exploring FPGA integration, in-memory computing, and parallel processing frameworks. Advising & Grants: Advises 8 current graduate students, focusing on topics like chiplet design, neural acceleration, and sustainable computing. Recipient of NSF grants for projects like OpenPiton (open-source manycore research platform) and CAREER awards for energy-efficient architectures. Labs & Collaborations: Leads the Wentzlaff Research Group at Princeton. Develops open-source frameworks like PRGA (FPGA prototyping) and OpenPiton (manycore processor).
Prof. Dr. Estela Suarez is a Professor of High Performance Computing at the Institute for Computer Science, University of Bonn (W2 in the Jülich Model) and Joint Lead of the Division "Novel System Architecture Design" at the Jülich Supercomputing Centre (JSC), Forschungszentrum Jülich GmbH. She also leads the Research Group "Next Generation Architectures and Prototypes" at JSC and serves as Spokesperson of Helmholtz Information Program 1, Topic 2. Currently on sabbatical during the 2024/2025 and 2025 academic years, she remains active in research leadership roles. 2010: PhD in Physics from University of Geneva, Switzerland 2004: Master in Physics, Specialization in Astrophysics, University Complutense of Madrid, Spain Professor Suarez specializes in high performance computing with particular expertise in heterogeneous HPC system architectures and modular supercomputing architecture (MSA). Her research spans hardware prototyping and evaluation, system software development, operational data analysis, and co-design methodologies. She has pioneered approaches to address hardware heterogeneity through system-wide orchestration of diverse computing resources, enabling more efficient scientific computing across multiple domains. Her work bridges theoretical computer architecture with practical implementation challenges in exascale computing environments, focusing on real-world applications that require specialized hardware configurations. Professor Suarez's publication record shows a clear evolution from foundational work on the DEEP project (2016) through the development of modular supercomputing concepts (2019-2021) to current applications across diverse scientific domains (2022-2024). Her recent publications demonstrate how modular architectures can be effectively applied to climate modeling, neuroscience simulations, quantum chemistry calculations, and other computationally intensive fields. This trend highlights her focus on practical implementation challenges and the growing importance of adaptable computing architectures in modern scientific research. 2023/2024 Lehrpreis der Universität Bonn: UniBonn teaching award Professor Suarez has secured significant research funding through major projects including NUMERIQS (Projects A05, B02, and Z02), European Processor Initiative (EPI), DEEP-SEA (Software for Exascale Architectures), IFCES2 (optimization of simulation algorithms for exascale supercomputers), and AIDAS (virtual laboratory between Forschungszentrum Jülich and CEA on AI and data analytics). While currently not accepting new students due to sabbatical, she has previously mentored graduate students in high performance computing techniques and has delivered numerous invited lectures at international conferences. Professor Suarez leads the "Next Generation Architectures and Prototypes" research group at JSC and serves as Joint Lead of the "Novel System Architecture Design" division. She chairs the Research and Innovation Advisory Group (RIAG) from EuroHPC Joint Undertaking since 2024. Her work involves close collaboration with international research teams on advancing supercomputing architectures, including contributions to the University of Bonn's new HPC system "Marvin" which ranks on both the TOP500 and GREEN500 lists.
Dr. Feng Yan is an Associate Professor at the University of Houston's Computer Science Department, leading the Intelligent Data and Systems Lab (IDS Lab). He previously held an Associate Professor position at the University of Nevada, Reno. His research focuses on bridging Big Data, Machine Learning, and Systems, with interdisciplinary applications in wildfire science, materials engineering, and civil infrastructure. He has received prestigious awards such as the NSF CAREER Award and the Regents' Rising Researcher Award. Education: Ph.D. (2016) and M.S. (2011) in Computer Science from College of William and Mary; B.S. (2008) in Computer Science from Northeastern University. Research experience includes roles at Microsoft Research and HP Labs. Research Interests: Large Language Models (LLM), Distributed Deep Learning, AutoML, Serverless Computing, Federated Learning, and AI-driven domain sciences. His work emphasizes real-world impact through collaborations with industry and national labs. Publications: Over 60+ papers in top-tier venues like NeurIPS, ICLR, KDD, AAAI, SOSP, SC, and VLDB. Key contributions include ZeRO++ (collective communication optimization), Gradient Compression techniques, and Federated Learning frameworks like TiFL and HDFL. Awards: NSF EPSCoR Award ($20M), NSF CAREER Award, FAA BAKFAA Grant, and multiple best paper awards (IEEE CLOUD 2018, CLOUD 2019). Active in program committees for HPDC, ICAC, ICPE, and AAAI. Advising: Supervised over 30+ graduate/undergraduate students, with placements at Microsoft Research, IBM, Oak Ridge National Lab, Facebook, and MathWorks. Runs a vibrant lab with a focus on interdisciplinary AI/Systems research.
Dr. Eric Rotenberg is a Professor in the Department of Electrical and Computer Engineering at North Carolina State University. His research focuses on high-performance, low-power, and reliable processor architectures, with contributions to 3D stacked circuits, heterogeneous multi-core systems, and adaptive microarchitecture design. Education: Ph.D. in Computer Sciences, University of Wisconsin-Madison (1999) M.S. in Computer Sciences, University of Wisconsin-Madison (1996) B.S. in Electrical Engineering, University of Wisconsin-Madison (1991) Research Interests: Computer Architecture and Systems 3D-Stacked Integrated Circuits Heterogeneous Multi-Core Processors Microarchitecture Optimization Energy Efficiency in Processors Key Awards: IEEE Fellow (2015) NSF CAREER Award (2001) NC State Outstanding Teacher Award (2004) 2015 Micro Test-of-Time Award (co-authored) Professional Contributions: Developed the AnyCore adaptive processor framework and the H3 3D-stacked heterogeneous multi-core processor. Explored post-silicon microarchitecture adaptation and slipstream processors for improved performance and fault tolerance.
Anuj Pathania serves as an Assistant Professor in the Parallel Computing Systems (PCS) group within the Informatics Institute at the University of Amsterdam's Faculty of Science. His research pioneers sustainable computing systems operating under severe power, thermal, and reliability constraints, with significant contributions to energy-efficient hardware design and embedded systems. Education: PhD in Computer Science (2018), Karlsruhe Institute of Technology MSc in Computer Science (2012), National University of Singapore B.Tech in Computer Science (2009), Maharaja Agrasen Institute of Technology Pathania's research centers on low-power design and sustainable systems for constrained environments, with particular expertise in thermal management of 3D-stacked architectures and energy-efficient machine learning inference . His work bridges electronic design automation with real-world reliability challenges, developing novel power budgeting techniques like T-TSP that incorporate transient temperature effects ignored by conventional methods. Current projects include EU-funded initiatives on energy labeling for digital services, addressing ecological impacts through technological, behavioral, and legal frameworks. His publication trajectory reveals a strategic evolution toward zero-waste computing , with recent work (2023-2025) focusing on hardware-software co-design for edge AI, energy modeling across computing continua, and parameter-efficient neural adaptation. Key themes include thermal-aware scheduling for S-NUCA many-cores, cooperative processor utilization in heterogeneous systems, and sustainability metrics for digital services. Scientific Recognition: Best Paper Award Nomination at IEEE Computer Society Annual Symposium on VLSI 2023 for 3D-TTP power budgeting technique Pathania actively mentors 4 PhD students (Ehsan Aghapour, Saeedeh Baneshi, Sudam Wasala, Yixian Shen) and has successfully supervised 5 Master's theses (including Cum Laude defenses by Joris op ten Berg and Jurre Wolff). His research is supported by major grants including Energy Labels for Ecologically Sustainable Digital Services (2023-2024) and Towards Zero-Waste Computing (2021-2025), developing simulation frameworks like HotSniper and CoMeT for thermal analysis. The PCS group maintains strong industry collaborations with ARM and NVIDIA, particularly through tools like ARM-CO-UP for heterogeneous processor utilization.
