Dr. John Wickerson is an Associate Professor in the Circuits and Systems group at the Department of Electrical and Electronic Engineering, Imperial College London. His research focuses on improving the reliability of high-performance computing through formal methods, with contributions to high-level synthesis, memory models, and concurrency verification. He holds leadership roles including Course Director for the Electrical and Information Engineering degree and Deputy Tutor for PhD students. Research Interests: Formal Verification of Hardware/Software Systems High-Level Synthesis (HLS) and FPGA Compilation Weak Memory Models and Concurrency Semantics Fuzz Testing for Hardware Tools Compiler Optimization and Correctness Digit Elision and Arbitrary-Precision Arithmetic Notable Achievements: Best Paper Award at EuroSys 2024 (database isolation validation) Pioneered formal methods for HLS tools (e.g., QuteFuzz, C4) Co-developed the C4 C compiler concurrency checker Published over 60 peer-reviewed papers across top venues (ASPLOS, PLDI, FPGA) Lab/Team: Part of the Circuits and Systems group at Imperial College, collaborating with industry partners like Kaihong Yann and ARM.
Luciano Lavagno is a Full Professor at the Department of Electronics and Telecommunications, Polytechnic University of Turin, with over two decades of academic and research contributions. His work bridges hardware acceleration, low-power electronics, and intelligent system design. Research Focus: Hardware-accelerated machine learning, high-level synthesis (HLS) for FPGA/ASIC, heterogeneous CPU/GPU/FPGA platforms Key Projects: SPACE (predictable acceleration), REBECCA (secure AI acceleration), HPC-National Center (quantum computing), and oral history preservation via "Ti racconto una storia" initiative His recent publications analyze CNN inference optimization, subgraph isomorphism, and superword-level parallelism exploitation. Lavagno supervises multiple PhD students working on FPGA acceleration, neural network hardware, and embedded systems. As Principal Investigator for national and EU-funded projects (PRIN, JTI-ECSEL, PNRR), he drives advancements in sustainable computing infrastructure. His patented technologies include MIx&Latch timing methodology, capacitive sensing innovations, and 5G acceleration frameworks.
Kimia Zamiri Azar serves as an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida, focusing on hardware security and verification methodologies. Her research bridges theoretical formal methods with practical security implementations in semiconductor design and testing. Her educational background includes: Ph.D. in Electrical and Computer Engineering, George Mason University (2021) Postdoctoral Research, University of Florida Dr. Azar's research spans hardware security with emphasis on system-level verification, VLSI design-for-trust, and advanced IC testing. She pioneers techniques in logic locking, secure heterogeneous integration, and IC supply chain security, developing frameworks for authenticated encryption in Systems-in-Package and runtime security monitoring. Her work integrates formal verification with innovative testing methodologies to address hardware trust challenges across the semiconductor lifecycle. Analysis of her recent publications reveals two dominant trends: (1) Application of large language models (LLMs) to hardware design tasks including high-level synthesis code generation and RTL optimization, and (2) Advancement of secure heterogeneous integration techniques for System-in-Package architectures with focus on counterfeit prevention and split-test security protocols. These directions address critical gaps in hardware trustworthiness amid increasingly complex semiconductor supply chains. Her scientific contributions have earned significant recognition: Best Paper Award at ICCAD 2019 Best Paper Award at ISVLSI 2020 Best Paper Award at ICCAD 2020 Best Paper Award at IEEE DCAS 2020 Best Paper Award at HOST 2022 Best Paper Award at DATE 2023 Dr. Azar secures substantial research funding from premier agencies including NSF, SRC, DARPA, AFRL, DoD (NG), and Microsemi. Her grants support projects spanning hardware security validation frameworks, secure heterogeneous integration, and AI-augmented verification methodologies. She actively mentors students in her research group, guiding publications in top venues like IEEE D&T, IEEE TC, and DAC while fostering industry-academic collaborations. Her work directly impacts semiconductor security standards through patented innovations and open-source verification tools. As an active IEEE and ACM member, she contributes to community advancement through conference organization (HOST, DATE), journal editorial roles, and workshop leadership on hardware security standards. Her research group collaborates with semiconductor industry leaders to translate theoretical security frameworks into practical design-for-trust methodologies for next-generation integrated circuits.
Nikos Hardavellas is a Professor of Computer Science and Electrical and Computer Engineering at Northwestern University, affiliated with the McCormick School of Engineering. He leads the Parallel Architecture Group at Northwestern (PARAG@N), focusing on energy-efficient parallel computing and quantum systems. His research spans quantum computing systems, fault-tolerant quantum error management, memory-centric architectures, and photonics-based interconnects. Education: Ph.D. Computer Science, Carnegie Mellon University (2009) M.S. Computer Science, Carnegie Mellon University (2006) M.S. Computer Science, University of Rochester (1997) B.S. Computer Science, University of Crete (1995) Research Interests: Quantum system software stack and error mitigation Memory-centric computing and programmable memory systems Energy-efficient architectures and dark silicon Photonics and optical interconnects Parallel systems and compiler-hardware co-design Key Contributions: Developed SupermarQ, a scalable quantum benchmark suite Pioneered optical cache hierarchies (Pho$) and energy-proportional photonic networks Advanced compiler-driven virtual memory systems (CARAT) and MPI autotuning (ACCLAiM) Awards & Honors: NSF CAREER Award (2015) Future CRA Leader (2024) Best Paper Awards at HPCA (2022) and ISLPED (2021 nomination) Test-of-Time Award at EDBT (2019) Grants & Service: Secured $4.8M in research funding from NSF, industry partners, and university initiatives Executive Committee member of Northwestern’s INQUIRE Institute for Quantum Research General Co-chair of IEEE/ACM MICRO 2022 Extensive service on departmental committees and thesis advisory boards Labs & Teams: Directs PARAG@N, collaborating on quantum computing, photonics, and energy-efficient architectures. Engages with industry partners like AMD, Intel, and Synopsys.
Yongshan Ding is an Assistant Professor of Computer Science and Applied Physics at Yale University. He leads the Quantum Systems Lab (QSL) and directs Yale's Quantum Science and Engineering Certificate program. Affiliated with the Yale Quantum Institute (YQI) and Computer Systems Lab (CSL), his research focuses on quantum computing systems spanning algorithms, architecture, and hardware/software co-design. Dr. Ding earned his Ph.D. from the University of Chicago and a B.Sc. from Carnegie Mellon University. He has received prestigious awards including the Siebel Scholarship (2020) and William Rainey Harper Dissertation Fellowship (2020). Research Interests: Quantum computing architectures, noise-resilient quantum algorithms, error correction methods, quantum compilation, hardware-software co-design, and NISQ system optimization. Editorial Roles: Editor at Quantum journal and Associate Editor at ACM Transactions on Quantum Computing . Labs: Founder of Yale's Quantum Systems Lab (QSL) and contributor to the Computer Systems Lab (CSL). Awards: Siebel Scholarship (2020) William Rainey Harper Dissertation Fellowship (2020) QCE Best Paper Award (2024) IEEE Micro Top Picks Honorable Mention (2023, 2020) IBM Q Best Paper Award, First Prize (2020) Mathematics Competition Runner Up (2016)
Mark Batty is a Professor in the School of Computing at the University of Kent, specializing in formal methods for concurrent systems. His work bridges hardware-software interfaces, focusing on memory models for C/C++, OpenCL, and architectures including x86, ARM, POWER, and GPUs. As a member of the Programming Languages and Systems Research Group, he develops mathematical specifications and verification tools for real-world concurrency challenges. His research centers on empirical testing of hardware/compiler behavior, formal modeling of system components, and verification of fine-grained concurrent algorithms. Key contributions address relaxed memory semantics, transactional memory, and compositional reasoning for concurrent data structures. His work combines theoretical rigor with practical tool development to ensure correctness in complex concurrent environments. Analysis of his 2015-2025 publications reveals consistent focus on memory consistency models, formal verification of weak memory concurrency, and compiler optimizations. Dominant themes include C/C++11 standards, GPU concurrency semantics, and mechanized verification techniques. His research demonstrates strong industry relevance through collaborations with hardware vendors and contributions to language standards. Mark Batty has received significant recognition: John C. Reynolds Doctoral Dissertation Award (2015) from ACM SIGPLAN CPHC and BCS Distinguished Dissertation Award (2015) Lloyds Register Foundation and Royal Academy of Engineering Research Fellowship (2016) He actively leads major research initiatives and mentors next-generation researchers: Current Funding: EPSRC Standard Grant 'Verifiably Correct transactional memory' (2018), VeTTS Grant 'Specification and verification of C++ data structure libraries' (2018), EPSRC First Grant 'Compositional, dependency-aware C++ concurrency' (2018) PhD Recruitment: Actively seeking candidates for UKRI-funded studentship in Verified Trustworthy Software Systems Batty drives community engagement through Kent Concurrency Workshop (2016) and South of England Programming Language Seminars, fostering national collaboration in programming languages research. His leadership in organizing Royal Society discussions underscores his influence in trustworthy systems verification.
Lisa Yan serves as a Teaching Professor in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley, appointed in Spring 2022. She teaches core computer science education courses including CS 195 (Social Implications of Computer Technology), CS H195 (Honors variant), CS 294-189 (Teaching Process Design), and CS 375 (Teaching Techniques), holding regular office hours in Soda Hall for student engagement. Her academic credentials include: PhD in Electrical Engineering from Stanford University (2019) MS in Electrical Engineering from Stanford University (2015) BS in Electrical Engineering and Computer Science from UC Berkeley (2013) Dr. Yan's research centers on data-driven analysis of student learning in large-scale computer science courses, with significant contributions to computing ethics pedagogy and teaching assistant development programs. Her work develops innovative methodologies for assessing student earnestness in interactive lectures, creating flexible learning extensions, and designing integrity-focused assessments. Earlier research focused on software-defined networking and network switch performance optimization, demonstrating technical depth before her pivot to educational innovation. Current projects emphasize scalable teaching techniques and mastery learning frameworks that address challenges in modern CS education. Analysis of her 14 publications (2013-2024) reveals a strategic shift from computer networking (pre-2018) to computer science education research (2018-present). Recent work (2020-2024) dominates in venues like SIGCSE, featuring tools such as Otter-Grader for Jupyter notebook grading and the Earnest Insight Toolkit for lecture participation analysis. This evolution highlights her commitment to solving practical educational challenges through data analysis and tool development, particularly for large undergraduate courses. She received recognition through: The Faculty Award for Outstanding Mentorship of GSIs (2024) Lisa actively mentors Graduate Student Instructors and collaborates with educational technology initiatives. Her research team includes dedicated support staff like Taylor Kaserman (taylor.kase@berkeley.edu), reflecting structured collaboration in developing teaching innovations. She contributes to curriculum design committees within EECS, focusing on assessment integrity and scalable pedagogical methods for growing student populations. Her work operates through the EECS department's educational infrastructure, utilizing Soda Hall resources for both teaching coordination and research development, with strong connections to Berkeley's broader computing education ecosystem.
Chris Peikert is a Professor in the Department of Computer Science and Engineering at the University of Michigan's College of Engineering. He received his Ph.D. from MIT's Computer Science and Artificial Intelligence Laboratory in 2006 under the supervision of Silvio Micali. Peikert is a leading researcher in cryptography, particularly known for his foundational work in lattice-based cryptography. His research interests span cryptography, lattices, coding theory, algorithms, and computational complexity, with a particular focus on cryptographic schemes whose security can be based on the apparent intractability of lattice problems. Peikert has made significant contributions to the development and analysis of lattice-based cryptographic primitives, including ring-LWE, fully homomorphic encryption, and zero-knowledge proofs. Peikert's recent work demonstrates continued leadership in post-quantum cryptography, with publications in top venues like CRYPTO, EUROCRYPT, and STOC. His research spans theoretical foundations of lattice problems to practical implementations of lattice-based cryptographic systems, including hardware acceleration for fully homomorphic encryption. IACR Fellow (2024) Test-of-Time Award from Crypto 2008 (2023) TCC Test-of-Time Award (2017) Patrick C. Fischer Development Professor of Theoretical Computer Science (2017) Best Paper Award at Eurocrypt 2010 Best Paper Award at STOC 2009 Alfred P. Sloan Foundation Fellowship Google Research Award Peikert has been actively involved in the cryptographic research community, serving on program committees for major conferences including CRYPTO, EUROCRYPT, FOCS, and TCC (where he was program co-chair in 2021). He has also developed educational resources, including extensive lecture materials on lattice-based cryptography and teaching courses on cryptography and theoretical computer science at both the undergraduate and graduate levels.
Heiko Falk is a Professor and Head of the Institute of Embedded Systems at Technische Universität Hamburg (TUHH). His roles include serving as Workshop Chair for the 2024 Embedded Systems Week (ESWEEK), Scientific Coordinator for the B.Sc. and M.Sc. Computer Science programs, and Deputy Head of the Board of Examiners for Computer Science and Engineering. His research focuses on real-time systems, compiler optimizations, and worst-case execution time (WCET) analysis. Key areas include multi-core architectures, cache management, energy efficiency, and hardware/software co-design. Falk's work emphasizes practical compiler techniques for improving real-time performance, such as WCET-aware memory allocation, dynamic SPM optimization, and event-driven scheduling. His publications analyze shared cache interference, preemptive/non-preemptive scheduling, and DMA-aware optimizations. Recent work explores multi-objective trade-offs between WCET, energy consumption, and code size in embedded systems. No scientific awards are explicitly listed, but his contributions to WCET benchmarking (e.g., haRTStone project) and compiler frameworks demonstrate significant impact in the field. Advising and grants: No formal advisees are listed in the provided texts. Falk's work is supported through projects like teamplay, focusing on cyber-physical systems optimization. Labs/Teams: His group operates within TUHH's Institute of Embedded Systems, collaborating on projects addressing real-time system challenges in multi-core environments.
Simon Moore is a Professor of Computer Engineering at the University of Cambridge's Department of Computer Science and Technology. He leads the Computer Architecture research group, focusing on secure processors and subsystems, particularly the CHERI project. His work emphasizes formal verification, hardware-software co-design, and scalable security solutions. He is a Fellow and Director of Studies at Trinity Hall, overseeing undergraduate admissions and mentoring in Computer Science. Research Interests: Moore's primary focus is the CHERI secure processor architecture, integrating RISC-V cores with formal verification. His work spans secure hardware design, memory safety, and embedded systems. Notable contributions include the CHERI-RISC-V microarchitecture, CheriABI, and formal verification frameworks. Key Projects: CHERI, CheriBSD, Morello (ARM collaboration) Recent Achievements: Test of Time Award (IEEE Security & Privacy 2025), finalist for Bhattacharyya Award (2022) Grants: Innovate UK Digital Security by Design, DARPA Mission Oriented Resilient Clouds Publications: Over 200 papers on secure architectures, including influential work on CHERI's capability model, formal verification, and hardware security. Recent focus areas include temporal memory safety, embedded system security, and GPU-based capability systems. Labs/Teams: Directs the Computer Architecture Group and collaborates with industry partners like ARM and Microsoft on CHERI implementations.
Darko Marinov is a Professor at the Siebel School of Computing and Data Science and a member of the Information Trust Institute at the University of Illinois at Urbana-Champaign. His research focuses on software testing methodologies, particularly regression testing, flaky tests, and software reliability engineering. He has contributed to frameworks like Ekstazi for regression test selection and DeFlaker for identifying flaky tests. Marinov holds an NSF CAREER Award (2008) for his work in this domain. His research interests span testing techniques for modern software systems, including configuration testing, test prioritization, and fault localization. He has pioneered studies on the characteristics of flaky tests in large-scale projects and developed tools to improve software quality assurance processes. Marinov collaborates across academic and industrial settings, addressing challenges in continuous integration, reproducibility of computational experiments, and hardware-software co-design for resilience. His work bridges theory and practice, with applications in cloud computing, AI workloads, and cybersecurity. Awards: NSF CAREER Award (2008) Key Contributions: Ekstazi, DeFlaker, FastFlip, and Ctest4J frameworks Labs/Teams: Active member of the Information Trust Institute and leads software testing research groups at UIUC
Paul R. Genssler is a Dr.-Ing. researcher at the Chair of AI Processor Design (AI-Pro) within the Technical University of Munich (TUM), actively advancing hardware solutions for artificial intelligence under Prof. Hussam Amrouch. His work bridges computer engineering and emerging technologies, focusing on overcoming fundamental limitations in conventional computing architectures through brain-inspired paradigms. His research spans critical domains in next-generation computing: Hyperdimensional Computing for robust pattern recognition and bioinformatics applications Neuromorphic and In-Memory Computing architectures for energy efficiency Reliability engineering for emerging memory technologies (FeFET, etc.) Quantum computing support systems including cryogenic embedded electronics Machine learning-driven transistor aging prediction and mitigation Analysis of his 15 most recent publications (2023-2024) reveals a dominant trend toward hyperdimensional computing as a unifying framework for addressing reliability challenges in emerging technologies. His work consistently integrates in-memory computing techniques to bypass von Neumann bottlenecks while targeting real-world applications like genome matching and unsupervised learning. A significant portion focuses on error-resilient implementations for unreliable nanoscale devices, demonstrating exceptional cross-stack expertise from transistor physics to algorithm design. As a core member of TUM's AI Processor Design group affiliated with the Munich Institute of Robotics and Machine Intelligence (MIRMI), Genssler collaborates extensively on projects spanning cryogenic quantum control systems, FPGA-based AI resilience, and monolithic 3D integration. The team operates at the intersection of semiconductor physics, computer architecture, and machine learning, with strong industry connections evident through publications at DATE, ASP-DAC, and ICCAD.
Pasquale Davide Schiavone holds multiple research and teaching positions at École Polytechnique Fédérale de Lausanne (EPFL), serving as a Lecturer at the School of Computer and Communication Sciences (IC) and as a Scientist at both the Embedded Systems Laboratory (ESL) within the School of Engineering (STI) and PAT Administration. His interdisciplinary work bridges computer architecture, embedded systems design, and biomedical applications, with office located at ELG 136 in Lausanne, Switzerland. Dr. Schiavone's research focuses on ultra-low-power computing systems, particularly RISC-V architectures and TinyML applications for edge devices. His work develops open-source hardware platforms like X-HEEP and HEEPOCRATES that enable energy-efficient AI at the edge, with applications spanning biomedical monitoring, neural interfaces, and wearable computing. He explores innovative hardware-software co-design approaches to overcome energy constraints in resource-limited environments. His recent publications reveal a consistent research trajectory centered on open, configurable computing platforms for specialized applications. The work spans from fundamental RISC-V architecture improvements (ARCANE, e-GPU) to application-specific implementations for biomedical contexts (BiomedBench, neural interfaces). A strong emphasis on energy efficiency permeates all his research, whether through novel arithmetic approaches (Posit), system architecture (near-memory computing), or specialized accelerators (Strela, Quadrilatero). Lecturer, School of Computer and Communication Sciences (IC) Scientist, Embedded Systems Laboratory (ESL), School of Engineering (STI) Scientist, PAT Administration, School of Engineering (STI) Dr. Schiavone teaches courses on hardware compilation, presenting algorithms and methods for transforming hardware description languages into optimized circuit implementations. His Embedded Systems Laboratory work places him at the forefront of developing practical, open-source solutions for next-generation computing challenges in energy-constrained environments.
Prof. Ilia Polian serves as Head of the Institute of Computer Engineering and Chair of the Hardware-Oriented Computer Science (HOCOS) department at the University of Stuttgart. His leadership spans research, teaching, and institutional coordination across multiple high-impact projects. Prof. Polian's research focuses on developing circuit and system architectures based on both traditional and novel principles, including neuromorphic, stochastic, and approximate architectures. His second major research focus is systematic design methodology and design automation, with particular emphasis on safety and reliability properties of developed systems. Current research directions include quantum computing engineering, secure mixed-signal neural networks, and resource-efficient stochastic circuits for near-sensor computing applications. His recent publications demonstrate strong trends in quantum computing (particularly circuit partitioning and compilation for multi-QPU architectures), hardware security (including memristive cryptographic implementations), and AI-driven approaches to hardware testing and reliability. These works bridge fundamental computer architecture research with practical industrial applications. University of Stuttgart's Publication Prize for Paper on Partitioning of Quantum Circuits Prof. Polian actively supervises doctoral students including Devanshi Upadhyaya, and leads significant research grants such as the DFG Priority Program Nano Security which he coordinates. His department offers numerous thesis and research opportunities for students interested in cutting-edge hardware research. The Hardware-Oriented Computer Science department maintains strong collaborations with industry partners including IBM, Infineon Technologies, and Advantest, as well as academic institutions through the IQST Graduate School and QuantumBW initiatives.
Daniel Müller-Gritschneder is an Adjunct Teaching Professor (Privatdozent) at the Technical University of Munich (TUM), affiliated with the Chair of Electronic Design Automation. He leads the 'Electronic System Level' research group, focusing on embedded systems, TinyML, virtual prototyping, and hardware resilience. He temporarily served as head of the Chair of Real-Time Systems (2019–2020) and holds a senior membership in IEEE. His research spans: TinyML : Optimizing neural network inference for microcontrollers. Virtual Prototyping : Fast simulation for embedded software development (e.g., ETISS simulator). Runtime Verification : Hardware monitoring for safety-critical systems. Fault Tolerance : Cross-layer resilience against soft errors. Design Automation : NoC synthesis and RISC-V toolchain optimization. His publications emphasize RISC-V-based systems, TinyML deployment, fault injection, and embedded AI. Recent works show trends toward compiler-assisted security, thermal management, and automated design-space exploration for edge devices. Awards: Best Paper Award (SiPS 2019) Habilitation Award (Bund der Freunde der TUM, 2019) 2nd Best Paper (SMACD'15) Best Paper nominations at DAC'07, DATE'10, Analog'10, NOCS'13 He advises researchers in the Electronic System Level group and contributes to EU projects (e.g., Scale4Edge). His lab develops tools like ETISS, MLonMCU, and Seal5 for RISC-V and TinyML ecosystems.
