Dr. Chang Y Choo is a Professor of Electrical Engineering at San José State University, where he also serves as Director of the AI/ML FPGA/DSP Systems Laboratory. His academic career spans over three decades, with previous positions at Worcester Polytechnic Institute and industry experience at Altera Corp. (now Intel). Dr. Choo maintains an active research program focusing on hardware acceleration for AI and signal processing applications, with particular emphasis on FPGA-based implementations for real-world systems. Dr. Choo's educational background includes: Ph.D. in Computer and Systems Engineering, Rensselaer Polytechnic Institute (1986) M.S. in Operations Research and Statistics, Rensselaer Polytechnic Institute (1982) B.S./M.S. in Engineering, Seoul National University, Korea Dr. Choo's research interests center on the intersection of hardware design and artificial intelligence. His work focuses on implementing computer vision, deep learning, and digital signal processing algorithms on specialized hardware platforms including FPGAs, GPUs, and custom ASICs. Current projects include developing real-time illumination/view-independent object recognition systems for autonomous vehicles, wideband acoustic echo cancellation for wearable technology, and FPGA-based accelerators for medical imaging applications. His research bridges theoretical algorithm development with practical hardware implementation constraints. Analysis of Dr. Choo's recent publications reveals a clear trajectory toward increasingly sophisticated hardware-accelerated AI systems. His work has evolved from foundational research in digital signal processing and image compression to cutting-edge applications of deep learning on specialized hardware. Recent publications demonstrate expertise in implementing CNN architectures on FPGAs, developing metabolic syndrome prediction models, and creating food object detection systems using transformer models. This progression reflects the broader field's shift toward hardware-aware AI development. Dr. Choo's significant scientific contributions include multiple patents that have advanced the state of the art in several domains: U.S. Patent No. 9,025,763 (2015): 'Apparatus and Method for cancelling wideband acoustic echo' U.S. Patent Nos. 7,058,675 (2006) and 7,124,161 (2006): 'Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices' U.S. Patent Nos. 5,943,096 (1999) and 6,621,864 (2003): 'Motion vector based frame insertion process' U.S. Patent Nos. 5,832,131 (1998) and 5,991,455 (1999): 'Hashing-based vector quantization' U.S. Patent No. 5,587,710 (1997): 'Syntax based arithmetic coder and decoder' Throughout his career, Dr. Choo has been actively involved in both academic and industry collaborations. He has served as a technical consultant for numerous Silicon Valley companies including National Semiconductor (now Texas Instruments), Philips Semiconductor, Skybox Imaging (acquired by Google), Novariant (now AgJunction), and Ricoh Innovations. His industry experience informs his teaching approach, which emphasizes practical implementation considerations alongside theoretical foundations. Dr. Choo has also served as an expert witness in intellectual property court cases involving audio and video compression algorithms and FPGA hardware. Dr. Choo directs the FPGA/DSP AI/DL Laboratory at San José State University, which focuses on developing hardware-accelerated solutions for real-time AI applications. The lab maintains strong connections with Silicon Valley technology companies and provides students with hands-on experience in cutting-edge hardware design methodologies. Current research directions include autonomous vehicle navigation systems, medical imaging applications, and edge AI deployment strategies.
