Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.
Karthik R. Narasimhan is a Professor at Princeton University's School of Engineering and Applied Science in the Department of Computer Science. Previously, he earned his PhD from MIT under Regina Barzilay and served as a visiting research scientist at OpenAI during 2017-18. His research focuses on the intersection of language and decision-making, building autonomous agents that learn from both experience and human knowledge. His research spans multiple high-impact areas including language agents (Text-DQN, CALM, ReAct, Tree of Thoughts), reinforcement learning (h-DQN, Multi-Objective RL), and AI safety (Toxicity in ChatGPT, DataMUX). He has developed critical datasets and benchmarks such as WebShop, InterCode, SWE-bench, and SILG that have become standard evaluation tools in the field. Current work emphasizes agent capabilities, software engineering automation, and multimodal interaction. His publication trends show strong focus on practical agent deployment (SWE-agent, Tree of Thoughts), safety evaluation (Probing AI Safety), and efficiency improvements (DataMUX). Recent work increasingly addresses real-world challenges in software engineering, security, and human-AI collaboration through rigorous benchmarking. Co-author of foundational GPT (2018) paper Key developer of Text-DQN (2015), CALM (2020), ReAct (2022), Tree of Thoughts (2023) Creator of influential benchmarks: WebShop (2022), SWE-bench (2023), InterCode (2023) He actively advises students through Princeton's computer science program, with research supported by multiple grants focused on autonomous agent development and language-based decision systems. His GitHub repositories (nlp-datasets, text-world-player) demonstrate strong community engagement in open-source research tools. Current projects include advancing language agent capabilities through Reflexion (2023) and Tree of Thoughts (2023) frameworks while addressing critical safety and efficiency challenges.
Gert Cauwenberghs is a Professor of Bioengineering at the University of California San Diego (UCSD), affiliated with the Jacobs School of Engineering. He co-directs the Institute for Neural Computation and holds a visiting professorship at MIT. His research focuses on neuromorphic engineering, energy-efficient neural interfaces, and wearable biosensors. Key contributions include silicon-based adaptive neural circuits, implantable neural recording systems, and in-ear biosensing devices. Education: M.Eng. in Applied Physics (University of Brussels, 1988), M.S. and Ph.D. in Electrical Engineering (Caltech, 1989–1994). Prior roles include Professorships at Johns Hopkins University and Visiting Professor at MIT. Research Interests: Biomedical integrated circuits, neuromorphic computing, brain-machine interfaces, and energy-efficient neural systems. His work bridges neuroengineering and clinical applications, emphasizing adaptive intelligence and low-power designs. Recent Work: Development of femtojoule-efficient neural chips, high-density neural interfaces, and closed-loop wearable systems. Projects include neurobench benchmarking frameworks and RRAM-based neuromorphic hardware. Awards: NSF Career Award (1997), ONR Young Investigator (1999), PECASE (2000), IEEE Distinguished Lecturer (2003–2004). Grants & Labs: Active in NIH and DoD-funded projects, co-directs the UCSD Institute for Neural Computation. Collaborates with industry on neural interface technologies. Labs/Teams: Cauwenberghs Lab at UCSD focuses on integrated neuroengineering systems, including neural recording systems and neuromorphic computing architectures.
Michael O'Boyle is a Professor at the University of Edinburgh's School of Informatics, where he serves as Director of the ARM Research Centre of Excellence and the EPSRC Centre for Doctoral Training in Pervasive Parallelism. Holding an EPSRC Established Career Research Fellowship, he leads pioneering work in compiler technology for heterogeneous architectures, bridging theoretical advances with practical high-performance computing applications. Professor O'Boyle's research spans multiple cutting-edge areas including heterogeneous code discovery and optimization, neural machine translation for program synthesis, deep neural network system stack optimization, software-defined hardware, and compiler/architecture co-design. His approach integrates constraint analysis, program synthesis, and machine learning to address complex challenges in high-performance computing across diverse hardware platforms. His recent publications reveal a strong trend toward integrating machine learning with traditional compiler techniques, particularly in neural program synthesis, tensor optimization, and architecture-aware compilation. This work represents a paradigm shift in compiler design, moving from rule-based systems to learning-based approaches that can automatically adapt to diverse hardware targets. IEEE/ACM CGO 2025 Distinguished Paper Award for 'Tensorize: Fast Synthesis of Tensor Programs from Legacy Code' IEEE/ACM CGO 2024 Test of Time Award ACM GPCE 2023 Best Paper Award for 'C2TACO: Lifting Tensor Code to TACOM' ACM ASPLOS 2021 Distinguished Paper Award IEEE HPCA 2021 Best Paper Award for 'Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads' Professor O'Boyle has successfully mentored numerous PhD students who have secured prominent positions in academia (including at Cambridge, Edinburgh, Leeds, and McGill) and industry (including Meta, NVIDIA, Qualcomm, Huawei, and Microsoft). His research is supported by significant funding from EPSRC, ARM, and European projects including Bonseyes and Transmuter, demonstrating strong international recognition and industry impact. He leads the influential Compiler and Architecture Design (CArD) Group at the University of Edinburgh and is a founder of the HiPEAC Network of Excellence, which has grown into a major European initiative connecting researchers and practitioners in high-performance and embedded computing.
Gustavo Alonso is Full Professor at the Department of Computer Science (D-INFK) of ETH Zurich and Head of the Institute for Computing Platforms . He has been at ETH since 1995, first as a post-doc, then as Assistant Professor from April 1998, and promoted to Full Professor in October 2001. Within the Systems Group he leads the Information and Communication Systems Research Group . Education: 1989 – Telecommunications Engineering (undergraduate), Madrid Technical University (UPM-ETSIT), Spain 1992 – M.S. Computer Science, University of California, Santa Barbara (UCSB) 1994 – Ph.D. Computer Science, University of California, Santa Barbara (UCSB) Research Interests: His work spans databases, distributed systems, cloud-computing architecture, FPGAs, hardware acceleration for data science, parallel and reconfigurable computing . The group investigates how modern heterogeneous hardware—from GPUs to SmartNICs—can be integrated into data-processing systems to achieve orders-of-magnitude performance gains, energy savings, and new functionality such as in-network computation and serverless acceleration. Scientific Awards & Honors: Fellow of the ACM (Association for Computing Machinery) Fellow of the IEEE (Institute of Electrical and Electronics Engineers) Distinguished Alumnus, Department of Computer Science, UC Santa Barbara Four Test-of-Time / Most Influential Paper Awards across databases, programming languages, cloud computing, and software engineering Labs & Projects: He directs the Information and Communication Systems Research Group within the Systems Group ( systems.ethz.ch ). The lab develops open-source platforms such as Coyote v2 for FPGA abstractions, Shuhai for HBM benchmarking, and MicroRec for micro-second recommendation serving, while collaborating with industry on SmartNICs, serverless analytics, and cloud-scale data analytics.
Prof. Dr. Timothy Roscoe is a Full Professor in the Department of Computer Science at ETH Zurich. His research focuses on operating systems, networking, and distributed systems. He was inducted as an ACM Fellow in 2014 for contributions to these fields. Previously, he worked at Intel Research Berkeley, UC Berkeley (Adjunct Professor), and Sprint Labs. His work includes foundational contributions to systems like PlanetLab, P2 Declarative Networking, and the Nemesis OS. Roscoe holds a PhD from the University of Cambridge and has led projects in cloud computing, wide-area network measurement, and secure systems design. His current research emphasizes hardware-software co-design, formal verification of systems, and scalable memory architectures. Education: PhD in Computer Science, University of Cambridge (1995) Key Roles: Principal Researcher at Intel Berkeley Lab, Visiting Researcher at National ICT Australia Research Highlights: Contributions to distributed systems (PlanetLab), declarative networking (P2), and secure microkernels (seL4 integration). Current projects address challenges in disaggregated memory systems, coherent interconnects, and trustworthy embedded systems. Awards: ACM Fellow (2014), numerous grants and industry collaborations. Labs/Teams: Systems Group at ETH Zurich, focusing on OS design, hardware architectures, and formal methods.
Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology and serves as the Director of the 3D Systems Packaging Research Center. His research focuses on heterogeneous integration of microsystems, including 2.5D and 3D ICs and packaging technologies, with significant contributions to advanced cooling systems, electrical and photonic interconnects, and biosensor integration with CMOS. Dr. Bakir's research interests span heterogeneous microsystem design and integration, advanced cooling and power delivery for emerging architectures, electrical and photonic interconnect technologies, biosensor technologies, and nanofabrication. His work addresses critical challenges in next-generation electronics, enabling polylithic integration that concatenates heterogeneous ICs of various functionalities while mimicking monolithic-like densities. His research particularly focuses on co-design of thermal technologies, power delivery networks, and signaling networks for silicon nanoelectronic systems. His recent publications demonstrate strong trends in fused-silica stitch-chip technology for heterogeneous integration, with particular emphasis on RF and mm-wave applications, power delivery for AI accelerators, and thermal management solutions. His work bridges electrical engineering, materials science, and thermal management to solve critical bottlenecks in computing performance and efficiency. 2013 Intel Early Career Faculty Honor Award 2012 DARPA Young Faculty Award 2011 IEEE CPMT Society Outstanding Young Engineer Award 2012 National Academy of Engineering Frontiers of Engineering Symposium Invited Participant 2015 IEEE CPMT Society Distinguished Lecturer 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology More than 25 conference and student paper awards Twelve issued US Patents Dr. Bakir leads the Integrated 3D Systems Lab (I3DS) at Georgia Tech, which is actively researching advanced packaging, interconnects, electrical and thermal design, and system integration. His team has received significant recognition for their work, including multiple best paper awards from major conferences like ECTC, IITC, and CICC. The lab is currently seeking postdoctoral researchers and research faculty to advance next-generation electronics through collaborative research. His lab focuses on enabling the next phase of Moore's Law through polylithic integration, which concatenates heterogeneous ICs of various functionalities (digital, analog, photonic, and mm-wave) using advanced off-chip '2.5D' and '3D' heterogeneous interconnects and packaging. This work impacts applications in high-performance computing, machine learning, edge intelligence, autonomous vehicles, augmented/virtual reality, and healthcare.
Professor Hanumant Singh leads the Electrical and Computer Engineering department at Northeastern University, with a joint appointment in Mechanical and Industrial Engineering , and serves as Program Director for the Master of Science in Robotics. He earned his Ph.D. from MIT/WHOI Joint Program in 1995 and has conducted over 60 expeditions globally, focusing on marine geology, polar studies, and coral reef ecology. His research emphasizes field robotics , including SLAM, underwater manipulation, and imaging in extreme environments. He developed the Seabed AUV and Jetyak ASV , widely used in scientific research. His labs include the Field Robotics Lab and the Institute for Experiential Robotics . Research Interests: Machine Learning for Fisheries SLAM with dynamic objects Underwater imaging and manipulation Autonomous surface and aerial systems Polar and marine robotics Awards: ICRA Best Student Paper Award, IEEE Oceanic Engineering Society Distinguished Faculty Award (2025), Lifetime Achievement Award (2022), and IEEE Fellow status. His work has been featured in Nature Geoscience , Polar Biology , and media outlets like WGBH. Students & Collaborations: Advises students like Srinidhi Pattala (MS Robotics) and Dennis Giaya (PhD Computer Engineering). Collaborates with institutions on projects such as Antarctic sea ice thickness estimation and deep-sea submersible missions.
Sumeet Kumar Gupta is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University. His academic career spans from his current role to a prior Assistant Professorship at Pennsylvania State University (2014-2017) and an engineering position at Qualcomm Inc. (2012-2014). He holds a PhD in Electrical and Computer Engineering from Purdue University (2012), an M.S. from the same institution (2008), and a B.Tech in Electrical Engineering from IIT Delhi (2006). B.Tech, Electrical Engineering, IIT Delhi (2006) M.S., Electrical and Computer Engineering, Purdue University (2008) PhD, Electrical and Computer Engineering, Purdue University (2012) Dr. Gupta's research focuses on neuromorphic computing, low power variation-aware VLSI design in emerging nanotechnologies, device-circuit co-design, and nano-scale device modeling/simulations. His work addresses challenges in ferroelectric materials, crossbar arrays for deep neural networks, and energy-efficient AI hardware. Recent publications (2025-2024) highlight trends in: Ferroelectric HfO2/HZO thin films Compute-in-memory architectures Variability/stochasticity analysis Machine learning for device optimization Interconnect resistance/temperature effects AI hardware fault tolerance Scientific Awards & Recognitions: DARPA Young Faculty Award (2016) Early Career Professorship, Penn State (2014) 6th TSMC Outstanding Student Research Bronze Award (2012) Magoon Award (Purdue) Outstanding Teaching Assistant Award (Purdue, 2007) Intel PhD Fellowship (2009) His professional journey includes academic appointments at Purdue University (2020-present, Associate Professor) and Pennsylvania State University (2014-2017, Assistant Professor) after industry experience at Qualcomm Inc. (2012-2014). He maintains IEEE and EDS membership while publishing over 100 refereed works.
Ming-Syan Chen is a distinguished academic holding dual roles as a Distinguished Research Fellow and Director of the Research Center for Information Technology Innovation (CITI) at Academia Sinica, Taiwan, and a Distinguished Professor jointly appointed across multiple departments at National Taiwan University (NTU), including Electrical Engineering (EE), Computer Science and Information Engineering (CSIE), and the Graduate Institute of Communication Engineering (GICE). His career spans academia and industry, with prior roles as a research staff member at IBM Watson Research Center and leadership positions in Taiwan's technology sector. Education: He earned a B.S. in Electrical Engineering from National Taiwan University, followed by M.S. and Ph.D. degrees in Computer, Information, and Control Engineering from the University of Michigan, Ann Arbor. Research Interests: Chen's work focuses on databases, data mining, machine learning, multimedia networking, and cloud computing. He has authored over 350 papers and holds numerous patents, contributing to foundational advancements in query processing, data management, and networked systems. Award Highlights: Recipient of ACM and IEEE Fellowships, National Chair Professorship (lifetime honor), Teco Award, Pan Wen Yuan Distinguished Research Award, and IBM's Outstanding Innovation Award. His contributions span research, teaching, and technology commercialization. Leadership & Service: Former Dean of NTU's College of Electrical Engineering and Computer Science, CEO of Taiwan's Networked Communication Program, and Editor-in-Chief of the International Journal of Electrical Engineering. He has chaired international conferences and served on editorial boards of journals like IEEE TKDE and VLDB. Labs & Teams: Leads the Network Database Laboratory and collaborates on national initiatives in information and communication technologies. His research groups focus on data science, distributed systems, and social network analysis.
Matteo Sonza Reorda is a Full Professor at the Polytechnic University of Turin, affiliated with the Department of Automatic Control and Computer Science (DAUIN). He holds roles such as Partnership Agreement Coordinator with SMAT and has served as Vice-Rector for Research (2021–2024). His research focuses on fault tolerance, hardware reliability, and AI acceleration, with contributions to GPU/CNN reliability, self-test libraries, and defect-oriented testing. Education: M.S. in Electronics Engineering, Politecnico di Torino (1986) Ph.D. in Computer Engineering, Politecnico di Torino (1990) Research Interests: His work spans automatic test equipment, circuit reliability, GPU fault tolerance, neural network hardening, and embedded systems safety . He leads the Electronic CAD & Reliability Group and collaborates with institutions like the ISI Foundation and the National Research Council (CNR). Publications & Impact: With over 180 publications, his recent work emphasizes AI accelerator reliability, fault injection techniques, and safety-critical systems. Key trends include GPU resilience for CNNs, self-test library optimization, and radiation fault modeling in neural networks. Awards & Recognition: IEEE Fellow (2016–) Multiple best-paper awards at IEEE conferences (DDECS, DATE, etc.) Grants & Collaborations: Coordinator of EU projects (RESCUE, TUTORIAL) Partnerships with EDF, Marelli Europe, and SMAT Lead on National HPC/Quantum Computing Spoke 1 (2022–2025) Labs/Teams: Leads the CAD Group and collaborates with the French-Italian LIA LAFISI lab on hardware-software integration.
Babak Falsafi is a Full Professor at the School of Computer and Communication Sciences (IC) at EPFL, leading the Parallel Systems Architecture Laboratory (PARSA). He is a renowned expert in computer architecture, datacenter systems, and cloud-native server design. His research focuses on post-Moore era computing, emphasizing heterogeneous architectures, energy efficiency, and scalable IT infrastructure. Falsafi is the founder of EcoCloud, an EC-sponsored industrial-academic consortium investigating sustainable information technology. He holds ACM and IEEE fellowships, a Sloan Research Fellowship, and has contributed to major projects like Optimus Prime (data transformation acceleration), AstriFlash (flash-based online service systems), and Midgard (virtual memory re-design). His work spans hardware-software co-design, memory systems, and security. Falsafi advises numerous PhD students and collaborates with industry partners such as Google and Cavium. Key achievements include pioneering scalable multiprocessor architectures, snoop filters in IBM BlueGene, and spatial memory streaming in ARM cores. His lab develops open-source tools like QFlex for server simulation. He frequently presents at top conferences (HPCA, ISCA, MICRO) and chairs workshops on post-Moore infrastructure. Teaching roles include leading courses in computer architecture and parallel systems across multiple EPFL departments (SIN, EDIC, SSC, SMA). His work addresses datacenter challenges like the 'data tax' and mitigating latency through specialized accelerators.
Bernhard J. Berger is a Lecturer in the Department of Computer Engineering at the Institute of Embedded Systems, Hamburg University of Technology (TUHH). His research focuses on software security, static code analysis, machine learning, optimization, and research data management. He has held significant roles such as Program Committee member for ICPC 2025 and MSR 2025, and has received awards including the Best Reviewer Award (ICPC 2023) and Best Engineering Paper Award (SCAM 2019). His work spans interdisciplinary applications including maritime systems security, GPU-accelerated AI, and evolutionary algorithms. Recent studies emphasize AI-driven security tools (e.g., ML-SAST) and domain-specific language approaches to optimization (EvoAl). He has contributed to over 30 peer-reviewed publications, with notable work in IEEE Transactions on Software Engineering and Science of Computer Programming. Berger collaborates closely with industry through DAAD review committees and serves on artifact evaluation boards for ISSTA and ARES conferences. Education: Doctoral Thesis (2022), Diploma in Computer Science (2007) Key Projects: ArchSec tool suite, Threat Modeling Frameworks, Bauhaus static analysis methodology Lab Affiliation: Embedded Systems Design Group His advisory roles include Deputy of TUHH's Election Verification Committee and Session Chair at IEEE Congress on Evolutionary Computation 2023. Current research trends integrate machine learning with static analysis for automated vulnerability detection, while also exploring explainable AI techniques for neural network optimization.
Mariano Scazzariello is a Lecturer at KTH Royal Institute of Technology, Sweden, affiliated with the School of Electrical Engineering and Computer Science and the Department of Network and Systems Engineering. He teaches the course 'Network Systems with Edge or Cloud Datacenters (IK2227)'. His research focuses on advanced networking topics including machine learning in networks, high-speed packet processing, network emulation, and software-defined networking innovations. His work spans contributions to network emulation tools like Kathará and Megalos, stateful packet processing at terabit scales, and leveraging large language models (LLMs) for network configuration and vulnerability detection. Recent research emphasizes low-latency protocols (e.g., SRv6/DetNet integration) and GPU-centric networking on commodity hardware. Mariano’s publications (2020–2025) highlight expertise in network function virtualization, ASIC-based switching, and optimizing network configurations through AI-driven approaches. He has pioneered frameworks for evaluating routing protocols and virtualizing large network scenarios at scale.
Dr. Akhilesh Jaiswal serves as Assistant Professor of Electrical and Computer Engineering at the University of Wisconsin-Madison, where his research pioneers device-circuit co-design for next-generation computing systems. His work focuses on enabling extreme-edge intelligence through processing-in-pixel technology, in-memory computing architectures, and bio-inspired neuromorphic systems. His academic credentials include: PhD in Nano-electronics from Purdue University (2019) MS from the University of Minnesota (2014) Bachelor of Technology from Shri Guru Gobind Singhji Institute of Engineering and Technology (2011) Dr. Jaiswal's research program centers on revolutionizing edge computing through hardware innovations that integrate sensing and processing. His device-circuit co-design approach leverages alternate state variables to create energy-efficient systems for real-time applications, with particular emphasis on retina-inspired sensors and photonic memory architectures. This work bridges semiconductor physics with AI acceleration needs, targeting applications from autonomous systems to biomedical devices. Analysis of his 2023-2025 publications reveals dominant themes in photonic SRAM-based in-memory computing (40% of output), retina-inspired motion processing (30%), and secure hardware architectures (20%). His team consistently develops novel bitcell designs that enable XOR logic execution within memory arrays while maintaining compatibility with CMOS fabrication processes. Recent work shows increasing focus on biomedical applications of processing-in-pixel technology. His distinguished recognition includes: Three consecutive ISI Exploratory Research Awards (2020-2023) IEEE Brain Community Best Paper Award (2022) 27 issued US patents with multiple pending applications Nomination for USC Moore Inventor Fellowship (2022) Dr. Jaiswal actively mentors graduate researchers through ECE 790/890/990 courses while securing exploratory funding through ISI and Keston Foundation awards. His patent portfolio demonstrates exceptional translational impact, with industry game-changer classifications from USPTO. The 2022 VLSI-SoC nomination and multiple research highlights in major outlets validate his contributions to hardware security and neuromorphic vision sensors. His laboratory develops integrated hardware platforms combining magnetic tunnel junctions, photonic memory, and CMOS image sensors to create unified processing-in-sensor systems. Current projects include retina-inspired motion segmentation for event cameras and electro-optic frequency transducers for quantum computing interfaces, with strong industry collaboration through patent licensing.
