جستجوی استاد راهنمای دانشگاهی

• Video Coding
• Machine Learning
• FPGA Acceleration
• +۳ مورد دیگر

Jarno Vanne is a Professor at the Department of Computing Sciences, Faculty of Information Technology and Communication Sciences at Tampere University. His research focuses on video coding standards, real-time systems, and hardware acceleration, particularly in the context of FPGA implementations and open-source tools. He leads projects involving VVC (Versatile Video Coding), V-PCC (Volumetric Video Coding), and HEVC (High Efficiency Video Coding), with an emphasis on efficiency, low latency, and machine learning integration. Key research interests include point cloud compression, saliency-guided encoding, parallelization schemes, and real-time video communication protocols. His work often addresses challenges in multi-party video streaming, embedded systems, and encryption mechanisms for privacy protection. He has contributed to open-source projects like the UVG dataset, Kvazaar encoder, and CiThruS simulation frameworks. Recent publications highlight advancements in VVC intra encoding optimizations, machine learning-driven partitioning schemes, and FPGA-accelerated solutions for edge computing. His research bridges theoretical video coding algorithms with practical implementations, aiming to improve compression efficiency while maintaining real-time performance.

• High-Level Synthesis
• FPGA Design
• Hardware Engineering
• +۳ مورد دیگر

Sakari Lahti is a Lecturer in the Department of Computing Sciences at Tampere University, within the Faculty of Information Technology and Communication Sciences. His primary responsibilities include teaching digital logic and hardware design. He holds an ORCID identifier: 0000-0002-9915-4784 . Lahti's research focuses on High-Level Synthesis (HLS) for FPGAs, with emphasis on optimizing embedded systems, real-time applications, and digital signal processing. His work spans FPGA implementation techniques, compiler optimizations for HLS tools, and practical applications in media processing and wireless communications. Notable projects include real-time HEVC video encoding and nonlinear self-interference cancellation systems. His publications reflect a sustained contribution to FPGA-based hardware design, with a decade of work from embedded systems (2002) to modern C++ integration in HLS (2023). Collaborations include colleagues like Teemu Hämäläinen and Jari Vanne, focusing on bridging software and hardware design methodologies. His research also extends to educational aspects, such as real-world product development in system design courses. Lahti’s work is peer-reviewed and published in prestigious venues like IEEE Transactions and conferences like DDECS and ISCAS. His research unit is the Unit of Computing Sciences at Tampere University.

• Video Coding
• Machine Learning in Video Compression
• Energy-Efficient Encoding
• +۳ مورد دیگر

Alexandre Mercat is an Assistant Professor in the Department of Computer Engineering at Tampere University, within the Faculty of Information Technology and Communication Sciences. His research focuses on video coding, energy-efficient encoding, and real-time multimedia systems. He leads projects on open-source video encoders and standards, including contributions to HEVC, VVC, and V-PCC technologies. His work emphasizes machine learning integration, low-power hardware optimizations, and scalable distributed encoding frameworks. Key technical interests include improving video compression efficiency through algorithmic innovations, developing open-source tools like the UVG dataset and Kvazaar encoder, and addressing challenges in volumetric video communication and 3D point cloud encoding. His research spans theoretical algorithm design to practical implementations, with applications in virtual reality, live streaming, and edge computing. Recent projects include real-time saliency-guided video coding frameworks, energy reduction techniques for HDR streaming, and multi-layer VVC coding schemes for hybrid machine-human consumption. He also explores FPGA acceleration and parallelization strategies for distributed video encoding systems. No scientific awards are explicitly mentioned in the provided texts. While no formal advisees are listed, his research group likely involves students through open-source development and collaborative projects. His work integrates closely with industry standards bodies and open-source communities, emphasizing reproducible evaluation frameworks and end-to-end software tools.

• System-on-Chip (SoC) Design
• FPGA-Based High-Level Synthesis
• Real-Time Embedded Systems
• +۵ مورد دیگر

Timo Hämäläinen is a Professor of Computer Engineering at Tampere University, leading the Unit of Computing Sciences within the Faculty of Information Technology and Communication Sciences. He is a core member of the System-on-Chip research group and the Computer Engineering Team, actively contributing to the System-on-Chip Hub initiative. His research focuses on System-on-Chip (SoC) design methodologies, FPGA-based high-level synthesis, real-time embedded systems, and open-source hardware-software co-design frameworks like RISC-V and HEVC encoding. He has pioneered work on agile SoC development processes and validation techniques for large-scale hardware systems. Key research areas include: High-level synthesis (HLS) optimization for FPGAs Real-time processor architectures and context-switching latency reduction Formal verification of IP-XACT-compliant SoC designs Resilient RISC-V MPSoC implementations Hardware-accelerated algorithms for signal processing and networking His recent publications (2023-2025) emphasize agile SoC development frameworks, hardware-software co-design for real-time systems, and validation methodologies for large-scale embedded systems. He has contributed to open-source projects like Kvazaar HEVC encoder and the Kactus2 IP-XACT toolchain. Academic advising includes students such as Santéri Mäki-Äijö (formal verification), Arto Oinonen (RISC-V tooling), and Sakari Lahti (processor modeling). His work integrates academic research with industrial collaboration through frameworks like the Fault-slip-Through quality assessment methodology.

• FPGA
• HEVC Encoding
• Software-Defined Networking
• +۶ مورد دیگر

Arto Oinonen is a Lecturer at Tampere University , affiliated with the Faculty of Information Technology and Communication Sciences and the Department of Computing Sciences . His work bridges academic instruction and research in advanced computing technologies. Dynamic Resource Allocation in SDN Cloud Hardware Acceleration for HEVC and IPsec SystemVerilog and UVM Implementation Oinonen's research focuses on FPGA-based hardware acceleration for video encoding (HEVC) and network security protocols (IPsec) in cloud environments. His publications analyze optimization strategies for resource allocation, latency reduction, and energy efficiency in programmable logic architectures. He also contributes to educational frameworks for SystemVerilog and UVM in digital design training. Key collaborations include researchers at Tampere University's System-on-Chip Design group. His work has been cited in academic and patent literature, with a focus on practical implementations in cloud and networked systems.

• Microelectronics
• Computer Engineering
• Embedded Systems
• +۷ مورد دیگر

Dr. Ari Kulmala serves as Professor of Practice at Tampere University's Faculty of Information Technology and Communication Sciences in the Computing Sciences department. With extensive industry experience in System-on-Chip (SoC) architecture and design, he specializes in ASIC and FPGA development for applications spanning 5G telecommunications, cloud acceleration, machine learning, security, and ultra-low-power mobile chips. His research focuses on System-on-Chip (SoC) design , with particular emphasis on heterogeneous architectures, RISC-V implementations, and hardware-software co-design for autonomous systems. Recent work includes secure SoC development for nano-UAVs, FPGA-based cryptographic acceleration, and agile chip development methodologies. The article collection demonstrates expertise in SoC architecture (10+ years), with evolving focus from foundational network-on-chip analysis (2008-2009) to modern implementations in RISC-V (2023-2024), cloud security acceleration (2019), and VR/4K video processing (2017-2018). Key technical areas include clock domain management, resource sharing, and performance optimization across various domains. As an industry leader in chip development organizations, Kulmala has worked across Telecom infrastructure (5G) Cloud acceleration Machine learning/AI Security hardware Ultra-low-power IoT Mobile chip design His work spans both academic research and practical implementation, including patents and commercial applications.