Jianguo Wang is an Assistant Professor in the Department of Computer Science at Purdue University, joining in Spring 2021. His research focuses on database systems for the cloud and large language models, including disaggregated databases and vector databases. He holds a PhD from the University of California, San Diego, and has worked at Zilliz (Milvus) and Amazon Web Services (AWS). Education: PhD in Computer Science (UC San Diego, 2019), MPhil (Hong Kong Polytechnic University), BSc (Zhengzhou University) Research interests include Disaggregated Databases, Vector Databases for Large Language Models, and cloud-native systems. Notable work includes OpenAurora (an open-source Amazon Aurora prototype) and contributions to Milvus. He has received grants like the NSF CAREER Award and honors such as the IEEE TCDE Rising Star Award. Advising a team of students in database systems and teaching courses like CS592 (Disaggregated Database Systems) and CS440 (Large-scale Data Analytics). Serves on program committees for SIGMOD, VLDB, and ICDE.
José F. Martínez holds the Lee Teng-hui Professorship of Engineering at Cornell University's College of Engineering, where he leads research in computer architecture and systems. His roles include Vice Chair of ACM SIGARCH, IEEE Fellow, and past leadership roles in ISCA, MICRO, and IEEE Computer Society journals. He has received prestigious awards such as the NSF CAREER Award, IBM/Qualcomm Faculty Awards, and multiple teaching accolades including Tau Beta Pi Professor of the Year (2011). Education: Licenciado en Informática de Sistemas (1996), Universidad Politécnica de Valencia M.S. (1999) and Ph.D. (2002) in Computer Science, University of Illinois at Urbana-Champaign His research focuses on computer architecture , including microprocessors, multiprocessors, memory subsystems, embedded systems, and processing-in-memory (PIM) innovations. He co-leads the DARPA/SRC ACE Center for Evolvable Computing and NSF's CROPPS Center, and previously co-founded Cornell's Institute for Digital Agriculture (CIDA). His work bridges hardware-software co-design and sustainable computing. Key Contributions: Advancing energy-efficient multiprocessor architectures Developing PIM frameworks like PUMICE and Membrane Market-based resource allocation systems (e.g., XChange, ReBudget) His advising spans over 15 graduate students and has guided Merrill Presidential Scholars. Current research explores evolvable computing paradigms and AI hardware acceleration, reflecting his dual focus on foundational architecture and applied systems innovation.
Jingtong Hu is an Associate Professor at the Swanson School of Engineering, University of Pittsburgh, where he also holds the William Kepler Whiteford Faculty Fellowship. His research focuses on Cyber-Physical Systems and Infrastructure Security, with significant contributions to embedded systems, non-volatile memory architectures, and hardware/software co-design for energy-constrained environments. Dr. Hu received his PhD from the University of Texas at Dallas (2007-2013) and his Bachelor of Engineering from Shandong University (2003-2007). His research spans multiple interdisciplinary areas including energy harvesting systems, non-volatile processors, FPGA acceleration, and machine learning at the edge. His recent publications demonstrate a strong focus on algorithm-hardware co-design, particularly for vision transformers, federated learning, and non-volatile memory systems. His work often addresses the challenges of implementing AI on resource-constrained edge devices, with emphasis on energy efficiency, reliability, and performance optimization. The trend in his publications shows increasing focus on sustainable AI processing, heterogeneous computing architectures, and personalized machine learning for IoT applications. Selected Awards: IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award (2021) ACM SIGDA Meritorious Service Award (2019) Multiple Best Paper Award nominations at top conferences including DAC, ASP-DAC, and CODES+ISSS Dr. Hu's research has been supported by multiple grants focusing on energy-efficient computing, non-volatile memory systems, and hardware acceleration for machine learning. His collaborative work spans numerous institutions and involves interdisciplinary teams working at the intersection of computer architecture, embedded systems, and artificial intelligence. His publications show extensive collaboration with researchers at the University of Pittsburgh, particularly with Albert K. Jones and Yiyu Shi. His laboratory work focuses on implementing practical systems for energy harvesting powered devices, non-volatile processors, and hardware accelerators for machine learning applications. Current projects appear to emphasize sustainable AI processing at the edge, heterogeneous FPGA acceleration, and personalized federated learning for health monitoring applications.
Prof. Dr. Sebastian Steinhorst is an Associate Professor (W3-level with tenure) at the Technical University of Munich (TUM) within the Embedded Systems and Internet of Things group at the TUM School of Computation, Information and Technology . His research focuses on advancing the security, predictability, reliability, and interoperability of smart connected and autonomous systems, particularly for applications in Internet of Things (IoT) , Industry 4.0 , and automotive systems . PhD in Computer Science (2011) from Goethe University Frankfurt Postdoctoral roles at TUMCREATE Singapore (2011-2016) and Aarhus University (2016) Joined TUM in 2016 as Rudolf Moessbauer Tenure Track Professor His research areas include decentralized embedded systems, hardware/software co-design, modeling and verification of cyber-physical systems, security protocols for automotive networks, and time-sensitive networking (TSN) for industrial applications. Recent work explores blockchain-based data sovereignty, zero-knowledge proofs for vehicle authentication, and resilient architectures for autonomous systems. Key scientific contributions include the 2019 ACM TODAES Best Paper Award and pioneering work on CyberSecDome , LeapChain , and Simutack frameworks. He serves on editorial boards and conference committees, including co-organizing the Autonomous Systems Design initiative at DATE. His teaching portfolio spans lectures on System Design for IoT , Software Architecture for Distributed Systems , and IoT Security across multiple semesters. He also leads advanced seminars on embedded systems and IoT.
Marina Blanton is an Associate Professor in the Department of Computer Science and Engineering at the University at Buffalo, and Faculty Director of Women in Science and Engineering within the School of Engineering and Applied Sciences. She holds a PhD in Computer Science from Purdue University (2007), along with multiple advanced degrees in Computer Science and Electrical Engineering from prestigious institutions in the US and Russia. Her research focuses on applied cryptography, information security, and privacy-preserving computation and outsourcing. She has pioneered work on secure multi-party computation protocols, privacy-preserving biometric authentication, and secure data analytics across distributed systems. Her contributions include foundational frameworks like PICCO, a compiler for private distributed computation, and advancements in protocols for genomic data analysis and floating-point secure computation. Blanton has been recognized with numerous awards, including IEEE and ACM Senior Membership (2016/2015), the ACM CCS Test of Time Award (2015), and the AFOSR Young Investigator Award (2013). Her research has been supported by grants such as NSF SaTC awards and AFOSR funding. Her work emphasizes practical implementations of secure computation, with applications in healthcare, biometrics, and distributed data systems. She has advised numerous students and contributed to educational initiatives promoting women in STEM through her leadership roles.
Cristian Cadar is a Professor in the Department of Computing at Imperial College London, leading the Software Reliability Group . His research focuses on improving software reliability and security through practical techniques in software engineering, computer systems, and program analysis. Education: Ph.D. in Computer Science, Stanford University M.Eng. in Computer Science, MIT B.S. in Computer Science and Mathematics, MIT His research interests center on software engineering and software security , particularly symbolic execution , dynamic symbolic execution (DSE) , and multi-version execution . Current work explores techniques for scalability, constraint solving, and runtime security in software systems. Key trends in his recent articles include optimizing symbolic execution for testing, addressing path explosion in constraint-based test generation, and advancing multi-version execution for dynamic software updates. His publications also cover program analysis , automated testing , and formal methods for software reliability. Awarded prestigious honors such as the Humboldt Research Award (2024) , ERC Consolidator Grant (2018) , and IEEE New Directions Award (2022) . Other accolades include the BCS Roger Needham Award (2019) and SIGOPS Hall of Fame (2018) . Cadar supervises PhD and postdoctoral researchers in software reliability and security. His group has secured grants from the ERC and EPSRC , including a Consolidator Grant (2018) and Early-Career Fellowship (2013) . He actively contributes to conference organizing committees and editorial boards. The Software Reliability Group at Imperial College, led by Cadar, specializes in techniques like KLEE and EXE for automated testing. Their work has been adopted by industry partners such as Fujitsu, IBM, and Microsoft, particularly in runtime security tools like WIT .
Helen Xu is an Assistant Professor at Georgia Tech's School of Computational Science and Engineering (College of Computing). She holds a Ph.D. from MIT (2022) under Charles E. Leiserson and was a Grace Hopper Postdoctoral Fellow at Lawrence Berkeley National Lab (2022). Her research focuses on parallel algorithms, cache-efficient data structures, and high-performance computing. Xu has interned at Microsoft Research, NVIDIA Research, and Sandia National Laboratories, and her work has been supported by prestigious fellowships including the National Physical Sciences Consortium and Chateaubriand awards. **Education**: Ph.D., Computer Science, MIT, 2022 Postdoctoral Research, Lawrence Berkeley National Lab (2022) **Research Interests**: Parallel and cache-friendly algorithms Dynamic graph and data structure optimization Algorithm performance engineering Sparse matrix/tensor operations **Awards**: Grace Hopper Postdoctoral Scholar (2022), Best Artifact Award (PPoPP 2024), National Physical Sciences Consortium Fellowship, Chateaubriand Fellowship. **Advising & Teaching**: Advises PhD/M.S. students in parallel computing and high-performance systems. Teaches courses like CSE 6220 (Introduction to HPC) and CSE 6230 (HPC Tools). Supervised MIT M.Eng. projects on BP-Trees and parallel prefix sums. **Labs/Teams**: Active in Georgia Tech's High-Performance Computing community, collaborating with researchers like Aydın Buluç and Prashant Pandey on graph containers and dynamic data structures.
Shantanu Dutt is a full Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Chicago , located in Chicago, IL. His office is in 930 SEO at 851 S. Morgan St, and he can be reached at dutt@uic.edu . Education Ph.D. in Computer Science and Engineering, University of Michigan, Ann Arbor (1990) M.Tech. in Computer Engineering, Indian Institute of Technology Kharagpur (1984) B.E. in Electronics and Communication Engineering, Maharaja Sayajirao University of Baroda (1983) Research Interests Professor Dutt’s research agenda centers on VLSI Computer-Aided Design (CAD) , with particular emphasis on physical design and incremental synthesis targeting both ASICs and FPGAs. He explores discrete optimization techniques to solve placement, routing, and partitioning problems. Another major thrust is FPGA built-in self-test (BIST) and trusted design , ensuring provable diagnosability and security against hardware Trojans. He also investigates fault-tolerant computing at both chip and system levels, and develops parallel and distributed computing algorithms for scalable performance. Scientific Awards 1996 Best Paper Award , ACM/IEEE Design Automation Conference, for “A probability-based approach to VLSI circuit partitioning” 1995 Most Influential Paper Award , Fault-Tolerant Computing Symposium, for “Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures” Research Impact and Funding Professor Dutt has published extensively in top-tier journals (IEEE TVLSI, ACM TRETS, IEEE TCAD) and premier conferences (ICCAD, DAC, DATE, FTCS). His work has shaped incremental placement, timing-driven routing, FPGA security, and fault-tolerant multiprocessor architectures. While specific grant numbers are not listed, the breadth and longevity of his publication record indicate sustained funding from NSF, industry, and other agencies. Laboratory and Collaborations Although no formal laboratory name is provided, Professor Dutt’s research is conducted within the ECE department’s VLSI CAD and Fault-Tolerance groups, collaborating with graduate students and colleagues across the US and internationally.
Michela Becchi is an Associate Professor in the Department of Electrical and Computer Engineering at North Carolina State University. She specializes in computer architecture, systems software, and applications, with a focus on heterogeneous systems, parallel algorithms, and acceleration techniques for bioinformatics, pattern recognition, and quantum computing. Her work spans multi-core CPUs, GPUs, FPGAs, and distributed clusters, emphasizing the boundary between hardware and software design. Dr. Becchi holds a Ph.D. and Master’s degree in Computer Engineering from Washington University in St. Louis (2009) and a Bachelor’s degree in Computer Engineering from Politecnico di Milano, Italy (2000). Her research has been recognized with prestigious awards, including the NSF CAREER Award (2015) and the University of Missouri System President Award for Early Career Excellence (2016). Her research interests include compiler and runtime techniques for heterogeneous systems, acceleration of bioinformatics algorithms, and high-speed networking applications. She has pioneered frameworks for efficient data transformation, GPU-accelerated compression, and memory-efficient graph algorithms for quantum computing. Her work also explores thread coarsening, mixed-precision auto-tuning, and secure multi-core processor design. Key contributions include the PILOT runtime system for GPU memory management, the GPU-FPtuner auto-tuner for floating-point applications, and innovative approaches to automata processors for genomic analysis. Her publications emphasize reproducible accuracy in scientific simulations and the optimization of irregular applications on many-core platforms.
Peter Dinda is a Professor in the Department of Computer Science at Northwestern University , with a secondary appointment in the Department of Electrical and Computer Engineering . He has authored over 130 scientific papers, holds five patents, and is a Fellow of the IEEE . As the former head of the Computer Engineering and Systems division, he has contributed extensively to experimental computer systems. Education: B.S. in Electrical and Computer Engineering from the University of Wisconsin Ph.D. in Computer Science from Carnegie Mellon University Research Focus: Experimental computer systems, particularly parallel and distributed systems , virtualization , operating systems , and empathic systems that integrate user satisfaction with systems-level decision-making. His work also spans compiler design, memory management, and hardware-software co-design for performance optimization. Recent Trends: His publications emphasize virtualization efficiency, memory protection frameworks, parallel programming language design, and power management in heterogeneous computing environments. Key areas include exascale systems, IoT privacy, and physiological sensor-based user modeling. Scientific Awards: Fellow, IEEE Leadership: Served as Director of Graduate Studies and previously led the Computer Engineering and Systems division.
Alastair F. Donaldson is a Professor and Director of Research in the Department of Computing at Imperial College London, where he leads the FastPL research group. His work bridges formal methods, software testing, and programming languages, with a focus on enhancing the reliability of high-performance and parallel software systems. He has held key roles including Director of Research (since 2023) and previously served as Lecturer (2011–2014), Senior Lecturer (2014–2017), and Reader (2017–2020) before being promoted to Professor in 2020. His research interests include formal verification, compiler testing, GPU programming, concurrency, and fuzzing. He has made significant contributions to the verification of GPU kernels, metamorphic testing of graphics drivers, and the development of tools like GPUVerify and GraphicsFuzz. His work combines theoretical rigor with practical impact, demonstrated by the acquisition of his startup GraphicsFuzz by Google in 2018 and his subsequent roles as Senior Software Engineer and Visiting Researcher at Google. His recent publications reflect a sustained focus on compiler and system reliability, with trends in fuzzing, formal specification, and automated testing of complex systems such as WebGPU, CXL cache coherence, and large language models for code generation. His work increasingly integrates empirical validation with formal techniques to uncover subtle bugs in real-world systems. Scientific awards and recognitions include: 2017 BCS Roger Needham Award EPSRC Early Career Fellowship Fellow of the British Computer Society Best Paper awards at EuroSys 2024, MET 2021, IISWC 2019, IWOCL 2019, and ICST 2016 Best Industry Paper at ICST 2024 ACM SIGSOFT Distinguished Paper at ISSTA 2023 ACM SIGPLAN Most Influential OOPSLA Paper Award (2012 paper), awarded in 2022 Best Student Paper at PPoPP 2014 He has advised numerous PhD students and leads a vibrant research group. He has secured significant research funding and collaborates extensively with industry and academia. His service includes leadership roles such as General Chair of PLDI 2020, PC Chair of ECOOP 2019, and Steering Committee Chair of PLDI (2022–2025). He also serves on the advisory board of PACM-PL and on program committees for top venues including POPL, OOPSLA, PLDI, ICSE, and ISSTA. He leads the FastPL research group, which focuses on the design and implementation of programming tools and techniques for reliable software. The group conducts cutting-edge research in compiler testing, formal methods, and high-performance systems, fostering collaboration across academia and industry.
Xiaoming Li is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Delaware , focusing on compiler optimization, GPU computing, and hardware-software interaction. His work bridges machine learning with code generation to enhance program efficiency. B.S. and M.E. from Nanjing University (1998, 2001) Ph.D. in Computer Science from University of Illinois at Urbana-Champaign (2006) Research interests include: Compiler optimizations for static and dynamic code transformation Machine learning-driven code generation techniques FFT algorithms for sparse and hybrid systems Non-traditional compilers for SAT solvers and virtual machines GPU acceleration for large-scale computational problems His publications span 15 years , emphasizing: FFT optimization across GPU/CPU architectures Compiler techniques for heterogeneous systems Adaptive scheduling and error resilience Integration of empirical and model-driven approaches Notable awards: NSF CAREER Award (2008) Best Paper Award at ADAPT Workshop (2013) Advising highlights: Current students: Ryan Taylor, Sha Li, Shuo Chen, Yuanfang Chen, Chao Yang, Chaoyu Chen Graduates: Liang Gu (FFT Libraries), Jakob Siegel (GPGPU Frameworks), Murat Bolat (Context-Aware Compilation)
Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.
Chester Rebeiro is an Associate Professor at the Department of Computer Science and Engineering within the Indian Institute of Technology Madras . His work spans hardware and software security with a focus on cryptographic implementations and microarchitectural vulnerabilities. Research interests include hardware security, applied cryptography, side channel analysis, and operating system security. He develops frameworks for automatic vulnerability detection and mitigation in cryptographic systems. Editorial Board: Associate Editor at Journal of Hardware and Systems Security (Springer, 2021-2024) Conference Leadership: General Co-Chair for SPACE 2024, Program Co-Chair for ATS 2024, and Program Co-Chair for INDOCRYPT 2023 Professional Activities: Organizer of e-CTF Embedded Capture The Flag and contributor to cybersecurity workshops across India and abroad Scientific contributions highlight two major awards: a Distinguished Paper Award at USENIX Security 2024 and a Best Paper Award at IEEE HOST 2020. His research focuses on practical security solutions for processors and cryptographic systems. Advising includes mentoring 11 PhD students and 7 MS by Research candidates, with notable co-guided projects in fault attack detection and side-channel mitigation. He actively contributes to educational initiatives through courses on Secure Processor Microarchitecture and Operating Systems.
Bruno Tiago da Silva Gomes is a Researcher in the Department of Electronics and Informatics at Vrije Universiteit Brussel (VUB), Belgium. His work focuses on FPGA-based hardware acceleration, biomedical signal processing, and embedded systems. He leads several high-impact projects, including ENACT (environmental health interventions) and Tech4Health (future health technologies). His research spans FPGA design, machine learning acceleration, and real-time signal processing. Education: PhD in Electronics and Informatics (2019, VUB), supervised by Professors Touhafi and Braeken. His thesis addressed streaming application acceleration on FPGAs. Research interests include Field-Programmable Gate Arrays (FPGA), biomedical sensors (e.g., photoplethysmography), beamforming, and high-level synthesis. He has co-authored over 60 publications and holds an h-index of 439. Key projects include OZR4103 (power-efficient AI for biomedical applications) and NSIS3 (decarbonisation technologies). His work integrates hardware-software co-design for edge computing and secure TinyML systems. Advising includes a Master’s thesis on PPG signal analysis. He contributes to datasets like the AMIVU Acoustic Map Imaging Dataset.
