Marco Vaccaمشاهده پروفایل
دانشیار
- Logic-in-memory
- Machine learning
- Nanocomputing
- +۷ مورد دیگر
Marco Vacca is an Associate Professor in the Department of Electronics and Telecommunications (DET) at Politecnico di Torino and a member of the Interdepartmental Center PIC4SeR - PoliTO Interdepartmental Centre for Service Robotics. His work bridges electronics, nanotechnology, and computing architecture with a focus on innovative solutions to the memory wall problem. His research spans Logic-in-memory computing, Machine learning hardware acceleration, and Nanocomputing with specific emphasis on circuit architectures for probabilistic computing, magnetic devices, hybrid technologies integration, and CAD tools for emerging technologies. Dr. Vacca leads research in RISC-V extensions, hardware accelerators for AI, and autonomous robot systems for agricultural applications through the VLSILAB research group. Recent publications reveal a strong trend toward solving fundamental computing challenges through nanoscale innovations, particularly in memory-centric architectures, molecular field-coupled computing, and novel transistor technologies. His work demonstrates how logic-in-memory approaches can overcome traditional von Neumann limitations while improving energy efficiency for AI workloads. Editorial board member of ELECTRONICS (2021-2023) Program committee member for Design, Automation and Test in Europe Conference (DATE) 2020-2021 Dr. Vacca supervises PhD student Alessandro Varaldi working on 'Hardware AI Accelerators for Automotive Applications' and has led significant research projects including 'Device for Storage and Processing Data and Related Method' (2020-2021) and 'Quantum Computing and Quantum Communication: State of the Art and Applications in the Telco Sector' (2020). His grant portfolio shows strong industry and competitive funding support. As a core member of the VLSILAB research group, Dr. Vacca contributes to advancing VLSI theory and design applications with particular focus on implementing Big Data, Machine Learning, and Neural Networks in specialized hardware architectures that push the boundaries of conventional computing.
