جست‌وجوی استاد و پژوهشگر

Andrew Childsمشاهده پروفایل

استاد

• Quantum Algorithms
• Quantum Information Processing
• Quantum Simulation
• +۲ مورد دیگر

Andrew Childs is a Professor at the University of Maryland, affiliated with the Department of Computer Science and the Institute for Advanced Computer Studies (UMIACS). He serves as Director of the NSF Quantum Leap Challenge Institute for Robust Quantum Simulation (RQS) and is a Fellow at the Joint Center for Quantum Information and Computer Science (QuICS). His research focuses on quantum algorithms for simulating physical systems, algebraic problems, and quantum walk protocols, with applications in quantum computing and computational complexity. University of Maryland Institute for Advanced Computer Studies (UMIACS) Joint Center for Quantum Information and Computer Science (QuICS) NSF Quantum Leap Challenge Institute for Robust Quantum Simulation Childs' research spans quantum simulation, quantum Fourier transform, phase estimation, and Hamiltonian dynamics. He has developed techniques to reduce quantum computational resources for simulating quantum systems and explored limitations of quantum computers through hidden subgroup problems and non-unitary dynamics. His publications cover diverse areas including quantum walk optimization, Hamiltonian simulation methods, and applications to cryptography and condensed matter physics. Recent works address spatial search algorithms, product formulas for commutators, and quantum routing protocols. As an educator, Childs has taught courses on quantum algorithms and information processing at both the University of Maryland and University of Waterloo, with lecture notes and materials spanning multiple years. Contact: amchilds@umd.edu | Office: ATL 3359 | Affiliated with University of Maryland's quantum research institutes.

• Reconfigurable Computing
• Field-Programmable Gate Arrays (FPGA)
• High-Level Synthesis
• +۳ مورد دیگر

Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.

Baker Mohammadمشاهده پروفایل

استاد

• Very-Large-Scale Integration (VLSI)
• Hardware Accelerators for Artificial Intelligence
• Hardware Security
• +۷ مورد دیگر

Prof. Baker Mohammad serves as Professor and Director of the System on Chip Lab in the Department of Computer and Information Engineering at Khalifa University. With over 15 years of industrial experience at Intel and Qualcomm designing microprocessors and DSP chips, he bridges academic research with real-world engineering challenges in high-performance computing and low-power systems. His educational background includes: Ph.D. in Electrical and Computer Engineering, University of Texas at Austin (2008) M.S. in Electrical and Computer Engineering, Arizona State University B.S. in Electrical Engineering, University of New Mexico Dr. Mohammad's research spans cutting-edge domains where VLSI design converges with AI acceleration and emerging memory technologies . His work pioneers Memristor applications in environmental sensing (radiation, vacuum, glucose) and neuromorphic computing, while advancing energy harvesting systems for wearable electronics. The integration of in-memory computing with security primitives represents a paradigm shift in hardware design, moving beyond traditional CMOS limitations. His publication trajectory reveals accelerating focus on self-powered neuromorphic systems and RRAM-based architectures, with recent work (2021-2023) emphasizing hardware-software co-design for edge AI. Over 75% of his recent publications involve cross-disciplinary collaborations spanning materials science, chemistry, and biomedical engineering. Notable scientific recognition includes: IEEE TVLSI Best Paper Award 2016 IEEE MWSCAS Myrill B. Reed Best Paper Award Qualcomm Qstar Award for Performance Leadership KUSTAR IP Excellence Award Multiple SRC Techon Best Session Papers As a dedicated mentor, he has supervised over 15 graduate students while securing competitive funding from Khalifa University, ADEK, Qualcomm, Tii, and UAE space agencies. His grant portfolio demonstrates exceptional translational impact, converting fundamental research in memristive devices into drone flight computers and medical sensors. Current projects integrate academic rigor with industrial deployment timelines. The System on Chip Lab operates as a multidisciplinary hub where semiconductor physicists collaborate with AI researchers to develop RISC-V-based secure processors and piezoelectric nanogenerator systems. Recent expansions include partnerships with Tii for aerospace applications and medical device startups for glucose monitoring technology.

Oliver Diesselمشاهده پروفایل

دانشیار

• Reconfigurable Hardware
• Computer Architecture
• Digital Systems
• +۶ مورد دیگر

Associate Professor Oliver Diessel is a faculty member at the University of New South Wales (UNSW) within the School of Computer Science and Engineering. He has been actively teaching and conducting research at UNSW since at least 2000, with teaching experience spanning various computer architecture and digital systems courses. Dr. Diessel completed his education at the University of Newcastle, Australia, earning a B.E. (Computer, Hons) and B.Math. in 1991, followed by a PhD in 1998. His academic career has focused on reconfigurable computing systems and computer architecture. His primary research interests center around the design, test, and implementation of digital systems in reconfigurable logic devices called Field-Programmable Gate Arrays (FPGAs). Specifically, he focuses on dynamically reconfigurable digital systems where circuits can be modified while the system is operational. His work aims to develop architectures, design methods, and tools that enhance the benefits and reduce the costs of reconfigurable systems. Current research projects include fault-tolerant FPGA-based systems for space applications and fine-grained accelerators for heterogeneous devices. Dr. Diessel has published extensively with 2 books, 1 book chapter, 16 journal articles, 67 conference papers, 1 edited conference proceedings, and 7 conference presentations to his credit. His publications reflect a strong emphasis on reconfigurable technology, computer architecture, and electronic design automation. As a supervisor, Dr. Diessel currently mentors two MPhil students: Tong Wu working on Runtime reconfiguration and Junning Fan working on Fault-tolerance of FPGA-based applications. He has previously supervised six students to completion. His supervision interests include reconfigurable technology and systems, electronic design automation, and computer architecture. Dr. Diessel is an active member of the professional community, serving on the Editorial Board of ACM Transactions on Reconfigurable Technology and Systems and as an IEEE Member. He has taught numerous courses including Configurable Systems (COMP4601), Computer Architecture (COMP3211, COMP4211), Digital Systems (COMP3222), and FPGA Implementation of Digital Systems using Verilog.

• Electrical and Electronic Engineering
• Computer Hardware
• Computer Software
• +۷ مورد دیگر

Professor Peter Y. K. Cheung is a Professor of Digital Systems at Imperial College London, holding dual affiliations within the Department of Electrical and Electronic Engineering and the Dyson School of Design Engineering. His work focuses on reconfigurable systems, FPGA architectures, and high-level synthesis tools. He co-founded one of the UK's leading FPGA research groups with Professor Wayne Luk, addressing challenges in variability mitigation, reliability, and application-specific FPGA deployments. His research spans Field-Programmable Gate Arrays (FPGAs) Reconfigurable computing Neural network acceleration Cryptographic protocols Embedded systems He has pioneered techniques such as logic shrinkage for FPGA-based neural networks and developed frameworks like LUTNet for efficient inference. His contributions also include fault-tolerant FPGA designs and methodologies for distributed computation protocols. Key collaborations include work with the Department of Computing on FPGA-based AI acceleration and cybersecurity applications. His recent work explores edge computing, secure decentralized systems, and pandemic modeling using adaptive control strategies. Notable projects include the DSCS protocol for secure distributed computation, acceleration of gravitational wave detection algorithms, and energy-efficient CNN implementations. His research bridges hardware-software co-design with real-world applications in healthcare, finance, and aerospace.

Callie Haoمشاهده پروفایل

استادیار

• Software/Hardware Co-design
• Reconfigurable Computing
• Graph Computing
• +۵ مورد دیگر

Callie Hao is an Assistant Professor in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology since 2021, holding the ON Semiconductor Junior Professorship. Her research bridges hardware efficiency and algorithmic innovation with significant industry and federal recognition. Education: Ph.D. in Electrical Engineering, Waseda University (2017) M.S. and B.S. in Computer Science and Engineering, Shanghai Jiao Tong University Research Focus: Dr. Hao pioneers software/hardware co-design for edge AI, specializing in hardware-efficient machine learning algorithms, FPGA-based reconfigurable computing, graph neural networks, and electronic design automation (EDA). Her work emphasizes neural architecture search, high-level synthesis optimization, and memory-efficient systems for embedded and IoT applications, driven by the philosophy that "1 + 1 > 2" for transformative efficiency gains. Publication Impact: Her 15 most recent publications (2023-2026) reveal a strategic shift toward machine learning-driven EDA tools, with 60% focused on high-level synthesis frameworks and 40% on graph neural network acceleration. Key trends include simulation speed breakthroughs (LightningSim), automated accelerator generation (GNNBuilder), and cryptographic hardware innovations (Cryptonite), predominantly published in top-tier venues like MICRO, ICCAD, and DAC. Awards & Recognition: NSF CAREER Award (2024) and Intel Rising Star Faculty Award (2023) Best Paper Awards at MLCAD 2024 and GLSVLSI 2021 ON Semiconductor Junior Professorship (2025) and Sutterfield Family Early Career Professorship (2022) DAC-SDC competition championships (2018-2020) Mentorship & Funding: Dr. Hao advises 8+ Ph.D. students in the Sharc Lab, with Rishov Sarkar winning the Oscar P. Cleaver Award and Qualcomm Innovation Fellowship. Her research is funded by DARPA (2021) for ultra-light video intelligence systems and supported by industry awards from Amazon and Sony. She actively serves on program committees for DAC, ICCAD, and DATE conferences. Lab Leadership: As director of the Sharc Lab (Software/Hardware Co-design lab), she cultivates interdisciplinary research at the intersection of FPGA design, machine learning, and EDA, requiring expertise in Verilog/HLS, GNNs, and compiler technologies while maintaining strict focus on real-world hardware implementation.

Jason H. Andersonمشاهده پروفایل

استاد

• Computer Engineering
• Electrical Engineering
• Computer-Aided Design (CAD)
• +۳ مورد دیگر

Professor Jason H. Anderson is a faculty member in the Department of Electrical & Computer Engineering (ECE) at the University of Toronto, affiliated with the Faculty of Applied Science & Engineering. He specializes in computer engineering, with a focus on field-programmable gate arrays (FPGAs) and related computer-aided design (CAD) tools. BSc in Computer Engineering from the University of Manitoba MASc and PhD in Electrical & Computer Engineering from the University of Toronto His research spans FPGA architecture, circuit design, and CAD tool development. He has contributed to strategic R&D projects through his academic and industry roles. Scientific awards include multiple Best Paper Awards at IEEE and ACM conferences (2017, 2014, 2011, 2010, 2009), the Xilinx Ross Freeman Award (2000), and teaching accolades such as the Gordon Slemon Award (2012) and several ECE Departmental Teaching Awards (2009-2014). He served as General Chair and Program Chair for leading FPGA conferences. As Chief Scientific Advisor and Co-Founder of LegUp Computing Inc., he bridges academic research with industry innovation. He is a licensed Professional Engineer in Ontario and an active IEEE/ACM member.

Danial Chitnisمشاهده پروفایل

مدرس

• Microelectronics
• Biomedical Engineering
• Quantum Technology
• +۳ مورد دیگر

Dr. Danial Chitnis is a Chancellor's Fellow and Lecturer in Electronics at the School of Engineering, University of Edinburgh. He holds a DPhil in Engineering Science from the University of Oxford (2013) and has expertise in microelectronics, biomedical engineering, and quantum imaging. His research focuses on SPAD arrays, time-of-flight sensors, and wearable optical systems for biomedical applications. Education: BSc in Electronics Engineering, Chamran University of Ahvaz (2002–2007) MSc in Advanced Microelectronics Systems Engineering, University of Bristol (2007–2008) DPhil in Engineering Science, University of Oxford (2009–2013) Research Interests: Single-Photon Avalanche Diode (SPAD) arrays for optical communications and biomedical imaging Quantum-enhanced imaging via QuantIC Hub Wearable sensors for near-infrared spectroscopy (NIRS) AI-driven automation in test and measurement systems Articles Trends: Recent work emphasizes AI integration in electronics design, photon-counting receivers for 6G networks, and portable biomedical devices. Notable contributions include SYCL-based acceleration of circuit simulations and FPGA-driven time-to-digital converters. Grants & Collaborations: Principal Investigator of multiple grants, including EPSRC-funded projects on AI-enhanced human-machine interfaces and quantum technology applications. Collaborates with UCL, QuantIC, and industry partners like Keysight Technologies. Labs/Teams: Co-investigator at QuantIC, the UK Quantum Technology Hub in Quantum Enhanced Imaging. Leads interdisciplinary research on detector arrays and systems for quantum physics and consumer cameras.

• Electronics Engineering
• Signal Processing
• Biomedical Engineering
• +۳ مورد دیگر

Bruno Tiago da Silva Gomes is a Researcher in the Department of Electronics and Informatics at Vrije Universiteit Brussel (VUB), Belgium. His work focuses on FPGA-based hardware acceleration, biomedical signal processing, and embedded systems. He leads several high-impact projects, including ENACT (environmental health interventions) and Tech4Health (future health technologies). His research spans FPGA design, machine learning acceleration, and real-time signal processing. Education: PhD in Electronics and Informatics (2019, VUB), supervised by Professors Touhafi and Braeken. His thesis addressed streaming application acceleration on FPGAs. Research interests include Field-Programmable Gate Arrays (FPGA), biomedical sensors (e.g., photoplethysmography), beamforming, and high-level synthesis. He has co-authored over 60 publications and holds an h-index of 439. Key projects include OZR4103 (power-efficient AI for biomedical applications) and NSIS3 (decarbonisation technologies). His work integrates hardware-software co-design for edge computing and secure TinyML systems. Advising includes a Master’s thesis on PPG signal analysis. He contributes to datasets like the AMIVU Acoustic Map Imaging Dataset.

Stephen Brownمشاهده پروفایل

استاد

• Field-Programmable Gate Arrays (FPGAs)
• Computer Architecture
• CAD Algorithms
• +۴ مورد دیگر

Stephen Brown is a Professor at the University of Toronto within the Department of Electrical and Computer Engineering under the Faculty of Applied Science and Engineering. He earned his B.A.Sc and M.A.Sc in Electrical Engineering from the University of Toronto and New Brunswick, respectively, and a Ph.D. in Electrical Engineering from the University of Toronto (1992). His career spans over two decades in academia and industry collaboration. Education : B.A.Sc, University of New Brunswick M.A.Sc, University of Toronto Ph.D, University of Toronto Professor Brown’s research focuses on field-programmable gate arrays (FPGAs) , CAD algorithms , and computer architecture , with applications in machine learning and high-level synthesis . He is a principal investigator in the LegUp project , an open-source high-level synthesis framework that bridges software and hardware design. His work also extends to optimizing FPGA interconnect delays, physical synthesis, and logic block architectures. Key trends in his publications include advancements in high-level synthesis tools, FPGA architecture evaluation, and timing-driven design methodologies. His contributions often intersect with design automation , resource sharing , and embedded systems . Scientific Awards : NSERC 1992 Doctoral Prize Hart Professorship for Innovation in Teaching (2017) Multiple teaching excellence awards Best Paper Award at ICCAD 1990 Best Paper Award nomination at Canadian Conference on VLSI (1989) As Director of the FPGA University Program at Intel Corporation, he leads industry-academia initiatives. His teaching portfolio includes courses like ECE253 (Digital Logic) and ECE1733F (Switching Theory).

• Hyperdimensional Computing
• Neuromorphic Hardware
• In-Memory Computing
• +۳ مورد دیگر

Paul R. Genssler is a Dr.-Ing. researcher at the Chair of AI Processor Design (AI-Pro) within the Technical University of Munich (TUM), actively advancing hardware solutions for artificial intelligence under Prof. Hussam Amrouch. His work bridges computer engineering and emerging technologies, focusing on overcoming fundamental limitations in conventional computing architectures through brain-inspired paradigms. His research spans critical domains in next-generation computing: Hyperdimensional Computing for robust pattern recognition and bioinformatics applications Neuromorphic and In-Memory Computing architectures for energy efficiency Reliability engineering for emerging memory technologies (FeFET, etc.) Quantum computing support systems including cryogenic embedded electronics Machine learning-driven transistor aging prediction and mitigation Analysis of his 15 most recent publications (2023-2024) reveals a dominant trend toward hyperdimensional computing as a unifying framework for addressing reliability challenges in emerging technologies. His work consistently integrates in-memory computing techniques to bypass von Neumann bottlenecks while targeting real-world applications like genome matching and unsupervised learning. A significant portion focuses on error-resilient implementations for unreliable nanoscale devices, demonstrating exceptional cross-stack expertise from transistor physics to algorithm design. As a core member of TUM's AI Processor Design group affiliated with the Munich Institute of Robotics and Machine Intelligence (MIRMI), Genssler collaborates extensively on projects spanning cryogenic quantum control systems, FPGA-based AI resilience, and monolithic 3D integration. The team operates at the intersection of semiconductor physics, computer architecture, and machine learning, with strong industry connections evident through publications at DATE, ASP-DAC, and ICCAD.

Andrea Fumagalliمشاهده پروفایل

استاد

• Optical Networking
• Photonic Slot Routing
• Wavelength Routing and Protection
• +۷ مورد دیگر

Andrea Fumagalli is a Professor in the Department of Electrical Engineering at the Erik Jonsson School of Engineering and Computer Science , The University of Texas at Dallas. He earned his Ph.D. (1992) and Laurea (1987) in Electrical Engineering from Politecnico di Torino, Italy. Research Interests: All-Optical Network Architectures, Photonic Slot Routing, Wavelength Routing and Protection, Sensor Networks, Cooperative Wireless Networks, Network Optimization, Next Generation Internet (NGI), and Multi-hop Optical Networks. Education: Ph.D., Electrical Engineering, Politecnico di Torino (1992) Laurea, Electrical Engineering, Politecnico di Torino (1987) Key Research Trends: His recent publications focus on 5G networking, optical network automation, elastic optical networks, network reliability, and cross-layer optimization. He explores FPGA acceleration in 5G Low-PHY functions, live migration of containerized network components, and spectral fragmentation mitigation in EONs. Scientific Awards: Best Teaching Award, Electrical Engineering, UTD (2002) Best Thesis Award for Ph.D. Advisee Isabella Cerutti (2002) IEEE ComSoc Distinguished Lecturer Tour (2000) Best Paper Award (1999): 'An Optimal Design Algorithm for Photonic Slot Routing Networks Migrating to Optical Packet Switching' Advising and Grants: He advised Ph.D. student Isabella Cerutti. In 2001, he secured a $300,000 grant from FUNDACAO CPqD for optical network reliability research. He leads the Optical Networking Advanced Research (OpNeAR) Lab at UTD, collaborating on international projects like the Italian government-funded grid computing initiative (2002) and the OMEGA Test-bed for differentiated reliability. Laboratories and Teams: He directs the OpNeAR Lab , which develops tools for optical network emulation and reliability testing. His projects involve partnerships with institutions in Brazil (Unicamp), Sweden (KTH), Italy (Politecnico di Torino, Scuola Superiore Sant'Anna), and CNR/CNIT.

Luciano Lavagnoمشاهده پروفایل

استاد

• Field Programmable Gate Arrays (FPGA)
• High-Level Synthesis
• Indoor Positioning
• +۱۰ مورد دیگر

Luciano Lavagno is a Full Professor at the Department of Electronics and Telecommunications, Polytechnic University of Turin, with over two decades of academic and research contributions. His work bridges hardware acceleration, low-power electronics, and intelligent system design. Research Focus: Hardware-accelerated machine learning, high-level synthesis (HLS) for FPGA/ASIC, heterogeneous CPU/GPU/FPGA platforms Key Projects: SPACE (predictable acceleration), REBECCA (secure AI acceleration), HPC-National Center (quantum computing), and oral history preservation via "Ti racconto una storia" initiative His recent publications analyze CNN inference optimization, subgraph isomorphism, and superword-level parallelism exploitation. Lavagno supervises multiple PhD students working on FPGA acceleration, neural network hardware, and embedded systems. As Principal Investigator for national and EU-funded projects (PRIN, JTI-ECSEL, PNRR), he drives advancements in sustainable computing infrastructure. His patented technologies include MIx&Latch timing methodology, capacitive sensing innovations, and 5G acceleration frameworks.

Yiorgos Makrisمشاهده پروفایل

استاد

• Hardware Security
• Trusted Systems
• Machine Learning in Semiconductor Manufacturing
• +۹ مورد دیگر

Yiorgos Makris is a Professor in the Department of Electrical and Computer Engineering at the Erik Jonsson School of Engineering & Computer Science, The University of Texas at Dallas, since July 2011. Previously, he was a faculty member at Yale University for over a decade. He holds a Ph.D. in Computer Engineering from the University of California, San Diego, and a Diploma in Computer Engineering from the University of Patras, Greece. Education: Ph.D. in Computer Engineering, University of California, San Diego (2001) M.S. in Computer Engineering, University of California, San Diego (1997) Diploma in Computer Engineering and Informatics, University of Patras, Greece (1995) Research Interests: Hardware Security and Trustworthiness Statistical Side-Channel Fingerprinting Machine Learning in Semiconductor Manufacturing Trusted and Reliable Integrated Circuits Hardware Trojans in Wireless Cryptographic ICs On-Die Learning and Emergent Technologies His work focuses on enhancing hardware security through statistical methods, machine learning, and formal verification, with applications in analog/RF ICs, post-production calibration, and secure IC design. Key Contributions: Co-Founder and Site-PI of NSF CHEST I/UCRC (Hardware and Embedded System Security and Trust) Leader of the Safety, Security, and Healthcare Thrust at TxACE (Texas Analog Center of Excellence) Director of the Trusted and RELiable Architectures (TRELA) Lab Grants and Funding: NSF, NIH, SRC, ARO, AFRL, AFWERX, DARPA, DOE, and industry partnerships with Boeing, Northrop Grumman, IBM, Intel, Qualcomm, etc. Recent grants include projects on DNA storage security, analog neural networks, and malicious hardware detection. Awards and Recognition: IEEE Fellow (2025) Best Paper Awards at DATE'13, VTS'15, DCAS'22 Best Hardware Demonstration Awards at HOST'16 and HOST'18 Erik Jonsson School Faculty Research Award (2020) Labs and Teams: TRELA Lab (Focus: Secure Hardware Design, Trusted Architectures) CHEST I/UCRC (Industry-University Collaboration)

Dirk Kochمشاهده پروفایل

دانشیار

• Reconfigurable Computing
• Field Programmable Gate Arrays (FPGA)
• Hardware Acceleration
• +۳ مورد دیگر

Dirk Koch is an Associate Professor in the Department of Computer Science at the University of Manchester. He specializes in reconfigurable computing, FPGA architecture, and hardware acceleration. His research addresses challenges in field-programmable gate arrays (FPGAs), high-level synthesis, and stream processing. He leads the Advanced Processor Technology group and contributes to the Digital Futures Institute for Data Science and AI. Education: Doctorate in Computer Engineering Affiliations: Centre for Digital Trust and Society, EPSRC Functional Oxide Reconfigurable Technologies Programme His work focuses on optimizing FPGA performance, reducing power consumption, and advancing reconfigurable hardware systems. Recent projects include bitstream manipulation frameworks, runtime stream processing pipelines, and FPGA fabric optimization techniques. He has collaborated extensively with industry partners like AMD-Xilinx. Dirk Koch has supervised 11 research projects, including work on clock region process variation analysis and FPGA virus scanning. He holds grants from EPSRC and has published 62 peer-reviewed works.