جستجوی استاد راهنمای دانشگاهی

Mirjana Stojilovicمشاهده پروفایل

پژوهشگر

• Field-programmable technology
• Electronic design automation (EDA)
• Hardware security
• +۵ مورد دیگر

Mirjana Stojilovic is a Researcher at École Polytechnique Fédérale de Lausanne (EPFL) in the School of Computer and Communication Sciences (IC), specifically within the Institute of Computer Engineering (IINFCOM) and the Parallel Systems Architecture Laboratory (PARSA). She also serves as a Lecturer in the SSC - Teaching department at EPFL. Her office is located at INJ 235, Station 14, 1015 Lausanne, Switzerland. Mirjana Stojilović received her Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. Her academic journey includes collaborating with the Processor Architecture Laboratory at EPFL as a Guest Researcher from 2010 to 2013, working at the University of Applied Sciences Western Switzerland as a senior researcher from 2013 to 2016, and joining the Parallel Systems Architecture Lab at EPFL in October 2016. Dr. Stojilovic's research spans field-programmable technology, electronic design automation (EDA), and electrical-level attacks and countermeasures for reconfigurable hardware. Her work bridges the gap between hardware design and security, with a particular focus on vulnerability analysis and protection mechanisms for FPGA-based systems in cloud environments. She has made significant contributions to understanding side-channel attacks, fault injection techniques, and secure multi-tenancy solutions for shared hardware resources. Her extensive publication record reveals a clear research trajectory from traditional FPGA design and EDA topics toward increasingly security-focused investigations. Recent work demonstrates deep expertise in power analysis attacks, hardware trojans, and countermeasures for cloud-based FPGA systems, reflecting the growing importance of hardware security in distributed computing environments. Scientific Awards and Recognitions: Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016) Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016) Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012) EPFL School of Computer and Communication Sciences (IC) Teaching Award (2015) Nominated for Best Paper Award at the International Conference on Field-Programmable Technology (FPT) (2020) Dr. Stojilovic has advised numerous PhD students including Coulon Louis, Pirayadi Rouzbeh, and Shrivastava Shashwat, along with past EPFL PhD students Glamocanin Ognjen and Mahmoud Dina. She has supervised dozens of semester and diploma projects focusing on hardware security, FPGAs, design automation, side-channel attacks, and cloud computing. Her service to the academic community includes serving on program committees for FPGA, FCCM, FPL, and DATE conferences, reviewing for multiple IEEE and ACM journals, and acting as associate editor for IEEE ESL and ACM TRETS. As a member of the Parallel Systems Architecture Laboratory at EPFL, Dr. Stojilovic leads research projects investigating security aspects of reconfigurable hardware systems. Her team works at the intersection of computer architecture, electronic design automation, and hardware security, with particular emphasis on vulnerabilities and protections for shared FPGA resources in cloud environments.

Russell Tessierمشاهده پروفایل

استاد

• Reconfigurable Computing
• FPGA Architecture
• CAD Algorithms for FPGAs
• +۴ مورد دیگر

Russell Tessier is a Professor and Department Head of Electrical and Computer Engineering at the University of Massachusetts Amherst, affiliated with the Manning College of Information and Computer Sciences. His research focuses on reconfigurable computing, FPGA architectures, and hardware security, with notable contributions in CAD algorithms for FPGAs, embedded systems, and multi-tenant FPGA vulnerability analysis. Education: B.S.C.S.E., Rensselaer Polytechnic Institute (1989) M.S. and Ph.D., Massachusetts Institute of Technology (1992 and 1999) Research Interests: Dr. Tessier's work spans FPGA security (e.g., side-channel attacks, power distribution vulnerabilities), reconfigurable cloud computing, and hardware acceleration for applications like SAR imaging and machine learning. His lab, the Reconfigurable Computing Group, develops open-source FPGA cores (e.g., FlexGrip GPGPU, DE4 NetFPGA) and explores cutting-edge security countermeasures. Awards and Honors: Chancellor's Leadership Fellow (2015-2016) NSF Information Technology Research Grant Lilly Teaching Fellow (2002-2003) Multiple College of Engineering Excellence Awards Grants and Projects: Active funding includes NSF SaTC grants on reconfigurable cloud security and NASA support for snowpack measurement systems. His research also addresses FPGA-based solutions for cybersecurity, such as intrusion detection and power-side channel mitigation. Labs and Teams: Leads the UMass Reconfigurable Computing Group, which collaborates on open-source FPGA tools, security frameworks, and embedded system designs. The group maintains platforms like the DE4 NetFPGA and FlexGrip architecture.

Chester Rebeiroمشاهده پروفایل

دانشیار

• Hardware Security
• Applied Cryptography
• Side Channel Analysis
• +۳ مورد دیگر

Chester Rebeiro is an Associate Professor at the Department of Computer Science and Engineering within the Indian Institute of Technology Madras . His work spans hardware and software security with a focus on cryptographic implementations and microarchitectural vulnerabilities. Research interests include hardware security, applied cryptography, side channel analysis, and operating system security. He develops frameworks for automatic vulnerability detection and mitigation in cryptographic systems. Editorial Board: Associate Editor at Journal of Hardware and Systems Security (Springer, 2021-2024) Conference Leadership: General Co-Chair for SPACE 2024, Program Co-Chair for ATS 2024, and Program Co-Chair for INDOCRYPT 2023 Professional Activities: Organizer of e-CTF Embedded Capture The Flag and contributor to cybersecurity workshops across India and abroad Scientific contributions highlight two major awards: a Distinguished Paper Award at USENIX Security 2024 and a Best Paper Award at IEEE HOST 2020. His research focuses on practical security solutions for processors and cryptographic systems. Advising includes mentoring 11 PhD students and 7 MS by Research candidates, with notable co-guided projects in fault attack detection and side-channel mitigation. He actively contributes to educational initiatives through courses on Secure Processor Microarchitecture and Operating Systems.

Kimia Zamiri Azarمشاهده پروفایل

استادیار

• Hardware Security
• Verification Formal Methods
• Advanced VLSI Testing
• +۳ مورد دیگر

Kimia Zamiri Azar serves as an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida, focusing on hardware security and verification methodologies. Her research bridges theoretical formal methods with practical security implementations in semiconductor design and testing. Her educational background includes: Ph.D. in Electrical and Computer Engineering, George Mason University (2021) Postdoctoral Research, University of Florida Dr. Azar's research spans hardware security with emphasis on system-level verification, VLSI design-for-trust, and advanced IC testing. She pioneers techniques in logic locking, secure heterogeneous integration, and IC supply chain security, developing frameworks for authenticated encryption in Systems-in-Package and runtime security monitoring. Her work integrates formal verification with innovative testing methodologies to address hardware trust challenges across the semiconductor lifecycle. Analysis of her recent publications reveals two dominant trends: (1) Application of large language models (LLMs) to hardware design tasks including high-level synthesis code generation and RTL optimization, and (2) Advancement of secure heterogeneous integration techniques for System-in-Package architectures with focus on counterfeit prevention and split-test security protocols. These directions address critical gaps in hardware trustworthiness amid increasingly complex semiconductor supply chains. Her scientific contributions have earned significant recognition: Best Paper Award at ICCAD 2019 Best Paper Award at ISVLSI 2020 Best Paper Award at ICCAD 2020 Best Paper Award at IEEE DCAS 2020 Best Paper Award at HOST 2022 Best Paper Award at DATE 2023 Dr. Azar secures substantial research funding from premier agencies including NSF, SRC, DARPA, AFRL, DoD (NG), and Microsemi. Her grants support projects spanning hardware security validation frameworks, secure heterogeneous integration, and AI-augmented verification methodologies. She actively mentors students in her research group, guiding publications in top venues like IEEE D&T, IEEE TC, and DAC while fostering industry-academic collaborations. Her work directly impacts semiconductor security standards through patented innovations and open-source verification tools. As an active IEEE and ACM member, she contributes to community advancement through conference organization (HOST, DATE), journal editorial roles, and workshop leadership on hardware security standards. Her research group collaborates with semiconductor industry leaders to translate theoretical security frameworks into practical design-for-trust methodologies for next-generation integrated circuits.

Yiorgos Makrisمشاهده پروفایل

استاد

• Hardware Security
• Trusted Systems
• Machine Learning in Semiconductor Manufacturing
• +۹ مورد دیگر

Yiorgos Makris is a Professor in the Department of Electrical and Computer Engineering at the Erik Jonsson School of Engineering & Computer Science, The University of Texas at Dallas, since July 2011. Previously, he was a faculty member at Yale University for over a decade. He holds a Ph.D. in Computer Engineering from the University of California, San Diego, and a Diploma in Computer Engineering from the University of Patras, Greece. Education: Ph.D. in Computer Engineering, University of California, San Diego (2001) M.S. in Computer Engineering, University of California, San Diego (1997) Diploma in Computer Engineering and Informatics, University of Patras, Greece (1995) Research Interests: Hardware Security and Trustworthiness Statistical Side-Channel Fingerprinting Machine Learning in Semiconductor Manufacturing Trusted and Reliable Integrated Circuits Hardware Trojans in Wireless Cryptographic ICs On-Die Learning and Emergent Technologies His work focuses on enhancing hardware security through statistical methods, machine learning, and formal verification, with applications in analog/RF ICs, post-production calibration, and secure IC design. Key Contributions: Co-Founder and Site-PI of NSF CHEST I/UCRC (Hardware and Embedded System Security and Trust) Leader of the Safety, Security, and Healthcare Thrust at TxACE (Texas Analog Center of Excellence) Director of the Trusted and RELiable Architectures (TRELA) Lab Grants and Funding: NSF, NIH, SRC, ARO, AFRL, AFWERX, DARPA, DOE, and industry partnerships with Boeing, Northrop Grumman, IBM, Intel, Qualcomm, etc. Recent grants include projects on DNA storage security, analog neural networks, and malicious hardware detection. Awards and Recognition: IEEE Fellow (2025) Best Paper Awards at DATE'13, VTS'15, DCAS'22 Best Hardware Demonstration Awards at HOST'16 and HOST'18 Erik Jonsson School Faculty Research Award (2020) Labs and Teams: TRELA Lab (Focus: Secure Hardware Design, Trusted Architectures) CHEST I/UCRC (Industry-University Collaboration)

• Security Engineering
• Hardware Security
• Post-Quantum Cryptography
• +۴ مورد دیگر

Prof. Tim Güneysu is a full Professor and Head of the Security Engineering department at the Faculty of Computer Science, Ruhr-Universität Bochum. He serves as Vice Dean for Strategy and Finances (since 2023) and previously as Speaker of the Horst-Görtz Institute for IT-Security (2020-2023). His academic journey includes roles as Associate Professor at the University of Bremen (2015-2017) and Assistant Professor at Ruhr-Universität Bochum (2011-2015). He also holds positions at the German Research Center for Artificial Intelligence (DFKI) and has conducted postdoctoral research at UMass Amherst. His research focuses on Security-by-Design principles, CAD for Security, and countermeasures against physical attacks. He emphasizes efficient cryptographic implementations and system-level hardware security. Key areas include post-quantum cryptography, side-channel resistant designs, and secure embedded systems. He has contributed over 200 publications in top venues, with recent work on FPGA-based cryptographic accelerators, secure hardware extensions (e.g., KeyVisor), and post-quantum algorithms for IoT. His research themes include agile signature acceleration, fault attack mitigation, and hardware-software co-design for security. Notable projects include CONVOLVE (edge-AI security) and QuantumRISC (quantum-safe systems). His work bridges theoretical cryptography with practical hardware implementations, emphasizing real-world security applications.

Fatemeh Ganjiمشاهده پروفایل

استادیار

• Hardware Security
• Cryptography
• Machine Learning
• +۳ مورد دیگر

Fatemeh Ganji is an Assistant Professor in the Department of Electrical & Computer Engineering at Worcester Polytechnic Institute (WPI), with an affiliation to the Cybersecurity program. She holds a Ph.D. in Electrical Engineering from the Technical University of Berlin (2017), where she received the BIMoS Ph.D. Award and was nominated for the ACM Dissertation Award. Prior to WPI, she served as a Post Doctoral Associate at the University of Florida (2018–2020) and at Telecom Innovation Laboratories/Technical University of Berlin (2017–2020). Her research focuses on interdisciplinary approaches in hardware security, combining machine learning and cryptography to design and evaluate security-critical hardware systems. Key areas include physically unclonable functions (PUFs), side-channel analysis, and countermeasures against tampering and counterfeiting. Her work is funded by the European Union (Horizon 2020, FP7), German BMBF, NSF, and NIST. Ganji actively contributes to the academic community as a reviewer for IEEE and ACM journals and serves on technical program committees for CHES, FPL, DATE, and SPACE conferences. Her recent projects include developing AI-driven forensic analysis for PCB tamper detection, secure multiparty computation frameworks for chiplet systems, and open-source tools for implementation security testing. Her awards include the BIMoS Ph.D. Award 2018 and recognition from the Technical University of Berlin for her doctoral work on PUF learnability. She has also pioneered methods to detect recycled integrated circuits and enhance hardware trust through reverse engineering and machine learning.

Berk Sunarمشاهده پروفایل

استاد

• Applied Cryptography
• Cybersecurity
• Microarchitectural Security
• +۵ مورد دیگر

Berk Sunar is a Professor of Electrical & Computer Engineering and the founder of the Vernam Applied Cryptography and Cybersecurity Laboratory at Worcester Polytechnic Institute (WPI). He joined WPI in 2000 after holding postdoctoral and research roles at Oregon State University (OSU) and Trust Inc. His work focuses on applied cryptography, microarchitectural security, AI security, post-quantum cryptography, and homomorphic encryption. Sunar received his BSc from Middle East Technical University (1995) and PhD from Oregon State University (1998). Research interests include vulnerabilities in hardware (e.g., Rowhammer, TPM-FAIL), side-channel attacks, and cryptographic implementations. Notable contributions include discovering flaws in Intel CPUs and TPM chips affecting billions of devices, as well as developing defenses like cuHE (GPU-accelerated homomorphic encryption). Publications highlight breakthroughs in transient execution attacks (e.g., LVI, RIDL), post-quantum signature schemes (Dilithium), and cloud security (Firecracker VMM vulnerabilities). Awards include NSF CAREER (2002) and IBM Pat Goldberg Best Paper (2007). Advised over 30 graduate students, many of whom hold senior roles in academia and industry. Current research addresses AI security, quantum-resistant algorithms, and automated attack detection via machine learning. The Vernam Lab remains a hub for cybersecurity innovation.

Jia Diمشاهده پروفایل

استاد

• Asynchronous Integrated Circuit Design
• Hardware Security
• Extreme Environment Electronics
• +۳ مورد دیگر

Jia Di serves as Professor and Department Head of the Department of Electrical Engineering and Computer Science at the University of Arkansas, holding the Rodger S. Kline Endowed Leadership Chair. He has been with the institution since 2004, progressing from Assistant Professor to his current leadership position within the College of Engineering. Education: B.S. in Automatic Control, Tsinghua University (1997) M.S. in Automatic Control, Tsinghua University (2000) Ph.D. in Electrical and Computer Engineering, University of Central Florida (2004) Research Focus: Dr. Di's work centers on asynchronous integrated circuit design and hardware security , with emphasis on Multi-threshold Null Convention Logic (MTNCL) for ultra-low-power secure systems. His research spans hardware Trojan detection, polymorphic logic gates, extreme environment electronics, and security solutions for IoT infrastructure. His Trustable Logic Circuit Design Lab has pioneered techniques for side-channel attack mitigation and cold boot attack prevention through self-destructive memory mechanisms. Publication Trends: Recent publications reveal a strategic shift toward hardware security applications for renewable energy systems and IoT edge devices, while maintaining core expertise in asynchronous circuit design. His work increasingly integrates machine learning (e.g., graph neural networks for hardware Trojan detection) and cross-platform verification frameworks, demonstrating evolution from pure circuit design to holistic cybersecurity solutions for critical infrastructure. Scientific Recognition: Senior Member of IEEE Eminent Member of Tau Beta Pi Elected Member of the National Academy of Inventors Research Leadership: Dr. Di has secured over $23 million in research funding for his Trustable Logic Circuit Design Lab, supporting development of 6 U.S. patents and two authoritative books. His lab collaborates with federal agencies and industry partners on hardware security challenges, with recent grants focusing on photovoltaic system protection and extreme-environment electronics. While specific student names aren't documented here, his extensive publication record indicates significant graduate mentorship in hardware security and asynchronous design. Lab Infrastructure: The Trustable Logic Circuit Design Lab maintains specialized capabilities for testing circuits in extreme environments (high temperature/radiation) and developing polymorphic security mechanisms. Current projects include RF aperture security, hardware-based IoT verification systems, and digital twin implementations for power electronics with integrated trust verification.

Pascal Sasdrichمشاهده پروفایل

پژوهشگر

• Hardware Security
• Secure Processor Design
• Computer-Aided Security
• +۳ مورد دیگر

Pascal Sasdrich is a Researcher at Ruhr University Bochum, Germany, affiliated with the Faculty of Computer Science and the Security Engineering department. He holds a PhD in IT-Security/Information Technology from the same university (2018), following M.Sc. (2015) and B.Sc. (2012) degrees in the same field. His research focuses on Hardware Security, Secure Processor Design, Computer-Aided Security, and Security by Design. He has extensive experience in cryptographic hardware implementations, including countermeasures against side-channel and fault attacks. Teaching includes courses on Processor Security and Implementation of Cryptographic Schemes. His work bridges theoretical security models with practical hardware implementations, emphasizing automated tools and formal verification for secure embedded systems. Key projects include contributions to Project HEP (open-source hardware security chip design) and development of methodologies like EASIMASK for automated masking in hardware. Publications span cryptographic hardware implementations, fault and side-channel countermeasures, and formal security verification. Notable works include combined threshold implementations, secure processor extensions, and automated generation of masked hardware circuits. Current research emphasizes securing embedded systems through holistic design approaches, including ISA extensions and automated EDA tools.

Nele Mentensمشاهده پروفایل

استاد

• Applied Cryptography
• Hardware Security
• Secure Coprocessor Design
• +۱۲ مورد دیگر

Nele Mentens is a full professor at both KU Leuven and Leiden University, where she leads cutting-edge research in applied cryptography, hardware security, and secure embedded systems. At KU Leuven, she is affiliated with the Faculty of Engineering Technology and the Electrical Engineering Department (ESAT), leading the Emerging Technologies, Systems & Security (ES&S) research group at the Diepenbeek campus. Simultaneously, she holds a full professorship at Leiden University’s Leiden Institute of Advanced Computer Science (LIACS), focusing on applied cryptography and security. She has been instrumental in numerous national and international research initiatives, including Horizon Europe and NWO-funded projects. Full Professor, KU Leuven (since 2023) Full Professor, Leiden University (since 2020) Associate Professor, KU Leuven (2014–2023) Post-doctoral Researcher & Lecturer, KHLim / KU Leuven (2007–2014) Ph.D. in Engineering Science, KU Leuven (2007) M.Sc. in Electrical Engineering, KU Leuven (2003) Her research focuses on secure and efficient hardware design, particularly for cryptographic applications on FPGAs, reconfigurable architectures, IoT security, and neuromorphic computing. She explores physical attack resistance, side-channel analysis protection, and trusted computing architectures, with applications in healthcare, industrial monitoring, and endpoint AI. Her work bridges theoretical cryptography with practical hardware implementations, emphasizing energy efficiency and real-time performance. The 15 most recent publications reflect a strong trend toward secure, energy-efficient, and intelligent embedded systems. Topics include neuromorphic AI accelerators, trusted IoT architectures, dynamic reconfiguration for side-channel protection, and secure medical data processing. These works span disciplines such as computer architecture, cybersecurity, digital design, and embedded systems, with a focus on hardware-software co-design and real-world deployment. Nele Mentens has received recognition for her contributions, including: Best Paper Award, DATE'16 Best Paper Nomination, AsianHOST'17 Best Paper Award, CHES'19 She has supervised over 15 Ph.D. students and post-docs, both current and former, and has served as principal investigator in approximately 25 funded research projects. Her work has attracted significant grants from Horizon Europe, NWO, FWO, and national innovation programs. She actively contributes to the academic community through editorial roles in top journals and leadership in major conferences. Nele Mentens leads the ES&S research group at KU Leuven and collaborates closely with LIACS at Leiden University. Her team includes Ph.D. students, post-docs, and research experts working on projects like NimbleAI, NeuroSoC, and TrustedIoT. She has also established secure electronics labs through infrastructure grants and maintains strong international ties with institutions such as EPFL, Ruhr University Bochum, and ETH Zurich.

Renaud Pacaletمشاهده پروفایل

پژوهشگر

• Hardware Security
• Side-Channel Attacks
• Embedded Systems
• +۷ مورد دیگر

Renaud Pacalet is a Researcher at Institut Mines-Télécom – Télécom Paris , affiliated with the Communications and Electronics (Comelec) Department and the System on Chip (LabSoc) research team under the Information Processing and Communication Laboratory (LTCI). His work spans hardware security, embedded systems, and software-defined radio (SDR) architectures. Current Research: Hardware security, side-channel attacks (power, timing, fault injection), RISC-V security analysis using gem5, FPGA scheduling for cloud data centers, and model-driven design methodologies. Past Research: Hardware acceleration for ray tracing, SDR front-end processing, SoC security, and memory bus protection (SecBus project). Teaching: Courses on Digital Systems, Computer Architecture, and Hardware Security at EURECOM, including lab sessions on side-channel attacks and fault analysis. Email: renaud.pacalet@telecom-paris.fr Contact: Télécom ParisTech, Campus SophiaTech, 450 route des Chappes 06410 Biot, France

Tarik Grabaمشاهده پروفایل

مدرس

• Hardware Security
• Embedded Systems Design
• Integrated Circuit Reliability
• +۳ مورد دیگر

Tarik Graba is a Lecturer at Télécom Paris and a member of the Secure and Safe Hardware (SSH) research team within the Information Processing and Communication Laboratory (LTCI) department. His work focuses on hardware security, embedded systems, and cryptographic implementation. Education: Not explicitly mentioned Current Affiliations: Télécom Paris (Faculty), LTCI, SSH Team His research explores designing secure and reliable integrated systems , with emphasis on managing complexity, power consumption, and flexibility in embedded environments. He contributes to side-channel analysis , lightweight cryptographic algorithms , and hardware-based security mechanisms . The 15 most recent publications highlight his work in lightweight cryptography , hardware security , and embedded system optimization , particularly focusing on RISC-V extensions , side-channel leakage , TRNG circuits , and secure cryptographic processors . Scientific Awards Academic Palms award, Télécom Paris (2021) Tarik Graba collaborates extensively in hardware security research and has advised multiple projects on physical security countermeasures and embedded cryptographic systems . He works with teams like the SSH Laboratory to develop secure hardware architectures.

Satwik Patnaikمشاهده پروفایل

استادیار

• VLSI Design
• Hardware Security
• Computer-Aided Design (CAD)
• +۳ مورد دیگر

Satwik Patnaik is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Delaware. His research focuses on strengthening hardware security through CAD tools, leveraging machine learning, and exploring emerging technologies. He holds a Ph.D. in Electrical Engineering from New York University (2020) and was a postdoctoral researcher at Texas A&M University (2020–2021). Education: Ph.D., Electrical Engineering, Tandon School of Engineering, New York University (2020) Postdoctoral Research, Texas A&M University (2020–2021) Research Interests: VLSI design, hardware security (e.g., logic locking, side-channel attacks), computer-aided design (CAD), and applications of machine learning in securing global semiconductor supply chains. His work emphasizes 3D integration, emerging devices (e.g., ferroelectric tunnel junctions), and reinforcement learning for adversarial testing. Key Contributions: Developed tools like SecureX, VIGILANT, and Titan. Published over 48 peer-reviewed articles in top venues (e.g., ICCAD, IEEE Transactions). Co-organized global competitions like HeLLO-CTF 2021 and AI vs. Humans 2022. Served as security track chair for ACM CADAthlon (2022) and technical program committee member for ICCAD, ASP-DAC, etc. Awards: ACM/SIGDA Bronze Medal (2018) Best Paper Award at ARC 2017 Third Place at ARC 2021 Expertise: Integrates hardware design, security, and AI to address vulnerabilities in semiconductor supply chains. Active in standardizing secure CAD flows and educating the next generation of hardware security researchers.

Dong Chenمشاهده پروفایل

دانشیار

• Cyber-Physical Systems (CPS)
• Internet of Things (IoT)
• Embedded AI
• +۵ مورد دیگر

Dong Chen is an Associate Professor in the Department of Computer Science at the Colorado School of Mines. His research focuses on building data-driven experimental systems in Cyber-Physical Systems (CPS), IoT, Embedded AI, and Embodied AI, with applications in smart devices, homes, cities, and renewable energy systems. He leads the Next Generation Cyber-Physical Systems Laboratory (CPSLab), emphasizing open-source systems and datasets. Dr. Chen holds PhDs in Electrical and Computer Engineering (2018, University of Massachusetts Amherst) and Computer Science (2014, Northeastern University). His work addresses security, privacy, sustainability, and efficiency in smart environments. Notable contributions include SolarFinder, SolarTrader, PrivacyGuard, and VoiceAttack, which tackle challenges in IoT privacy, energy trading, and adversarial attacks. He received the NSF CAREER Award (2023) and is a member of Sigma Xi, ACM, AAAI, and IEEE. His research spans system design, AI applications, and cross-cutting domains like solar energy modeling and edge computing. Current projects include AgileDART (edge stream processing) and SolarDetector (satellite-based PV array identification). Advising and collaborations: Dr. Chen seeks PhD and undergraduate students with strong CS/EE backgrounds. His lab focuses on CPS/IoT security, energy systems, and AI-driven solutions. He has published extensively on topics ranging from smart grid optimization to adversarial machine learning.