Prof. Tim Güneysu is a full Professor and Head of the Security Engineering department at the Faculty of Computer Science, Ruhr-Universität Bochum. He serves as Vice Dean for Strategy and Finances (since 2023) and previously as Speaker of the Horst-Görtz Institute for IT-Security (2020-2023). His academic journey includes roles as Associate Professor at the University of Bremen (2015-2017) and Assistant Professor at Ruhr-Universität Bochum (2011-2015). He also holds positions at the German Research Center for Artificial Intelligence (DFKI) and has conducted postdoctoral research at UMass Amherst. His research focuses on Security-by-Design principles, CAD for Security, and countermeasures against physical attacks. He emphasizes efficient cryptographic implementations and system-level hardware security. Key areas include post-quantum cryptography, side-channel resistant designs, and secure embedded systems. He has contributed over 200 publications in top venues, with recent work on FPGA-based cryptographic accelerators, secure hardware extensions (e.g., KeyVisor), and post-quantum algorithms for IoT. His research themes include agile signature acceleration, fault attack mitigation, and hardware-software co-design for security. Notable projects include CONVOLVE (edge-AI security) and QuantumRISC (quantum-safe systems). His work bridges theoretical cryptography with practical hardware implementations, emphasizing real-world security applications.
Dr. Ciara Rafferty is a Senior Lecturer at Queen's University Belfast's School of Electronics, Electrical Engineering and Computer Science, affiliated with the Centre for Secure Information Technologies. She leads research in advanced cryptography, focusing on post-quantum systems, homomorphic encryption, and hardware acceleration. Her work includes quantum-safe cryptography projects like the UK Quantum Communications Hub and AQuASeC (Innovate UK). She co-teaches CSC2056 - Systems Security and Cryptography and actively supervises PhD students. Dr. Rafferty is a Senior Member of IEEE and an EPSRC SPRITE+ Expert Fellow. Research Interests: Homomorphic Encryption Post-Quantum Cryptography Cryptographic Hardware Architectures Privacy-Preserving Technologies Side-Channel Attack Mitigation Key Projects: UK Quantum Communications Hub (Phase 2) SAFEcrypto (H2020 Project) AQuASeC (Toshiba Europe-funded) SEQURED (Rolls Royce-funded) Awards: Senior Member of IEEE EPSRC SPRITE+ Expert Fellow Advising & Grants: PhD Supervision: Shabnam K (Secure Cloud Computation) Funding: EPSRC, Innovate UK, Industry Partners Lab/Teams: Centre for Secure Information Technologies (CSIT), collaborating on hardware-accelerated cryptography and quantum-safe systems.
David Andrews is a Professor in the Department of Computer Science and Computer Engineering at the University of Arkansas College of Engineering. He holds the Mullins Endowed Chair of Computer Engineering and directs research through the Computer Systems Design Laboratory (CSDL). His work bridges hardware and software systems with a focus on practical implementation. His educational background includes: Ph.D. in Computer Engineering from Syracuse University Computer Engineer Degree from Syracuse University M.S.E.E. from University of Missouri-Columbia B.S.E.E. from University of Missouri-Columbia Andrews' research centers on embedded systems architectures from a holistic systems perspective, examining interactions between programming languages, runtime systems, and hardware components. His work spans reconfigurable computing, FPGA-based acceleration, and hybrid CPU/FPGA systems. A key contribution is the HybridThreads (hthreads) platform, which abstracts hardware/software boundaries to enable thread-based programming for heterogeneous systems. Recent publications demonstrate his focus on accelerating machine learning workloads on FPGAs, particularly transformer models and attention mechanisms, while addressing resource scheduling and real-time constraints. His publication trends reveal a consistent evolution from foundational work in parallel and distributed embedded systems toward specialized hardware acceleration for modern AI workloads. The research increasingly focuses on memory-centric architectures, computational overlays, and practical implementations for real-time applications across diverse domains including cultural heritage documentation and cybersecurity. As director of the Computer Systems Design Laboratory, Andrews leads interdisciplinary research in real-time embedded systems, reconfigurable computing, multiprocessor systems on chip, and hardware/software co-design. The lab integrates knowledge into undergraduate and graduate curricula covering digital design, computer organization, embedded systems, and systems modeling. CSDL supports a collaborative environment with undergraduate, master's, and PhD students working alongside visiting researchers from global institutions.
Thaier Hayajneh , Ph.D., is a University Professor at Fordham University's Department of Computer and Information Sciences. He serves as Founder Director of the Fordham Center for Cybersecurity and Program Director for the MS in Cybersecurity program. Previously, he held academic roles at New York Institute of Technology and Hashemite University in Jordan. Specializes in cybersecurity, networking, and applied cryptography Focus areas include blockchain, IoT security, and wireless network vulnerabilities Active in NSF cybersecurity review panels and as a CAE reviewer for NSA Recipient of peer-review awards from Publons His research spans secure protocols for medical IoT systems, lightweight cryptographic algorithms, and smart contract implementations in healthcare. Publications in IEEE IoT Journal, IEEE Systems Journal, and Journals like Future Generation Computer Systems demonstrate his expertise in securing emerging technologies. Dr. Hayajneh has received research funding from federal agencies including NSA, Department of Defense, and NSF. He has published over 80 papers and maintains active editorial roles in prestigious journals. Scientific Awards: Peer-review awards from Publons
Stefan Wildermann is a Professor at Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), where he leads the Reconfigurable Computing Group within the Chair of Computer Science 12 (Hardware-Software Co-Design) in the Department of Computer Science. He has maintained continuous research activity at FAU since 2006, progressing from researcher to his current leadership position. Dr. Wildermann earned his Diploma degree in Computer Science from FAU in 2006 and completed his doctorate (Dr.-Ing.) in Computer Science at the same institution in July 2012. His academic career has been entirely rooted at FAU, demonstrating a strong institutional commitment and progression through the ranks. His research spans multiple cutting-edge areas in computer science and engineering, with particular emphasis on reconfigurable systems and hardware-software co-design. Wildermann's work in edge computing explores efficient processing at the network periphery, while his research in organic computing investigates self-organizing systems that can adapt to changing environments. His expertise extends to optimization techniques for embedded systems, applying game theory principles and convex optimization methods to solve complex resource allocation problems. More recently, he has integrated reinforcement learning approaches to enhance system adaptability and performance. His teaching portfolio includes courses on event-driven systems, computer engineering fundamentals, embedded systems, and hardware-software co-design. Analysis of Wildermann's publication record from 2021-2025 reveals a strong focus on hardware acceleration, security, and embedded systems. His work demonstrates consistent evolution from foundational research in reconfigurable architectures toward practical applications in IoT, robotics, and secure computing. A significant portion of his recent work addresses near-data processing using FPGAs for database acceleration, while maintaining parallel research streams in side-channel security analysis and energy-efficient embedded systems design. His publications frequently appear in top-tier conferences including DATE, FPL, ASP-DAC, and HOST, reflecting strong recognition within the computer architecture and embedded systems communities. Wildermann has held significant leadership roles including Head of the Reconfigurable Computing Group since 2015 and previously served as Head of the Self-organizing Systems Group (2012-2015) and Lab Leader of the Automotive Lab within the Embedded Systems Initiative (2016-2020). His research has been consistently funded through multiple projects investigating invasive computing, reconfigurable architectures, and embedded systems design methodologies. Currently based in Room 02.116 at Cauerstr. 11, 91058 Erlangen, Wildermann continues to lead active research in the Hardware-Software Co-Design group, supervising projects that bridge theoretical computer science with practical hardware implementation challenges.
Guido Masera is a Full Professor at the Department of Electronics and Telecommunications (DET) at the Polytechnic University of Turin, where he has been actively involved in teaching and research for over two decades. He serves as a Member of the Board of Directors, Member of the GEDI Observatory for Gender Equality, Diversity and Inclusion, and Member of the Permanent University Observatory for monitoring the academic supply chain. His research interests span across channel decoders, circuits for communications, cryptography, deep learning, digital integrated circuits, field programmable gate arrays (FPGA), and hardware design. His work focuses on VLSI architectures for image and video coding, digital architectures for error correcting codes, application specific approximate computing, VLSI architectures for machine learning, digital architectures for bio-inspired processing, digital architectures for post-quantum cryptography, bio-inspired electronics for robotics and biomedical applications, RISC-V extensions and hardware accelerators, and circuit architectures for efficient machine learning and artificial intelligence. His recent publications (2025) demonstrate a strong focus on RISC-V architecture, particularly in the context of cryptographic implementations, hardware security, and post-quantum cryptography. His research group VLSILAB is actively engaged in cutting-edge research in hardware security, efficient processor design, and specialized computing architectures. Among his notable recognitions are the Premio Francesco Carassa awarded by the Telecommunications and Information Technologies Group Association (gtti) in 2010, and his recognition as a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) since 2007. He also serves as an Associate Editor for several prestigious journals including ELECTRONICS (2019-present), IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS (2015-2019), and IET CIRCUITS, DEVICES & SYSTEMS (2013-2016). Professor Masera has advised numerous PhD students working on advanced topics in VLSI design, post-quantum cryptography, hardware accelerators, and machine learning implementations. His current research projects include ISOLDE (2023-2026) and TRISTAN (2022-2025), both EU-funded projects focused on RISC-V technology and domain-specific ecosystems. He leads the VLSILAB research group at the Department of Electronics and Telecommunications, which focuses on cutting-edge research in VLSI architectures, hardware security, and specialized computing systems. The group collaborates with industry partners and participates in major European research initiatives.
Pascal Sasdrich is a Researcher at Ruhr University Bochum, Germany, affiliated with the Faculty of Computer Science and the Security Engineering department. He holds a PhD in IT-Security/Information Technology from the same university (2018), following M.Sc. (2015) and B.Sc. (2012) degrees in the same field. His research focuses on Hardware Security, Secure Processor Design, Computer-Aided Security, and Security by Design. He has extensive experience in cryptographic hardware implementations, including countermeasures against side-channel and fault attacks. Teaching includes courses on Processor Security and Implementation of Cryptographic Schemes. His work bridges theoretical security models with practical hardware implementations, emphasizing automated tools and formal verification for secure embedded systems. Key projects include contributions to Project HEP (open-source hardware security chip design) and development of methodologies like EASIMASK for automated masking in hardware. Publications span cryptographic hardware implementations, fault and side-channel countermeasures, and formal security verification. Notable works include combined threshold implementations, secure processor extensions, and automated generation of masked hardware circuits. Current research emphasizes securing embedded systems through holistic design approaches, including ISA extensions and automated EDA tools.
Prof. Mohammed Khalid is a Professor in the Department of Electrical and Computer Engineering at the University of Windsor. He specializes in FPGA-based systems, network-on-chip architectures, and hardware acceleration for signal processing applications. His leadership roles include serving on the executive committee of IEEE Canada. His research focuses on optimizing cryptographic hardware, automotive embedded systems, and efficient algorithm implementations on FPGAs. Key contributions include advancements in PUF-based security mechanisms, high-speed elliptic curve processors, and FPGA-accelerated machine learning algorithms. He has led projects in automotive radar systems and AUTOSAR configuration tools. His work emphasizes practical applications of hardware-software co-design principles. Research Highlights : Development of novel FPGA architectures for real-time signal processing Innovative approaches to resource-efficient cryptographic hardware Pioneering work on hybrid NoC architectures for multi-FPGA systems Awards : IEEE Windsor Section Award (2019) for group leadership Best Student Paper Award (2024) for supervised research by Mohit Sharma Prof. Khalid's 150+ publications span FPGA design methodologies, adaptive signal processing, and embedded systems security. His research group collaborates with industry partners to advance automotive electronics and IoT applications.
Uwe Meyer-Baese is an Associate Professor in the Electrical and Computer Engineering Department at the FAMU-FSU College of Engineering. He holds a Ph.D. (Dr.-Ing. habil) from Darmstadt University of Technology, Germany. His research focuses on Digital Signal Processing with FPGAs, VLSI design, and medical imaging applications. He has authored over 100 publications, 5 books, and holds 3 patents. He has been recognized with awards such as the Humboldt Fellowship (2009) and the FAMU-FSU Teaching Award (2007). Education History: Dr.-Ing. habil (Venia Legendi), Darmstadt University of Technology, Germany, 2003 Ph.D. (Dr. Ing.), Darmstadt University of Technology, Germany, 1995 M.S., Darmstadt University of Technology, Germany, 1989 Research Interests: FPGA-based embedded systems and real-time DSP Low-power VLSI architectures Medical image processing (e.g., breast MRI, brain tumor analysis) Hardware security and intellectual property protection Graph theory applications in biological networks Recent work includes advancements in FPGA implementations for microprocessor systems, brain network controllability studies, and AI-driven medical diagnostics. His lab focuses on bridging hardware design with biomedical applications, emphasizing practical implementations through FPGA platforms. Awards: Max-Kade Award in Neuroengineering (1997) ECE Department Research Award (2005) Humboldt Fellowship (2009) FAMU-FSU Teaching Award (2007) He has advised over 60 master’s theses and contributed to major grants in FPGA-based medical systems. His book Digital Signal Processing with Field Programmable Gate Arrays is a widely used textbook in the field.
Nele Mentens is a full professor at both KU Leuven and Leiden University, where she leads cutting-edge research in applied cryptography, hardware security, and secure embedded systems. At KU Leuven, she is affiliated with the Faculty of Engineering Technology and the Electrical Engineering Department (ESAT), leading the Emerging Technologies, Systems & Security (ES&S) research group at the Diepenbeek campus. Simultaneously, she holds a full professorship at Leiden University’s Leiden Institute of Advanced Computer Science (LIACS), focusing on applied cryptography and security. She has been instrumental in numerous national and international research initiatives, including Horizon Europe and NWO-funded projects. Full Professor, KU Leuven (since 2023) Full Professor, Leiden University (since 2020) Associate Professor, KU Leuven (2014–2023) Post-doctoral Researcher & Lecturer, KHLim / KU Leuven (2007–2014) Ph.D. in Engineering Science, KU Leuven (2007) M.Sc. in Electrical Engineering, KU Leuven (2003) Her research focuses on secure and efficient hardware design, particularly for cryptographic applications on FPGAs, reconfigurable architectures, IoT security, and neuromorphic computing. She explores physical attack resistance, side-channel analysis protection, and trusted computing architectures, with applications in healthcare, industrial monitoring, and endpoint AI. Her work bridges theoretical cryptography with practical hardware implementations, emphasizing energy efficiency and real-time performance. The 15 most recent publications reflect a strong trend toward secure, energy-efficient, and intelligent embedded systems. Topics include neuromorphic AI accelerators, trusted IoT architectures, dynamic reconfiguration for side-channel protection, and secure medical data processing. These works span disciplines such as computer architecture, cybersecurity, digital design, and embedded systems, with a focus on hardware-software co-design and real-world deployment. Nele Mentens has received recognition for her contributions, including: Best Paper Award, DATE'16 Best Paper Nomination, AsianHOST'17 Best Paper Award, CHES'19 She has supervised over 15 Ph.D. students and post-docs, both current and former, and has served as principal investigator in approximately 25 funded research projects. Her work has attracted significant grants from Horizon Europe, NWO, FWO, and national innovation programs. She actively contributes to the academic community through editorial roles in top journals and leadership in major conferences. Nele Mentens leads the ES&S research group at KU Leuven and collaborates closely with LIACS at Leiden University. Her team includes Ph.D. students, post-docs, and research experts working on projects like NimbleAI, NeuroSoC, and TrustedIoT. She has also established secure electronics labs through infrastructure grants and maintains strong international ties with institutions such as EPFL, Ruhr University Bochum, and ETH Zurich.
Tanvir Arafin serves as an Assistant Professor in the Department of Cyber Security Engineering at George Mason University, where his research focuses on hardware security and trust mechanisms for emerging computing platforms. With publications in premier venues including IEEE Transactions on Very Large Scale Integration Systems, IEEE Transactions on Computers, and ACM International Conference on Computer-Aided Design, he addresses critical security challenges in next-generation systems through rigorous hardware-software co-design approaches. His research portfolio spans Hardware Security, Trusted Computing, and IoT Security, with specialized expertise in Side-Channel Attacks and Secure Hardware Design. Dr. Arafin investigates electromagnetic side-channel vulnerabilities in O-RAN networks, develops countermeasures for autonomous vehicle cybersecurity, and pioneers RRAM-based security solutions for memory-constrained devices. His work bridges theoretical security models with practical implementations, emphasizing real-world applicability in edge computing environments and autonomous navigation systems. Current projects explore machine learning integration for anomaly detection in connected vehicles and secure acceleration of cryptographic operations. Analysis of Dr. Arafin's 2022-2025 publications reveals strategic focus areas: electromagnetic fingerprinting for radio units in O-RAN (2025), spatial acceleration of Kolmogorov-Arnold Networks (2025), and NTT-based cryptography accelerators (2024). His research demonstrates consistent innovation in securing autonomous navigation systems and edge devices, with emerging work on in-memory computing architectures using resistive memory technologies. Key trends include hardware-centric defense against model inversion attacks, voltage overscaling for lightweight authentication, and robust multi-robot coordination in dynamic environments. Scientific Awards: No scientific awards, fellowships, or medals were documented in the source materials. Dr. Arafin leads significant collaborative research, including the NSF CISE-MSI grant (DP: CNS) for edge-based robust multi-robot systems. His educational initiatives feature Capture-the-Flag competitions targeting underrepresented students in cybersecurity. Current grant activities emphasize practical security solutions for autonomous navigation, multi-robot coordination, and IoT edge devices, with demonstrated focus on translating research into deployable countermeasures for real-world threats in dynamic operational environments.
Mohammad Sadoghi is a Professor at the University of California, Davis, with former affiliations at Purdue University, IBM T.J. Watson Research Center, and the University of Toronto. His research focuses on distributed systems, blockchain technologies, consensus protocols, and fault-tolerant computing. He has contributed extensively to transaction processing, stream processing architectures, and the integration of edge-cloud systems with blockchain frameworks. Current Affiliation: University of California, Davis Former Affiliations: Purdue University, IBM, University of Toronto Research Interests include consensus algorithms, Byzantine fault tolerance, distributed ledger technologies, and scalable data processing. He has pioneered systems like ResilientDB and ByShard, addressing challenges in global-scale distributed systems and blockchain fabrics. His work bridges theoretical foundations with practical implementations, emphasizing real-world applications in edge computing and hybrid cloud-edge environments. Key publications highlight advancements in consensus protocols, blockchain scalability, and fault-tolerant architectures. Recent trends in his work focus on concurrent consensus mechanisms, DAG-based systems, and secure geo-replication. Contributions span both academic publications and industry-oriented solutions, such as the Bedrock platform for BFT protocol analysis. Grants and advising roles are implied through his extensive research output, though specific grants are not detailed in the provided text. His collaborations include projects on self-curating databases (e.g., L-Store) and systems like SplitJoin for stream processing.
Renaud Pacalet is a Researcher at Institut Mines-Télécom – Télécom Paris , affiliated with the Communications and Electronics (Comelec) Department and the System on Chip (LabSoc) research team under the Information Processing and Communication Laboratory (LTCI). His work spans hardware security, embedded systems, and software-defined radio (SDR) architectures. Current Research: Hardware security, side-channel attacks (power, timing, fault injection), RISC-V security analysis using gem5, FPGA scheduling for cloud data centers, and model-driven design methodologies. Past Research: Hardware acceleration for ray tracing, SDR front-end processing, SoC security, and memory bus protection (SecBus project). Teaching: Courses on Digital Systems, Computer Architecture, and Hardware Security at EURECOM, including lab sessions on side-channel attacks and fault analysis. Email: renaud.pacalet@telecom-paris.fr Contact: Télécom ParisTech, Campus SophiaTech, 450 route des Chappes 06410 Biot, France
Tarik Graba is a Lecturer at Télécom Paris and a member of the Secure and Safe Hardware (SSH) research team within the Information Processing and Communication Laboratory (LTCI) department. His work focuses on hardware security, embedded systems, and cryptographic implementation. Education: Not explicitly mentioned Current Affiliations: Télécom Paris (Faculty), LTCI, SSH Team His research explores designing secure and reliable integrated systems , with emphasis on managing complexity, power consumption, and flexibility in embedded environments. He contributes to side-channel analysis , lightweight cryptographic algorithms , and hardware-based security mechanisms . The 15 most recent publications highlight his work in lightweight cryptography , hardware security , and embedded system optimization , particularly focusing on RISC-V extensions , side-channel leakage , TRNG circuits , and secure cryptographic processors . Scientific Awards Academic Palms award, Télécom Paris (2021) Tarik Graba collaborates extensively in hardware security research and has advised multiple projects on physical security countermeasures and embedded cryptographic systems . He works with teams like the SSH Laboratory to develop secure hardware architectures.
Stanislaw Radziszowski is a Professor in the Department of Computer Science at Rochester Institute of Technology's Golisano College of Computing and Information Sciences. He has been at RIT since 1984, after working at the National Autonomous University of Mexico from 1980-1984. His academic career includes multiple visiting positions at the Australian National University in the 1990s and ongoing collaborations with institutions in Poland. Radziszowski earned his Ph.D. in Mathematics and Computer Science from the University of Warsaw in 1980, advised by Antoni Kreczmar and Andrzej Salwicki. His educational background includes BS and MS degrees from the same institution. Dr. Radziszowski's primary research focuses on combinatorial computing, with special emphasis on Ramsey theory and computational design theory. His "Small Ramsey Numbers" survey has become a standard reference in the field. More recently, he has expanded into applied cryptography, particularly post-quantum cryptography, leading to collaborations with the Computer Engineering Department. His work often combines theoretical insights with practical computational approaches to solve classical problems in combinatorics and graph theory. His recent publications demonstrate a growing focus on cryptographic applications, including post-quantum cryptography education, analysis of the MK-3 Authenticated Encryption Algorithm, and homomorphic encryption implementations. These works reflect his ability to bridge theoretical mathematics with practical security applications, particularly in hardware implementations and side-channel resistance. Dr. Radziszowski has made significant contributions to Ramsey theory, most notably computing R(4,5)=25 with Brendan McKay and improving bounds for R(5,5) and R(4,6). His survey "Small Ramsey Numbers" is a regularly updated reference in the field. He has also contributed to computational design theory, proving nonexistence of certain block designs. As an educator, Radziszowski teaches theory-oriented courses including Introduction to Cryptography, Foundations of Cryptography, and Quantum-Resistant Cryptography. He has developed specialized courses on combinatorial computing and has supervised numerous MS theses and projects. His recent work on post-quantum cryptography has led to educational initiatives in this emerging field. Dr. Radziszowski maintains active research collaborations, particularly with Xiaodong Xu on Ramsey and Folkman problems, and with Marcin Lukowiak on cryptographic implementations. His work often bridges the gap between theoretical mathematics and practical computing applications.
