Luca Benini is a Full Professor at the Department of Information Technology and Electrical Engineering at ETH Zurich. He works at the Institute for Integrated Systems, located at Gloriastrasse 35, 8092 Zurich, Switzerland. His contact number is +41 44 632 66 64. Research Interests: Focus on VLSI design and FPGA-based systems development. Teaching: Offers the course VLSI 1: HDL Based Design for FPGAs in the Fall semester 2025. Contact: lbenini@iis.ee.ethz.ch
Benjamin Carrison-Schafer is an Associate Professor and Assistant Dean for Graduate Student Success at the Department of Electrical and Computer Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas. He leads the Design Automation and Reconfigurable Computing Laboratory (DARClab), focusing on systems, high-level design, and programming methodologies for VLSI computing systems and FPGAs. Education: MBA from McGill University, Canada (2012) PhD in Electrical and Electronic Engineering from University of Birmingham, UK (2003) Research Interests: His work spans modeling, analysis, synthesis, optimization, and implementation of VLSI systems. Current projects include: Approximate Computing, High-Level Synthesis Design Space Exploration, Hardware Security, Behavioral MPSoC Optimization, and Automatic Fault-Tolerant System Generation. His research blends theory and practice, using analytical and experimental techniques to solve real-world problems. Publication Trends: Recent publications demonstrate strong focus on hardware security, FPGA optimization, and automated design methodologies. Key themes include High-Level Synthesis innovations, hardware acceleration techniques, and cross-disciplinary applications of reconfigurable computing. His work frequently addresses challenges in hardware trustworthiness, energy efficiency, and design automation scalability. Professional Activities: Associate Editor: IEEE Transactions on Sustainable Computing (2022-present) Conference Chair: ICCD 2024, DCAS 2024 Program Committee: ASP-DAC, DATE, FCCM, GLSVLSI Advising & Labs: Supervises multiple PhD and Master's students at DARClab. Current research includes domain-specific architecture design, hardware security, sustainable computing, and ML for VLSI design. The lab collaborates with industry partners like Renesas Electronics and develops commercial tools through spin-off company highX Technologies.
Bahar Asgari is an Assistant Professor in the Department of Computer Science at the University of Maryland, College Park. She holds appointments in CS, UMIACS, and ECE, and directs the Computer Architecture and Systems Lab (CASL). Her research focuses on domain-specific architecture design, near memory processing, and reconfigurable computing. Before joining UMD, she worked at Google, contributing to system optimization and memory utilization strategies. Education: Ph.D., Georgia Institute of Technology, 2021. Research Interests: Developing energy-efficient architectures for sparse problems, scientific computing acceleration, FPGA optimizations, and reconfigurable hardware systems. Her work addresses challenges in memory efficiency, parallelization, and hardware-software co-design across domains like machine learning and IoT. Key Awards: 2024 UMD Excellence in Teaching Award 2023 DOE Early Career Award Advising & Grants: Supervises 9 graduate students and leads projects sponsored by NSF, DOE, and industry partnerships. Her lab explores systolic arrays, near-data processing, and fault-tolerant computing. Labs/Teams: Directs CASL, which builds next-generation computing systems through hardware innovation and algorithm-architecture co-design.
Prof. Dr. Timothy Roscoe is a Full Professor in the Department of Computer Science at ETH Zurich. His research focuses on operating systems, networking, and distributed systems. He was inducted as an ACM Fellow in 2014 for contributions to these fields. Previously, he worked at Intel Research Berkeley, UC Berkeley (Adjunct Professor), and Sprint Labs. His work includes foundational contributions to systems like PlanetLab, P2 Declarative Networking, and the Nemesis OS. Roscoe holds a PhD from the University of Cambridge and has led projects in cloud computing, wide-area network measurement, and secure systems design. His current research emphasizes hardware-software co-design, formal verification of systems, and scalable memory architectures. Education: PhD in Computer Science, University of Cambridge (1995) Key Roles: Principal Researcher at Intel Berkeley Lab, Visiting Researcher at National ICT Australia Research Highlights: Contributions to distributed systems (PlanetLab), declarative networking (P2), and secure microkernels (seL4 integration). Current projects address challenges in disaggregated memory systems, coherent interconnects, and trustworthy embedded systems. Awards: ACM Fellow (2014), numerous grants and industry collaborations. Labs/Teams: Systems Group at ETH Zurich, focusing on OS design, hardware architectures, and formal methods.
Jan Madsen is a Professor at DTU Compute, Technical University of Denmark, and Head of the Embedded Systems Engineering section. His research focuses on system-level modeling and design of embedded computing systems, particularly cyber-physical systems, microfluidic biochips, and synthetic biology applications. Develops design automation tools and methodologies for embedded systems Supervises numerous PhD students and leads major research projects Research Interests Key areas include: Embedded systems-on-a-chip Cyber-Physical Systems (Internet-of-Things) Microfluidic Lab-on-Chip devices Synthetic biology with molecular computing Design, modeling, and optimization of complex systems Scientific Awards DATE Fellow (2019) IEEE CEDA Outstanding Recognition (2019) DTU Scientific Advise Award (2013) Best Paper Awards at MECO (2013) and CASES (2009) Jorck’s Foundation Research Award (1995) Publications His 14+ journal papers and 115+ conference papers demonstrate expertise in: SystemC-based modeling frameworks Energy-aware sensor networks Self-healing eDNA architectures Microfluidic biochip synthesis RTOS modeling and MPSoC exploration
André DeHon is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering at the University of Pennsylvania, affiliated with Electrical and Systems Engineering (ESE) and Computer and Information Science (CIS). He chairs the Computer Engineering (CMPE) program and directs the CyberSavvy Security Center. His research focuses on reconfigurable computing, FPGA architectures, computer security, and energy-efficient hardware design. He holds a Ph.D. and M.S. from MIT and a B.S. from MIT's Lincoln School. Research interests include reconfigurable computing, FPGA interconnect, hardware security, and fault-tolerant systems. Notable achievements include the SEVER & PROTECT DARPA award and IEEE/ACM Fellowships. Recent work addresses fast FPGA compilation (HiPR, PLD), security through compartmentalization (μSCOPE, SCALPEL), and partial reconfiguration techniques. Teaching includes courses on hardware security, system-on-chip architecture, and digital audio basics. Over 200 publications span FPGA design, network-on-chip optimization, and molecular-scale computing. His labs (Implementation of Computation Group) explore physical implementation of computations through hardware-software co-design.
Affiliation & Education Scott Hauck is a Professor at the University of Washington's Department of Electrical & Computer Engineering and an Adjunct Professor in Computer Science & Engineering. He leads the Adaptive Computing Machines and Emulators (ACME) Lab . He earned his BS in EECS from UC Berkeley (1990), and MS/PhD in CSE from the University of Washington (1992/1995). Research Focus Dr. Hauck specializes in FPGA-based reconfigurable computing with applications in: Quantum Computing: FPGA controllers for trapped-ion quantum systems enabling precise laser control and quantum state readout. Medical Imaging: Portable radiation sensors for personalized cancer therapy and PET scanner enhancements. High-Energy Physics: FPGA readout systems for ATLAS pixel detectors at CERN's Large Hadron Collider. AI Acceleration: Real-time machine learning inference for scientific applications via projects like hls4ml. His work bridges hardware innovation with computational physics, emphasizing real-time processing and low-latency systems. Publication Trends Recent research focuses on FPGA-accelerated machine learning for particle physics (e.g., transformer networks for LHC trigger systems) and quantum computing instrumentation. Earlier work established foundations in reconfigurable computing architectures and medical imaging electronics. Awards & Recognition Distinguished Teaching Award, University of Washington (2010) Advising & Funding Leads the ACME Lab with extensive funding from NSF, DARPA, NIH, DOE, and industry partners including Intel, Xilinx, and Microsoft. Mentored over 30 MS/PhD students in VLSI, reconfigurable systems, and scientific computing. Collaborations & Labs Directs the ACME Lab (EE1-307), collaborating with UW Radiology (Prof. Robert Miyaoka), UW Physics (Prof. Shih-Chieh Hsu), and Drexel University (Prof. Josh Agar). Projects include quantum control systems, LHC readout electronics, and medical sensor networks.
André DeHon is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering at the University of Pennsylvania, with affiliations in the Electrical and Systems Engineering (ESE) and Computer and Information Science (CIS) departments. He founded the Penn Computer Engineering (CMPE) program and directs the DARPA-sponsored CyberSavvy Security Center. His research spans reconfigurable computing, FPGA architecture, interconnect design, hardware security, and energy efficiency, with a focus on adapting to fabrication imperfections and runtime variability. His work explores programmable substrates (e.g., CMOS VLSI, molecular electronics) and algorithmic mappings to create resilient, efficient systems. Current projects include runtime feedback mechanisms (REFINE), partial reconfiguration (ExHiPR), and security frameworks like SCALPEL and μSCOPE. Recent publications highlight advancements in FPGA compilation (PLD, HiPR), security (SCALPEL, μSCOPE), and interconnect optimization (Asymmetry in NoC). These studies intersect computer architecture, security, and embedded systems. Scientific awards and recognitions: 2023 IEEE Fellow 2020 IEEE Mary Kenneth Keller Teaching Award 2018 ACM Fellow TCFPGA Hall of Fame (2019) Best Paper at ICFPT 2015 Academic leadership: He chairs the ACM/SIGDA Technical Committee on FPGAs and Reconfigurable Computing, previously held faculty roles at Caltech (1999–2006), and was a postdoc at UC Berkeley (1996–1999). Education includes MIT SB (1990), SM (1993), and PhD (1996) in Electrical Engineering and Computer Science.
Zhonghai Lu is a Professor of Electronic Systems Design (specializing in Dependable and Autonomous Systems) at KTH Royal Institute of Technology, part of the Department of Electrical Engineering in the School of Electrical Engineering and Computer Science (EECS). He serves as Program Director for KTH's Embedded Systems master's program and Director of Studies at the Division of Electronics and Embedded Systems. His research focuses on Network-on-Chip (NoC), computer architecture, embedded systems, and Prognostics and Health Management (PHM) of power electronics. He leads a research group exploring in-network processing and embedded intelligence, transforming passive networks into active computational frameworks. Lu holds a BSc from Beijing Normal University (1989), MSc and PhD from KTH (2002, 2007), and an MBA in Innovation and Growth from the University of Turku (2012). He has authored over 240 scientific papers, including journal articles and peer-reviewed conferences, with notable recognitions such as Best Paper Awards at NOCS’2015 and EU HiPEAC, and a Featured Paper in IEEE Transactions on Computers (2020). He serves as Associate Editor for ACM Transactions on Architecture and Code Optimization (TACO) and has chaired major conferences like HiPEAC’2017 and NOCS’2018. His research group’s recent work includes integrating AI into hardware acceleration, fault-tolerant neural networks, and RUL estimation for power electronics using recurrent neural networks. Lu has secured grants from the Swedish Research Council and Intel Corporation and developed courses like IL2230 (Hardware Architectures for Deep Learning) and IL2233 (Embedded Intelligence), pioneering embedded AI education at KTH. Education: BSc (Beijing Normal University), MSc/PhD (KTH), MBA (University of Turku) Awards: Best Paper Awards (NOCS, EU HiPEAC), Swedish Research Council Grants, Intel Research Gifts Labs/Teams: Research Group on In-Network Processing and Embedded Intelligence
Josiah Hester is Associate Professor of Interactive Computing and Computer Science at Georgia Tech's College of Computing, where he also directs the Center for Advancing Responsible Computing and the Ka Moamoa – Ubiquitous and Mobile Computing Lab . His research focuses on sustainable, battery-free computing systems for health, conservation, and education, informed by his Native Hawaiian heritage. Education: Ph.D. in Computer Science, Clemson University, 2017 B.S. in Computer Science, Clemson University Honors College, 2011 Research Interests: Hester’s group pioneers intermittent computing —devices that harvest ambient energy (solar, radio, thermal, microbial) and operate reliably despite frequent power loss. Applications span: Large-scale conservation sensing with Indigenous communities Battery-free health wearables (smart masks, implantables) Educational tools for sustainable design Carbon-aware IoT and recyclable robotics Recent Work & Trends: His 2024–2025 publications unveil soil-powered sensors, recyclable electronics, and culturally-grounded CS education tools. A consistent theme is co-design with underserved communities and embedding sustainability metrics at every layer—from hardware to curriculum. Scientific Awards: Presidential Early Career Award for Scientists and Engineers (PECASE) – 2025 Alfred P. Sloan Fellowship – 2022 NSF CAREER Award – 2022 Popular Science “Brilliant 10” – 2021 3M Non-Tenured Faculty Award – 2021 Multiple best-paper & best-presentation awards Grants & Teams: Hester’s lab is supported by >$50 million in active funding from NSF, NIH (ARPA-H), DARPA, DoD, Sloan, VMware, and 3M. He leads interdisciplinary teams on projects such as: $35 million ARPA-H bioelectronics initiative for diabetes and cancer $5 million NSF “Coastlines and People” Hub for Manoomin conservation $2 million NSF-DELPHI sustainable edge device design Laboratory & Mentorship: The Ka Moamoa Lab (named with Hawaiian meaning “lamp of the moamoa fish”) hosts graduate, undergraduate, and post-doctoral researchers. Hester actively recruits Native and Indigenous students and has mentored award-winning advisees such as Nivedita Arora (ACM Doctoral Dissertation Award 2024).
Dr. Hiren Patel is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. He holds a Doctorate in Computer Engineering from Virginia Tech and previously worked as a postdoctoral fellow at UC Berkeley under Edward A. Lee. His research focuses on real-time embedded systems, computer architecture, machine learning hardware, and cybersecurity. He teaches courses like ECE 150 (Programming), ECE 320/429 (Computer Architecture), and ECE 327 (Digital Systems). Research Interests: Cyber-physical systems and hybrid architectures Hardware/software co-design methodologies Predictable cache coherence protocols IoT and edge computing systems Security in embedded and real-time systems Recent work emphasizes cache coherence solutions for safety-critical systems and GPU acceleration strategies. His publications address challenges in multicore predictability, FPGA bandwidth optimization, and autonomous robotics orchestration. No specific awards are listed, though his extensive publication record indicates significant contributions to embedded systems research. He currently oversees graduate student applications focusing on his core research areas.
Christof Paar is a Professor of Embedded Security at Ruhr University Bochum's Faculty of Computer Science. His work focuses on hardware security, cryptography, and embedded systems security. He leads the Embedded Security Group within the CASE Cluster of Excellence (Cyber Security in the Age of Large-Scale Attacks), addressing cutting-edge challenges in hardware Trojans, side-channel attacks, and cryptographic engineering. His research spans FPGA and IoT security, with contributions to physical-layer security, wireless jamming defenses, and tamper-resistant systems. Research Interests: Paar's expertise lies in hardware-software co-design for security, with a focus on embedded systems. His work includes analyzing vulnerabilities in FPGAs, developing countermeasures against side-channel attacks, and exploring physical-layer security mechanisms. He also investigates the human factors in hardware reverse engineering and the implications of adversarial machine learning on security systems. Notable Work: Recent publications highlight breakthroughs in detecting hardware Trojans across CMOS generations, breaking industry-standard IP protection mechanisms (IEEE 1735), and proposing novel defenses like IRShield against adversarial wireless sensing. His group actively contributes to standards for secure embedded systems and IoT devices, emphasizing practical implementations.
Soheil Salehi is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at the University of Arizona, with a joint appointment in Systems and Industrial Engineering. He is the Director of the Privacy-preserving, Intelligent, and Secure Computing (PRISM) Lab, established in August 2022. Prior to this, he was an NSF-Sponsored Computing Innovation Fellow and Postdoctoral Research Fellow at the University of California, Davis. Ph.D., Electrical and Computer Engineering, University of Central Florida, 2020 M.S., Electrical and Computer Engineering, University of Central Florida, 2016 B.S., Isfahan University of Technology, Iran, 2014 Dr. Salehi's research focuses on the intersection of hardware, AI, and security. His work spans hardware and AI-enabled security in IoT , Generative AI for hardware design and security , neuromorphic and biologically-inspired AI hardware , emerging spin-based devices , reconfigurable architectures , low-power VLSI circuits , and digital twins and mixed reality for semiconductor workforce development . He also explores the application of Generative AI in personalized education . His recent publications, spanning 2023–2025, reveal a strong trend toward integrating AI and machine learning into hardware security and design. Key themes include automated secure IC design flows , AI-driven hardware obfuscation , firmware and side-channel attack analysis , security in neuromorphic and spiking neural networks , and educational frameworks using digital twins and generative models . His work appears in top venues like DAC, ICCAD, USENIX Security, IEEE TCAS-I, and ISCAS. Outstanding Reviewer Award, IEEE/ACM Design Automation Conference (DAC), 2023 Best Presentation of the Symposium Award, UC Davis Postdoctoral Research Symposium, 2021 UCF Excellence by a Graduate Teaching Assistant (University-Level), 2016 Nominated for 30-under-30 Award, UCF, 2020 Nominated for Postdoctoral Research Excellence Award, UC Davis, 2022 Dr. Salehi has secured significant research funding as PI and Co-PI, including a $300K NSF SaTC EAGER grant on Generative AI-based Personalized Cybersecurity Tutor, a $174,000 University of Arizona PIF Award, and multiple RII grants totaling over $198K. He has also received industry funding from CHEST. He actively mentors students and leads the PRISM Lab, which focuses on privacy-preserving and intelligent secure computing. His service includes roles as Technical Program Committee (TPC) Member and Session Chair at premier conferences such as DAC, ICCAD, CCS, NDSS, and GLSVLSI. The PRISM Lab, under his direction, conducts cutting-edge research in secure and intelligent hardware systems, with applications in IoT, edge computing, and workforce development. The lab emphasizes interdisciplinary collaboration and innovation in both research and education.
Prof. Baker Mohammad serves as Professor and Director of the System on Chip Lab in the Department of Computer and Information Engineering at Khalifa University. With over 15 years of industrial experience at Intel and Qualcomm designing microprocessors and DSP chips, he bridges academic research with real-world engineering challenges in high-performance computing and low-power systems. His educational background includes: Ph.D. in Electrical and Computer Engineering, University of Texas at Austin (2008) M.S. in Electrical and Computer Engineering, Arizona State University B.S. in Electrical Engineering, University of New Mexico Dr. Mohammad's research spans cutting-edge domains where VLSI design converges with AI acceleration and emerging memory technologies . His work pioneers Memristor applications in environmental sensing (radiation, vacuum, glucose) and neuromorphic computing, while advancing energy harvesting systems for wearable electronics. The integration of in-memory computing with security primitives represents a paradigm shift in hardware design, moving beyond traditional CMOS limitations. His publication trajectory reveals accelerating focus on self-powered neuromorphic systems and RRAM-based architectures, with recent work (2021-2023) emphasizing hardware-software co-design for edge AI. Over 75% of his recent publications involve cross-disciplinary collaborations spanning materials science, chemistry, and biomedical engineering. Notable scientific recognition includes: IEEE TVLSI Best Paper Award 2016 IEEE MWSCAS Myrill B. Reed Best Paper Award Qualcomm Qstar Award for Performance Leadership KUSTAR IP Excellence Award Multiple SRC Techon Best Session Papers As a dedicated mentor, he has supervised over 15 graduate students while securing competitive funding from Khalifa University, ADEK, Qualcomm, Tii, and UAE space agencies. His grant portfolio demonstrates exceptional translational impact, converting fundamental research in memristive devices into drone flight computers and medical sensors. Current projects integrate academic rigor with industrial deployment timelines. The System on Chip Lab operates as a multidisciplinary hub where semiconductor physicists collaborate with AI researchers to develop RISC-V-based secure processors and piezoelectric nanogenerator systems. Recent expansions include partnerships with Tii for aerospace applications and medical device startups for glucose monitoring technology.
Professor Wayne Luk is a Professor of Computer Engineering at the Department of Computing, Faculty of Engineering, Imperial College London. He leads the Programming Languages and Systems Section and the Custom Computing Research Group, and directs the EPSRC Centre for Doctoral Training in High-performance Embedded and Distributed Systems and the Centre for Advanced Financial Engineering. He previously served as a Visiting Professor at Stanford University from 2006 to 2009. His research spans FPGA acceleration, quantum computing, deep learning optimization, and algorithm-hardware co-design, with affiliations to the CRUK Convergence Science Centre and the Engineering Secure Software Systems group. His research interests include computational modeling for particle physics, causal discovery in agent-based systems, and high-throughput digital electronics. Notable contributions include FPGA-accelerated algorithms for neural networks, quantum circuit simulation, and Bayesian optimization frameworks. His work emphasizes practical applications of reconfigurable hardware in fields like medical imaging, high-energy physics, and financial systems. Professor Luk is a Fellow of the Royal Academy of Engineering, IEEE, and BCS. His publications focus on advancing hardware-aware machine learning, FPGA-based acceleration techniques, and scalable design methodologies. His research bridges theoretical computer science with applied engineering, addressing challenges in real-time systems, embedded computing, and next-generation computing architectures. His academic leadership includes directing interdisciplinary centers and training programs, fostering collaboration across computing, engineering, and physics. Current projects explore quantum computing tools, causal inference systems, and high-performance graph neural networks for particle physics applications.
