جست‌وجوی استاد و پژوهشگر

• Computer Architecture
• Hardware Design
• Signal Processing
• +۷ مورد دیگر

Prof. Dr.-Ing. Holger Blume serves as Vice President for Research and Transfer at Leibniz University Hannover while maintaining his academic position as Professor in the Architectures and Systems Section within the Faculty of Electrical Engineering and Computer Science. He holds multiple leadership positions including Chairperson of the Research Commission and Central Ethics Committee, Executive Board member of eNIFE (Leibniz Research Initiative for Neurosciences), and membership in both the Laboratory of Nano and Quantum Engineering and L3S Research Centre. His research interests span computer architecture, hardware design, signal processing, AI accelerators, hearing aid technology, and biomedical engineering. His work bridges theoretical computer science with practical applications in automotive systems, medical devices, and quantum engineering. Professor Blume's research demonstrates strong interdisciplinary connections between electrical engineering, computer science, and biomedical applications, with particular emphasis on hardware-oriented solutions for real-world problems. Analysis of his recent publications (2023-2025) reveals a strong focus on hardware acceleration for AI and signal processing applications, particularly in automotive radar/LiDAR systems and hearing aid technology. His work shows consistent innovation in RISC-V processor design, specialized hardware for mathematical functions, and biomedical applications of engineering principles. The research demonstrates a clear trajectory toward energy-efficient, specialized computing architectures for specific application domains. As Vice President for Research and Transfer, Professor Blume oversees significant research initiatives at Leibniz University Hannover, which hosts multiple Clusters of Excellence including PhoenixD (Photonics, Optics, and Engineering), QuantumFrontiers, and Hearing4all. The university participates in numerous collaborative research centers and junior research groups funded by DFG, BMBF, and EU programs. Professor Blume is actively involved in multiple research facilities including the Laboratory of Nano and Quantum Engineering and the L3S Research Centre. His work connects with Leibniz University's research focuses on optical technologies, quantum optics and gravitational physics, and biomedical research and technology. His leadership positions indicate strong involvement in shaping the research strategy and ethical framework of the university's scientific endeavors.

Stephen A. Edwardsمشاهده پروفایل

دانشیار

• Embedded Systems
• Real-Time Systems
• Hardware Synthesis
• +۵ مورد دیگر

Stephen A. Edwards is an Associate Professor at the Computer Science Department of Columbia University , where he explores automating software for embedded systems and real-time control . His work focuses on compiler techniques for languages like Esterel and domain-specific solutions for device drivers and communication protocols . Education : PhD in Electrical Engineering, University of California, Berkeley (1997) MS in Electrical Engineering, UC Berkeley (1994) BS in Electrical Engineering, California Institute of Technology (1992) Research Interests span hardware synthesis , functional programming , and synchronous languages . He develops domain-specific languages to bridge software and hardware, emphasizing determinism and timing precision in embedded systems. His group's work includes projects like the FHW compiler and the Sparse Synchronous Model . Article Trends show a focus on FPGA-based systems , garbage collection for accelerators, and parallel functional programming . These reflect his broader interests in hardware-software co-design and compiler optimization for real-time applications. Students : John Hui (2021-2024, Apple) Max Levatich (2020-) Richard Townsend (2013-2019, Tufts) Nalini Vasudevan (2007-2011, Google) Marcio Buss (2004-2008) Jia Zeng (2002-2008) Cristian Soviani (2002-2007, Synopsys) Consulting & Expert Services : He provides litigation support and expert witness services in patent cases involving software architecture and computer design , including ITC cases. Labs & Projects : Leads research on sparse synchronous systems and hardware synthesis , with initiatives like the GAPS CLOSURE Project and FHW Compiler for translating Haskell to System Verilog.

• Reconfigurable Computing
• Electronics Design Automation
• FPGA Design
• +۶ مورد دیگر

Andrea Guerrieri serves as an Associate Professor at the School of Engineering, University of Applied Sciences and Arts Western Switzerland Valais (HES-SO Valais-Wallis), specializing in reconfigurable computing and electronics design automation. His research has established significant industry impact through tools like DynaRapid and Dynamatic, with technology adopted by major semiconductor companies including MIPS, Intel, and AMD-Xilinx. BSc HES-SO in Industrial Systems - System-on-Chip specialization BSC HES-SO in Computer and Communication Systems - Digital Design specialization MSc HES-SO in Engineering - Embedded Hardware and Firmware specialization Professor Guerrieri's research focuses on reconfigurable computing, electronics design automation (EDA), and security, with particular emphasis on FPGA design, high-level synthesis, and post-quantum cryptography implementations. His work bridges the gap between theoretical computer architecture and practical hardware implementations, with strong applications in space technology and embedded security systems. His recent publications demonstrate increasing focus on energy-efficient implementations for space applications and quantum-resistant cryptographic systems. Analysis of his 15 most recent publications reveals a clear research trajectory toward optimizing FPGA implementations for post-quantum cryptography and space applications. His work consistently addresses the performance bottlenecks in high-level synthesis while maintaining practical applicability for industry partners like NASA, CERN, and major semiconductor companies. The recent surge in best paper awards (three in 2024 alone) reflects growing recognition of his contributions to efficient FPGA compilation techniques and cryptographic implementations. Scientific Awards: Best Paper Award at FPL 2024 Best Paper Award at HPEC 2024 Best Paper Award at ISFPGA 2020 Outstanding Short Paper Award at IEEE HPEC 2024 Outstanding TPC Member Award at DAC 2024 IEEE Senior Member (2021) Multiple Best Paper nominations (FCCM 2022, FPL 2022, HiPEAC 2022) Professor Guerrieri actively participates in international research projects including the DyReCte project (2019-2021) on dynamically reconfigurable cryptoengines for nano-satellites. He currently chairs the Onboard Computing topic for the Swiss consortium CHEESE affiliated with NASA SSERVI and collaborates extensively with industry partners including AMD-Xilinx, NVIDIA, Arm, NASA, and CERN, as well as academic institutions like ETH Zurich and University of Geneva. His current research focuses on developing next-generation EDA tools and reconfigurable computing platforms for both terrestrial and space applications. His laboratory work centers around FPGA-based prototyping and validation, with specialized facilities for space applications testing. Professor Guerrieri leads a research team that includes Andres Upegui, Quentin Berthet, Laurent Gantel, and Gabriel Da Silva Marques, focusing on practical implementations of reconfigurable architectures for security and space applications.

Sneha D. Goenkaمشاهده پروفایل

استادیار

• Computational Genomics
• Computer Systems Architecture
• High-Performance Computing
• +۵ مورد دیگر

Sneha D. Goenka is an Assistant Professor at Princeton University in the Department of Electrical and Computer Engineering, with associated faculty status in the Computer Science department. She earned her Ph.D. from Stanford University (2024) and dual B.Tech./M.Tech. degrees from IIT Bombay (2017). Her research bridges computer systems architecture and computational genomics to develop accelerated genomic pipelines. Education : Ph.D. (Electrical Engineering, Stanford 2024), Dual Degree (IIT Bombay 2017) Her work focuses on optimizing genomic data processing through hardware-software co-design, achieving speedups in clinical and evolutionary genomics. She led the development of the world's fastest genome diagnosis technique using nanopore sequencing and cloud computing. Recent publications highlight her expertise in GPU/FPGA acceleration (SegAlign, Darwin-WGA) and ultra-rapid variant detection pipelines. Her research has been published in top venues like Nature Biotechnology , New England Journal of Medicine , and SC/HPCA conferences . Scientific Awards : Stanford Centennial TA Award (2024) ACM Heidelberg Laureate Forum Young Researcher (2024) Forbes 30 Under 30 (Science) (2023) NVIDIA Graduate Fellow (2022) Cadence Women in Technology Scholar (2021) She advises students in her lab and has collaborated with institutions like Stanford Medicine, NVIDIA Research, and D.E. Shaw Research. She also contributed to the Pratham satellite project at IIT Bombay.

Tiantai Dengمشاهده پروفایل

مدرس

• FPGA-based Hardware Acceleration
• Sparse Processing Architecture for CNN and GEMM
• Number System and Approximation Computing
• +۳ مورد دیگر

Dr. Tiantai Deng is a Lecturer in Electronics and Digital Systems at the School of Electrical and Electronic Engineering , University of Sheffield (since 2021). His industrial background includes a senior research engineer role at HiSilicon/Huawei , where he focused on hardware architecture design for CNN, GEMM, and image/video processing on FPGAs/ASICs. Education: BEng, MSc, PhD Research interests span FPGA-based hardware acceleration , sparse processing architecture for CNN/GEMM, number system design , approximation computing , and high-level design environments . His work integrates algorithm-hardware co-optimization for efficiency in AI and mathematical computing. Recent publications emphasize neurodynamic systems for opinion modeling, parallel processing elements for ODE/AI acceleration, and low-power FPGA implementations for clustering/modulation classification. Earlier work addressed combustion dynamics and image processing pipelines. Contact: t.deng@sheffield.ac.uk | Office: G108, Sir Frederick Mappin Building, Sheffield S1 3JD | ORCID 0000-0003-4507-5746

• Energy-Efficient Computing
• Hardware Acceleration
• Machine Learning
• +۳ مورد دیگر

Dr. David Boland is a Senior Lecturer at the School of Electrical and Computer Engineering, University of Sydney. He holds an MEng and PhD from Imperial College London. His research focuses on energy-efficient hardware acceleration, particularly using FPGAs and application-specific integrated circuits (ASICs), to optimize computational efficiency in domains like machine learning and optical communications. He has contributed to projects involving custom hardware accelerators, federated learning for edge computing, and real-time signal processing. Education: MEng, Imperial College London, 2007 PhD, Imperial College London, 2012 Research Interests: Dr. Boland’s work emphasizes reducing computational overhead through customized hardware solutions. He explores techniques for minimizing unnecessary computations while maintaining accuracy, leveraging FPGA-based designs for parallelism and energy efficiency. Key areas include: Hardware acceleration for machine learning FPGA optimization for neural networks Energy-efficient algorithms for edge computing Online arithmetic and latency-accuracy trade-offs Grants & Collaborations: 2022: On-Board Federated Learning in Orbital Edge Computing (NSW Department of Industry) 2017: Fast Automated Anomaly Detection in Communication Networks (Defence Science & Technology Group) Affiliations: Member of the Net Zero Institute, collaborating on sustainable computing solutions.

• VLSI Design
• Wireless Communications (5G/6G)
• Massive MIMO
• +۵ مورد دیگر

Mohsin Abbas is an Assistant Professor (Tenure Track) in the Computing Sciences department at Tampere University, Finland. His research focuses on high-throughput, low-latency, and energy-efficient VLSI architectures for baseband processing systems, particularly channel code decoders. He has held roles including Research Assistant Professor at HKUST, Postdoctoral Fellow at McGill University, and Lead Engineer at ASTRI. Education: PhD in Electronics and Computer Engineering (2017), HKUST, under Prof. Chi-Ying Tsui MSc in Computer Science and Engineering (2011), Hanyang University, South Korea BSc in Computer Engineering (2007), University of Engineering and Technology Taxila, Pakistan Research Interests: VLSI Design (ASIC/FPGA) Wireless Communications (5G/6G) Massive MIMO and Compute-In-Memory (CiM) Channel Coding and Hardware Architecture Low-Latency Decoding Algorithms (e.g., GRAND) Energy-Efficient Systems and Green Communication Teaching Experience: HKUST: Digital Circuits and Systems (ELEC 2200), VLSI Design Automation (EESM 5020) Labs/Teams: Integrated Systems for Information Processing (ISIP) Lab, McGill University (2019–2022) HKUST’s ECE Department and ISIP Lab collaborations

Oliver Mischkeمشاهده پروفایل

پژوهشگر

• Side-Channel Cryptanalysis
• Efficient Cryptographic Implementation
• Hardware Security
• +۳ مورد دیگر

Dr. Oliver Mischke is an academic researcher focusing on hardware security and cryptographic implementations. He was affiliated with the Chair for Embedded Security at the Horst Görtz Institute for IT Security, Ruhr-University Bochum. His research emphasizes side-channel cryptanalysis, efficient cryptographic algorithms, and secure hardware design. Mischke completed his PhD in Security in Information Technology at Ruhr-University Bochum (2011–2013), with a year abroad at Purdue University (2007–2008). He has held roles as a Security Engineer (ESCRYPT GmbH) and an intern at Qualcomm's Product Security Group. His research interests include FPGA-based cryptographic implementations, fault analysis, and countermeasures against side-channel attacks. Notable contributions involve dynamic logic reconfiguration for FPGA security, glitch-resistant masking schemes, and evaluation of AES countermeasures. Mischke's publications span conferences like HOST, CHES, and IEEE venues, focusing on cryptographic hardware security, timing attacks, and secure embedded systems. His work bridges theoretical cryptography with practical hardware implementations, addressing vulnerabilities in reconfigurable and embedded systems. He has contributed to projects such as the MicroACP crypto-processor and IPSec core designs. His collaborations include prominent institutions and industry partners, reflecting a strong emphasis on applied security solutions.

• Post-Quantum Cryptography
• Hardware Implementation
• Embedded Systems Security
• +۷ مورد دیگر

Patrick Karl is a Researcher at the Chair of Security in Information Technology (Technische Universität München). He holds an M.Sc. degree and focuses on efficient hardware implementations for post-quantum cryptography , particularly hardware acceleration of digital signature algorithms on RISC-V platforms for embedded systems. His work addresses performance optimization, power/energy efficiency, and countermeasures against physical attacks such as side-channel and fault attacks . His research spans both FPGA prototyping and ASIC design , including tape-outs for security applications. He contributed to NIST submissions like CROSS , LESS , and FuLeeca , and has published extensively on topics including lattice-based cryptography, masked accelerators, and hardware API overhead for lightweight cryptography. Patrick has taught Lab Course ASIC Design of Hardware Accelerators for RISC-V since WS22/23 and Lab Course Crypto Implementation in SS22. His publications (15 most recent) highlight trends in post-quantum cryptographic hardware , RISC-V security , and physical attack countermeasures . He has presented at venues like RISC-V Summit Europe, COSADE, and FDTC.

Guillermo Payá Vayáمشاهده پروفایل

استاد

• Embedded Systems
• Processor Architecture
• FPGA Design
• +۵ مورد دیگر

Prof. Dr.-Ing. Guillermo Payá Vayá leads the Chair for Chip Design for Embedded Computing at Technical University of Braunschweig's Faculty of Electrical Engineering, Information Technology, and Physics. His research focuses on processor architecture design, FPGA/ASIC implementations, and optimization techniques for embedded systems, particularly in high-performance, low-power, and radiation-hardened computing domains. Primary research interests include: Application-Specific Instruction Set Processors (ASIPs) and compiler co-design Radiation effects characterization and fault-tolerant hardware Ultra-low-power processor architectures for embedded AI Hardware acceleration of neural networks and computer vision algorithms Memory subsystem optimization and parallel computing techniques Recent publications demonstrate strong emphasis on radiation-hardened electronics (35% of recent works), AI accelerator design (27%), and ultra-low-power systems (20%), with growing interest in biomedical applications. Experimental validation through FPGA prototyping and semiconductor testing is a consistent methodology across research domains. Leads research team investigating: Radiation-tolerant FPGA architectures (Trumann, Weide-Zaage) Vector processor optimization (Gesper, Thieu) Nano-scale controller design (Weißbrich) AI-hardware co-design (Kautz, Beyer)

Mohd. Tasleem Khanمشاهده پروفایل

استادیار

• Machine Learning/Artificial Intelligence
• Signal Processing
• Communication Systems
• +۴ مورد دیگر

Dr. Mohd. Tasleem Khan is an Assistant Professor at the Institute of Sensors, Signals, and Systems (ISSS), School of Engineering and Physical Sciences (EPS), Heriot-Watt University. Previously, he held roles as Principal Engineer at TSMC (2019), Assistant Professor at IIT Dhanbad (2020–2021), Research Consultant at KAUST (2020–2021), and Postdoctoral Researcher at Linköping University (2021–2024). He earned his Ph.D. in VLSI for signal processing and communication systems from IIT Guwahati (2019). His research focuses on Machine Learning/AI, Signal Processing, and Communication Systems, with expertise in VLSI architectures. Key contributions include energy-efficient designs for neural networks, adaptive filtering algorithms, and 6G systems. His work bridges theoretical algorithms with hardware implementation, emphasizing low-power and high-throughput solutions. Publications span circuits, systems, and interdisciplinary areas like biochemistry, showcasing his interdisciplinary approach. He has contributed to advancements in distributed arithmetic-based architectures, LMS filters, and FPGA implementations. Current affiliations include the Microwaves and Antenna Engineering Group at Heriot-Watt University, a global leader in wireless systems research.

• Integrated Circuits
• RF Circuit Design
• Low-Power Electronics
• +۳ مورد دیگر

Jean-Baptiste Bégueret is a researcher with extensive contributions to integrated circuits , RF design , and low-power electronics . His work spans analog , digital , and mixed-signal systems.

Sebastien Pillementمشاهده پروفایل

مدرس

• Computer Engineering
• Embedded Systems
• Computer Architecture
• +۳ مورد دیگر

Sébastien Pillement is a Lecturer at Polytech'Nantes, the College of Engineering of the University of Nantes, and a member of the ASIC research team within the IETR UMR 6164 laboratory. His career spans over 13 years at the IUT of Lannion (University of Rennes 1) before joining the University of Nantes in 2012. He holds a PhD in Computer Science from the University of Montpellier II (1998) and a Habilitation à Diriger des Recherches (HDR) from the University of Rennes 1 (2010). Current Research Focus: Dynamically Reconfigurable Architectures (DRA), Hardware Security, Fault-Tolerant Embedded Systems, NoC (Network-on-Chip), Design Methodologies. Teaching Areas: Digital Circuits, Computer Architecture, Operating Systems, Real-Time Systems, and Algorithms for Embedded Computing. His research explores flexible and efficient architectures for embedded systems, emphasizing real-time management, reliability, and security. Key article trends include RISC-V processors, neural network acceleration on MPSoC, formal verification of arithmetic circuits, and runtime FPGA scheduling. Collaborations span international institutions like the University of Toronto and CEA, as well as industrial partners such as STMicroelectronics and Thales. PhD Students : Current: Laureline Dubucq (Security & AI), Mustafa Ibrahim (Ultra-Low Power AI), Téo Biton (Runtime Anomaly Detection), Mohamed Amine Zhiri (Adaptive NoC), Juliette Pottier (RISC-V Protection). Graduates: Quentin Dariol (Neural Network Timing), Alexis Duhamel (FPGA Scheduling), Safouane Noubir (Security in Multi-Core Systems), Hai Dang Vu (Probabilistic Timing Analysis), David Pallier (Sensor Clock Synchronization). Projects : Current: ADAPTING (2023-2029), FITNESS (2023-2027), SEC-V (2022-2025), NOP (2021-2025). Past: SPARTE (2015-2018), ARDyT (2011-2015), FosFor (2008-2011).

Qinru Qiuمشاهده پروفایل

استاد

• Neuromorphic computing
• Machine learning
• Green computing
• +۵ مورد دیگر

Dr. Qinru Qiu is a Distinguished Professor in the Department of Electrical Engineering and Computer Science at Syracuse University. She holds a PhD in Electrical Engineering from the University of Southern California (2001) and a BS from Zhejiang University (1994). Her research focuses on neuromorphic computing, energy-efficient systems, and machine learning applications, emphasizing power and thermal management in embedded and high-performance computing systems. She leads NSF's Center for Alternative Sustainable and Intelligent Computing (ASIC) and serves on editorial boards of IEEE journals and conference committees. Education: PhD (USC, 2001), MS (USC, 1998), BS (Zhejiang University, 1994) Her research interests include neuromorphic architectures for cognitive applications, energy harvesting systems, and hardware-accelerated machine learning. Recent work explores in-memory computing with memristive devices and energy-efficient anomaly detection frameworks. She has published widely in top venues like IEEE/ACM conferences and journals. Notable awards include the NSF CAREER Award (2009), IEEE Region 1 Technological Innovation Award (2020), and ACM Distinguished Member (2022). She is an IEEE Fellow and served as CEDA Society Distinguished Lecturer (2023–2024). Dr. Qiu advises numerous graduate students in neuromorphic systems and energy-efficient computing. Her professional services include roles as Associate Editor for IEEE TNNLS and TCDS, and conference organizing roles at ISLPED and ICCAD.

• System-on-Chip (SoC) Design
• FPGA-Based High-Level Synthesis
• Real-Time Embedded Systems
• +۵ مورد دیگر

Timo Hämäläinen is a Professor of Computer Engineering at Tampere University, leading the Unit of Computing Sciences within the Faculty of Information Technology and Communication Sciences. He is a core member of the System-on-Chip research group and the Computer Engineering Team, actively contributing to the System-on-Chip Hub initiative. His research focuses on System-on-Chip (SoC) design methodologies, FPGA-based high-level synthesis, real-time embedded systems, and open-source hardware-software co-design frameworks like RISC-V and HEVC encoding. He has pioneered work on agile SoC development processes and validation techniques for large-scale hardware systems. Key research areas include: High-level synthesis (HLS) optimization for FPGAs Real-time processor architectures and context-switching latency reduction Formal verification of IP-XACT-compliant SoC designs Resilient RISC-V MPSoC implementations Hardware-accelerated algorithms for signal processing and networking His recent publications (2023-2025) emphasize agile SoC development frameworks, hardware-software co-design for real-time systems, and validation methodologies for large-scale embedded systems. He has contributed to open-source projects like Kvazaar HEVC encoder and the Kactus2 IP-XACT toolchain. Academic advising includes students such as Santéri Mäki-Äijö (formal verification), Arto Oinonen (RISC-V tooling), and Sakari Lahti (processor modeling). His work integrates academic research with industrial collaboration through frameworks like the Fault-slip-Through quality assessment methodology.