جست‌وجوی استاد و پژوهشگر

Giovanni De Micheliمشاهده پروفایل

استاد

• Integrated Circuit Design
• Hardware Synthesis
• Logic Optimization
• +۵ مورد دیگر

Giovanni De Micheli is a Full Professor at École Polytechnique Fédérale de Lausanne (EPFL), holding appointments in both the School of Computer and Communication Sciences (IC) and the School of Engineering (STI). He is affiliated with the Integrated Systems Laboratory (LSI) and serves as Scientific Director of EcoCloud. His primary office is located in INF 341 building at EPFL's Lausanne campus where he conducts research and teaching activities. Professor De Micheli's research spans multiple domains in electronic design automation and integrated circuit design. His primary interests include: Integrated Circuit Design and Hardware Synthesis Logic Optimization and Boolean Methods Nanoelectronics and 2D Electronics Quantum Computing and Emerging Technologies Low-Power Electronics and Energy-Efficient Systems Electronic Design Automation for Novel Computing Paradigms His recent publications demonstrate a strong focus on advancing logic synthesis techniques for both conventional and emerging technologies. Professor De Micheli's work bridges theoretical foundations with practical applications, particularly in adapting traditional EDA methods to novel computing paradigms like quantum computing and superconducting electronics. His research group has made significant contributions to the development of efficient algorithms for circuit optimization across multiple technology domains, with particular emphasis on area, power, and delay optimization while maintaining functional correctness. Professor De Micheli has supervised numerous doctoral students throughout his career at EPFL, mentoring over 40 PhD candidates whose research spans various aspects of electronic design automation, circuit design, and emerging technologies. His students have gone on to make significant contributions in both academia and industry. As Scientific Director of EcoCloud, Professor De Micheli leads research initiatives focused on energy-efficient computing systems and sustainable cloud infrastructure. His laboratory, the Integrated Systems Laboratory, serves as a hub for interdisciplinary research connecting computer science, electrical engineering, and materials science, with particular focus on next-generation computing technologies.

Scott Hauckمشاهده پروفایل

استاد

• Reconfigurable Computing
• FPGA Architecture
• Quantum Computing Control
• +۵ مورد دیگر

Affiliation & Education Scott Hauck is a Professor at the University of Washington's Department of Electrical & Computer Engineering and an Adjunct Professor in Computer Science & Engineering. He leads the Adaptive Computing Machines and Emulators (ACME) Lab . He earned his BS in EECS from UC Berkeley (1990), and MS/PhD in CSE from the University of Washington (1992/1995). Research Focus Dr. Hauck specializes in FPGA-based reconfigurable computing with applications in: Quantum Computing: FPGA controllers for trapped-ion quantum systems enabling precise laser control and quantum state readout. Medical Imaging: Portable radiation sensors for personalized cancer therapy and PET scanner enhancements. High-Energy Physics: FPGA readout systems for ATLAS pixel detectors at CERN's Large Hadron Collider. AI Acceleration: Real-time machine learning inference for scientific applications via projects like hls4ml. His work bridges hardware innovation with computational physics, emphasizing real-time processing and low-latency systems. Publication Trends Recent research focuses on FPGA-accelerated machine learning for particle physics (e.g., transformer networks for LHC trigger systems) and quantum computing instrumentation. Earlier work established foundations in reconfigurable computing architectures and medical imaging electronics. Awards & Recognition Distinguished Teaching Award, University of Washington (2010) Advising & Funding Leads the ACME Lab with extensive funding from NSF, DARPA, NIH, DOE, and industry partners including Intel, Xilinx, and Microsoft. Mentored over 30 MS/PhD students in VLSI, reconfigurable systems, and scientific computing. Collaborations & Labs Directs the ACME Lab (EE1-307), collaborating with UW Radiology (Prof. Robert Miyaoka), UW Physics (Prof. Shih-Chieh Hsu), and Drexel University (Prof. Josh Agar). Projects include quantum control systems, LHC readout electronics, and medical sensor networks.

• Reconfigurable Computing
• Field-Programmable Gate Arrays (FPGA)
• High-Level Synthesis
• +۳ مورد دیگر

Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.

Jason Congمشاهده پروفایل

استاد

• Electronic Design Automation
• VLSI CAD
• FPGA Synthesis
• +۶ مورد دیگر

Jason Cong is the Volgenau Chair for Engineering Excellence and Distinguished Chancellor's Professor in the Computer Science Department at UCLA's Samueli School of Engineering. He directs the Center for Domain-Specific Computing (CDSC) and the VLSI Architecture, Synthesis, and Technology (VAST) Laboratory, and serves as Associate Vice Provost for Internationalization and Co-Director of UCLA/PKU Student and Scholar Program. Dr. Cong's research spans electronic design automation, customizable computing for machine learning and big-data applications, quantum computing, and highly scalable algorithms. His work has produced over 500 publications with more than 41,000 citations and an H-index of 106. His recent work focuses on quantum computing compilation, domain-specific acceleration for AI workloads, and high-level synthesis optimization techniques that leverage machine learning. His publication trend shows a strong emphasis on quantum computing and machine learning acceleration in recent years, with numerous papers on quantum layout synthesis, LLM acceleration, and high-performance FPGA implementations. His team has developed frameworks like TAPA for task-parallel dataflow programming and RapidStream for automated parallel implementation of FPGA designs. Member of National Academy of Engineering (2017) IEEE Robert N. Noyce Medal recipient (2022) Phil Kaufman Award recipient (2024) ACM Chuck Thacker Breakthrough Award recipient (2024) 18 Best Paper Awards across major conferences Multiple 10-Year Retrospective Most Influential Paper Awards Dr. Cong has graduated 50 PhD students, many of whom are now faculty at major research universities or hold key positions at leading tech companies. He has led over 100 research projects funded by DARPA, NSF, SRC, and industry sponsors. His entrepreneurial activities include founding three successful companies (Aplus Design Technologies, AutoESL, and Falcon Computing Solutions), all acquired by major EDA players. His VAST Laboratory continues to push boundaries in domain-specific computing, with active research in quantum computing, AI acceleration, and high-performance FPGA implementations.

Callie Haoمشاهده پروفایل

استادیار

• Software/Hardware Co-design
• Reconfigurable Computing
• Graph Computing
• +۵ مورد دیگر

Callie Hao is an Assistant Professor in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology since 2021, holding the ON Semiconductor Junior Professorship. Her research bridges hardware efficiency and algorithmic innovation with significant industry and federal recognition. Education: Ph.D. in Electrical Engineering, Waseda University (2017) M.S. and B.S. in Computer Science and Engineering, Shanghai Jiao Tong University Research Focus: Dr. Hao pioneers software/hardware co-design for edge AI, specializing in hardware-efficient machine learning algorithms, FPGA-based reconfigurable computing, graph neural networks, and electronic design automation (EDA). Her work emphasizes neural architecture search, high-level synthesis optimization, and memory-efficient systems for embedded and IoT applications, driven by the philosophy that "1 + 1 > 2" for transformative efficiency gains. Publication Impact: Her 15 most recent publications (2023-2026) reveal a strategic shift toward machine learning-driven EDA tools, with 60% focused on high-level synthesis frameworks and 40% on graph neural network acceleration. Key trends include simulation speed breakthroughs (LightningSim), automated accelerator generation (GNNBuilder), and cryptographic hardware innovations (Cryptonite), predominantly published in top-tier venues like MICRO, ICCAD, and DAC. Awards & Recognition: NSF CAREER Award (2024) and Intel Rising Star Faculty Award (2023) Best Paper Awards at MLCAD 2024 and GLSVLSI 2021 ON Semiconductor Junior Professorship (2025) and Sutterfield Family Early Career Professorship (2022) DAC-SDC competition championships (2018-2020) Mentorship & Funding: Dr. Hao advises 8+ Ph.D. students in the Sharc Lab, with Rishov Sarkar winning the Oscar P. Cleaver Award and Qualcomm Innovation Fellowship. Her research is funded by DARPA (2021) for ultra-light video intelligence systems and supported by industry awards from Amazon and Sony. She actively serves on program committees for DAC, ICCAD, and DATE conferences. Lab Leadership: As director of the Sharc Lab (Software/Hardware Co-design lab), she cultivates interdisciplinary research at the intersection of FPGA design, machine learning, and EDA, requiring expertise in Verilog/HLS, GNNs, and compiler technologies while maintaining strict focus on real-world hardware implementation.

Shantanu Duttمشاهده پروفایل

استاد

• VLSI CAD
• Discrete Optimization
• FPGA Testing and Trusted Design
• +۲ مورد دیگر

Shantanu Dutt is a full Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Chicago , located in Chicago, IL. His office is in 930 SEO at 851 S. Morgan St, and he can be reached at dutt@uic.edu . Education Ph.D. in Computer Science and Engineering, University of Michigan, Ann Arbor (1990) M.Tech. in Computer Engineering, Indian Institute of Technology Kharagpur (1984) B.E. in Electronics and Communication Engineering, Maharaja Sayajirao University of Baroda (1983) Research Interests Professor Dutt’s research agenda centers on VLSI Computer-Aided Design (CAD) , with particular emphasis on physical design and incremental synthesis targeting both ASICs and FPGAs. He explores discrete optimization techniques to solve placement, routing, and partitioning problems. Another major thrust is FPGA built-in self-test (BIST) and trusted design , ensuring provable diagnosability and security against hardware Trojans. He also investigates fault-tolerant computing at both chip and system levels, and develops parallel and distributed computing algorithms for scalable performance. Scientific Awards 1996 Best Paper Award , ACM/IEEE Design Automation Conference, for “A probability-based approach to VLSI circuit partitioning” 1995 Most Influential Paper Award , Fault-Tolerant Computing Symposium, for “Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures” Research Impact and Funding Professor Dutt has published extensively in top-tier journals (IEEE TVLSI, ACM TRETS, IEEE TCAD) and premier conferences (ICCAD, DAC, DATE, FTCS). His work has shaped incremental placement, timing-driven routing, FPGA security, and fault-tolerant multiprocessor architectures. While specific grant numbers are not listed, the breadth and longevity of his publication record indicate sustained funding from NSF, industry, and other agencies. Laboratory and Collaborations Although no formal laboratory name is provided, Professor Dutt’s research is conducted within the ECE department’s VLSI CAD and Fault-Tolerance groups, collaborating with graduate students and colleagues across the US and internationally.

Jason H. Andersonمشاهده پروفایل

استاد

• Computer Engineering
• Electrical Engineering
• Computer-Aided Design (CAD)
• +۳ مورد دیگر

Professor Jason H. Anderson is a faculty member in the Department of Electrical & Computer Engineering (ECE) at the University of Toronto, affiliated with the Faculty of Applied Science & Engineering. He specializes in computer engineering, with a focus on field-programmable gate arrays (FPGAs) and related computer-aided design (CAD) tools. BSc in Computer Engineering from the University of Manitoba MASc and PhD in Electrical & Computer Engineering from the University of Toronto His research spans FPGA architecture, circuit design, and CAD tool development. He has contributed to strategic R&D projects through his academic and industry roles. Scientific awards include multiple Best Paper Awards at IEEE and ACM conferences (2017, 2014, 2011, 2010, 2009), the Xilinx Ross Freeman Award (2000), and teaching accolades such as the Gordon Slemon Award (2012) and several ECE Departmental Teaching Awards (2009-2014). He served as General Chair and Program Chair for leading FPGA conferences. As Chief Scientific Advisor and Co-Founder of LegUp Computing Inc., he bridges academic research with industry innovation. He is a licensed Professional Engineer in Ontario and an active IEEE/ACM member.

• Reconfigurable Computing
• Machine Learning Acceleration
• Hardware Acceleration
• +۵ مورد دیگر

Aman Arora is an Assistant Professor at Arizona State University's Ira A. Fulton Schools of Engineering, specializing in the School of Computing and Augmented Intelligence. His research focuses on reconfigurable computing, hardware acceleration of machine learning, and non-traditional computing paradigms like Processing-In-Memory. With over a decade of semiconductor industry experience, he bridges academic research and industrial applications. PhD in Computer Science from The University of Texas at Austin Research interests emphasize domain-specific acceleration through FPGA optimization , compute-in-memory architectures , and machine learning for CAD/EDA . His work addresses critical challenges in energy efficiency and throughput for AI workloads. Recent publications demonstrate trends toward compute-in-memory systems , FPGA-based deep learning acceleration , and sustainable hardware design . Key contributions include frameworks like SAF, CSR, and GAMA for dynamic hardware optimization. Laboratory Website: ADVENT Lab Teaching includes courses on digital hardware design (CSE 320) and advanced topics in machine learning acceleration (CEN 524/CSE 524). Industry experience informs his practical approach to research and education.

Ameer Abdelhadiمشاهده پروفایل

استادیار

• Hardware Acceleration
• Neurotechnology
• Reconfigurable Computing
• +۴ مورد دیگر

Dr. Ameer Abdelhadi is an Assistant Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on application-specific custom-tailored computer architectures, hardware-efficient deep learning, neurotechnology, and reconfigurable computing. He holds a PhD from the University of British Columbia and has held academic positions at the University of Toronto, Imperial College London, and Simon Fraser University, alongside industry experience in semiconductor design. Education: PhD in Computer Engineering (University of British Columbia, 2016). Research Interests: Hardware acceleration for machine learning and neurotechnology Reconfigurable computing and FPGAs/ASICs Asynchronous circuits and synchronization protocols VLSI physical design and CAD algorithms Publications span high-impact venues such as IEEE Journal of Solid-State Circuits, IEEE Hot Chips, and IEEE Micro. Notable achievements include the 2017 Best Paper Award at ASYNC for work on synchronization FIFOs. Teaching includes COMPENG 4DV4 (VLSI System Design) and ELECENG 4OI6B (Engineering Design). His lab focuses on advancing hardware systems for next-generation applications in AI and biomedical engineering.

Luca Carloniمشاهده پروفایل

استاد

• Computer Science
• Embedded Systems
• Hardware Design
• +۶ مورد دیگر

Luca Carloni is a Professor of Computer Science and Department Chair at Columbia University's Columbia Engineering. He leads the System-Level Design Group, focusing on heterogeneous system-on-chip (SoC) architectures, networks-on-chip (NoC), and embedded systems. Carloni holds a Laurea Summa Cum Laude in Electronics Engineering from the University of Bologna and a PhD in Electrical Engineering and Computer Sciences from UC Berkeley. His work emphasizes specialized hardware design, energy-efficient computing, and FPGA-based prototyping. Research interests include system-level design methodologies for SoCs, embedded accelerators, and quantum computing hardware. He has pioneered frameworks like Embedded Scalable Platforms (ESP) and tools like MosaicSim for rapid SoC prototyping. Carloni has received numerous awards, including the NSF CAREER Award (2006), IEEE Fellow (2017), and multiple best paper awards at DATE and CloudCom conferences. He has served on editorial boards of IEEE Transactions on CAD and ACM Transactions on Embedded Computing , and chaired key conferences like EMSOFT and ESWeek. His research addresses challenges in heterogeneous architectures, power management, and the intersection of machine learning with embedded systems. Current projects explore quantum control systems, brain-computer interfaces, and energy-efficient datacenter computing.

Russell Tessierمشاهده پروفایل

استاد

• Reconfigurable Computing
• FPGA Architecture
• CAD Algorithms for FPGAs
• +۴ مورد دیگر

Russell Tessier is a Professor and Department Head of Electrical and Computer Engineering at the University of Massachusetts Amherst, affiliated with the Manning College of Information and Computer Sciences. His research focuses on reconfigurable computing, FPGA architectures, and hardware security, with notable contributions in CAD algorithms for FPGAs, embedded systems, and multi-tenant FPGA vulnerability analysis. Education: B.S.C.S.E., Rensselaer Polytechnic Institute (1989) M.S. and Ph.D., Massachusetts Institute of Technology (1992 and 1999) Research Interests: Dr. Tessier's work spans FPGA security (e.g., side-channel attacks, power distribution vulnerabilities), reconfigurable cloud computing, and hardware acceleration for applications like SAR imaging and machine learning. His lab, the Reconfigurable Computing Group, develops open-source FPGA cores (e.g., FlexGrip GPGPU, DE4 NetFPGA) and explores cutting-edge security countermeasures. Awards and Honors: Chancellor's Leadership Fellow (2015-2016) NSF Information Technology Research Grant Lilly Teaching Fellow (2002-2003) Multiple College of Engineering Excellence Awards Grants and Projects: Active funding includes NSF SaTC grants on reconfigurable cloud security and NASA support for snowpack measurement systems. His research also addresses FPGA-based solutions for cybersecurity, such as intrusion detection and power-side channel mitigation. Labs and Teams: Leads the UMass Reconfigurable Computing Group, which collaborates on open-source FPGA tools, security frameworks, and embedded system designs. The group maintains platforms like the DE4 NetFPGA and FlexGrip architecture.

Lev Kirischianمشاهده پروفایل

دانشیار

• Task-adaptive reconfigurable computing systems
• Automated architectural synthesis of data-flow parallel computers
• FPGA-based stream processors
• +۳ مورد دیگر

Lev Kirischian is an Associate Professor at the Department of Electrical and Computer Engineering , Toronto Metropolitan University. He established the Embedded and Reconfigurable Systems Laboratory in 1999 for research and graduate studies. His expertise spans reconfigurable computing, parallel systems, and embedded design. BSc/MASc in Aerospace Control Systems, Moscow Institute of Aviation Technology (MAI) PhD in Parallel and Reconfigurable Computing Systems, Moscow Power Engineering Institute (MPEI) Research Interests : Task-adaptive reconfigurable computing systems Automated architectural synthesis of data-flow parallel computers FPGA-based stream processors Article Trends : His recent research focuses on reconfigurable computing architectures, modular system optimization, and FPGA applications in aerospace and industrial systems. Work includes radiation protection for FPGAs, multi-parametric architecture optimization, and frameworks for parallel multi-tasking environments.

Jonathan Roseمشاهده پروفایل

استاد

• FPGA architecture
• Computer-Aided Design (CAD)
• Field-Programmable Systems
• +۳ مورد دیگر

Jonathan Rose is a Professor in the Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto . He received his PhD in Electrical Engineering from the University of Toronto in 1986 and held postdoctoral and research roles at Stanford University's Computer Systems Laboratory (1986-1989). His academic career spans decades, including a 1998-1999 sabbatical at Xilinx and leadership roles at Altera Toronto Technology Centre. He served as Department Chair of Electrical and Computer Engineering (2004-2009) and directed the Engineering Business Minor (2010-2017). Currently, he chairs the Engineering Entrepreneurship Hatchery Advisory Board and engages with organizations like Academics without Borders and Massey College. His research has historically focused on FPGA architecture , Computer-Aided Design (CAD) , Field-Programmable Systems , and Soft Processors . More recently, his work explores the Automation of Medicine , particularly in mental health. His contributions include co-founding the ACM FPGA Symposium and receiving numerous awards for teaching, research, and leadership. Scientific Awards : University of Toronto Engineering Alumni Hall of Distinction Award, 2017 Best Paper Award, ACM TRETS, 2016 University of Toronto President’s Teaching Award, 2016 Foreign Member of the American National Academy of Engineering, 2011 Fellow of the Royal Society of Canada, 2012 The 15 most recent articles reflect his interdisciplinary engagement, spanning Political Science , Public Policy , and Deliberative Democracy , with sub-fields such as Employability Support , Electoral Reform , and Local Governance . His career bridges engineering innovation and societal challenges, particularly in governance and policy.

David Zhigang Panمشاهده پروفایل

استاد

• Electronic Design Automation
• Machine Learning
• Hardware Acceleration
• +۵ مورد دیگر

David Zhigang Pan is a Professor in the Department of Electrical & Computer Engineering at The University of Texas at Austin. He also holds the Silicon Laboratories Endowed Chair. Prior to joining UT Austin, he was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. His academic journey began with a B.S. from Peking University, followed by M.S. and Ph.D. degrees from UCLA. Research Areas: Electronic Design Automation (EDA), Machine Learning Hardware, FPGA Prototyping, Optical Computing, Hardware Security, and CAD for Emerging Technologies Academic Timeline: Assistant Professor (2003-2008), Associate Professor (2008-2013), Full Professor (2013-present) His research focuses on design automation for mixed-signal circuits , GPU-accelerated EDA tools , and hardware-software co-design for AI . Recent work explores FFT-based optical neural networks and deobfuscation techniques for integrated circuits , reflecting his interdisciplinary approach at the intersection of machine learning , computer architecture , and semiconductor manufacturing . Key publication trends reveal expertise in: VLSI design , lithography optimization , and deep learning applications for EDA tools. His work has been recognized with multiple Best Paper Awards at top conferences including DAC , ASP-DAC , and HOST . Awards: IEEE Fellow (2014), SPIE Fellow (2017), ACM SRC Graduate Category Honors for students Patents: 8 U.S. Patents in electronic design and hardware optimization Prof. Pan has mentored 40 PhDs and postdocs who now hold key positions in academia and industry. He leads research initiatives involving GPU acceleration frameworks and optical computing architectures . His lab focuses on vertical integration of architecture, CAD tools, and fabrication technologies for next-generation hardware solutions.

Luciano Lavagnoمشاهده پروفایل

استاد

• Field Programmable Gate Arrays (FPGA)
• High-Level Synthesis
• Indoor Positioning
• +۱۰ مورد دیگر

Luciano Lavagno is a Full Professor at the Department of Electronics and Telecommunications, Polytechnic University of Turin, with over two decades of academic and research contributions. His work bridges hardware acceleration, low-power electronics, and intelligent system design. Research Focus: Hardware-accelerated machine learning, high-level synthesis (HLS) for FPGA/ASIC, heterogeneous CPU/GPU/FPGA platforms Key Projects: SPACE (predictable acceleration), REBECCA (secure AI acceleration), HPC-National Center (quantum computing), and oral history preservation via "Ti racconto una storia" initiative His recent publications analyze CNN inference optimization, subgraph isomorphism, and superword-level parallelism exploitation. Lavagno supervises multiple PhD students working on FPGA acceleration, neural network hardware, and embedded systems. As Principal Investigator for national and EU-funded projects (PRIN, JTI-ECSEL, PNRR), he drives advancements in sustainable computing infrastructure. His patented technologies include MIx&Latch timing methodology, capacitive sensing innovations, and 5G acceleration frameworks.