جست‌وجوی استاد و پژوهشگر

• Electronics Engineering
• Signal Processing
• Biomedical Engineering
• +۳ مورد دیگر

Bruno Tiago da Silva Gomes is a Researcher in the Department of Electronics and Informatics at Vrije Universiteit Brussel (VUB), Belgium. His work focuses on FPGA-based hardware acceleration, biomedical signal processing, and embedded systems. He leads several high-impact projects, including ENACT (environmental health interventions) and Tech4Health (future health technologies). His research spans FPGA design, machine learning acceleration, and real-time signal processing. Education: PhD in Electronics and Informatics (2019, VUB), supervised by Professors Touhafi and Braeken. His thesis addressed streaming application acceleration on FPGAs. Research interests include Field-Programmable Gate Arrays (FPGA), biomedical sensors (e.g., photoplethysmography), beamforming, and high-level synthesis. He has co-authored over 60 publications and holds an h-index of 439. Key projects include OZR4103 (power-efficient AI for biomedical applications) and NSIS3 (decarbonisation technologies). His work integrates hardware-software co-design for edge computing and secure TinyML systems. Advising includes a Master’s thesis on PPG signal analysis. He contributes to datasets like the AMIVU Acoustic Map Imaging Dataset.

John Wickersonمشاهده پروفایل

دانشیار

• Computer Hardware
• Electrical and Electronic Engineering
• Computer Software
• +۷ مورد دیگر

Dr. John Wickerson is an Associate Professor in the Circuits and Systems group at the Department of Electrical and Electronic Engineering, Imperial College London. His research focuses on improving the reliability of high-performance computing through formal methods, with contributions to high-level synthesis, memory models, and concurrency verification. He holds leadership roles including Course Director for the Electrical and Information Engineering degree and Deputy Tutor for PhD students. Research Interests: Formal Verification of Hardware/Software Systems High-Level Synthesis (HLS) and FPGA Compilation Weak Memory Models and Concurrency Semantics Fuzz Testing for Hardware Tools Compiler Optimization and Correctness Digit Elision and Arbitrary-Precision Arithmetic Notable Achievements: Best Paper Award at EuroSys 2024 (database isolation validation) Pioneered formal methods for HLS tools (e.g., QuteFuzz, C4) Co-developed the C4 C compiler concurrency checker Published over 60 peer-reviewed papers across top venues (ASPLOS, PLDI, FPGA) Lab/Team: Part of the Circuits and Systems group at Imperial College, collaborating with industry partners like Kaihong Yann and ARM.

Papadimitriou Kyprianosمشاهده پروفایل

پژوهشگر

• Reconfigurable Systems
• Hardware Design
• Digital Systems
• +۷ مورد دیگر

Kyprianos Papadimitriou is a Researcher at the Microprocessor and Hardware Laboratory within the School of Electrical and Computer Engineering at the Technical University of Crete . He holds a PhD in Electronic and Computer Engineering (2012) and has been involved in teaching laboratory courses such as Logic Design , Computer Architecture , and VLSI/ASIC Circuit Design . Research Areas : His work spans Reconfigurable Systems , Hardware Design , Computer Architecture , RFID Systems , and Real-Time Systems . He has developed innovative approaches in FPGA-based dynamic reconfiguration, MPSoC security, and 3D stereo vision for surveillance. Key Trends : Runtime reconfiguration for FPGAs Security frameworks for NoC-based MPSoCs Low-cost embedded vision systems Optimization of reconfiguration overhead Hardware task scheduling methodologies Genetic algorithm implementations on FPGAs Scientific Contributions : 1 USA patent (2005) Co-author of VLSI-SoC 2013 paper nominated for 1st Prize Active member of scientific committees (FPL, ReConFig) Peer reviewer for IEEE, Elsevier, and Springer journals Session chair at IEEE CNS and HPCC conferences Grants & Projects : Participated in competitive European and national programs, serving as scientific manager, coordinator, and technical coordinator. Developed spin-off company (2003-2005) to commercialize master's thesis research. Laboratory & Teaching : Affiliated with the Microprocessor and Hardware Laboratory , focusing on practical training in digital systems, processor-based systems, and VLSI design.

Stephen Brownمشاهده پروفایل

استاد

• Field-Programmable Gate Arrays (FPGAs)
• Computer Architecture
• CAD Algorithms
• +۴ مورد دیگر

Stephen Brown is a Professor at the University of Toronto within the Department of Electrical and Computer Engineering under the Faculty of Applied Science and Engineering. He earned his B.A.Sc and M.A.Sc in Electrical Engineering from the University of Toronto and New Brunswick, respectively, and a Ph.D. in Electrical Engineering from the University of Toronto (1992). His career spans over two decades in academia and industry collaboration. Education : B.A.Sc, University of New Brunswick M.A.Sc, University of Toronto Ph.D, University of Toronto Professor Brown’s research focuses on field-programmable gate arrays (FPGAs) , CAD algorithms , and computer architecture , with applications in machine learning and high-level synthesis . He is a principal investigator in the LegUp project , an open-source high-level synthesis framework that bridges software and hardware design. His work also extends to optimizing FPGA interconnect delays, physical synthesis, and logic block architectures. Key trends in his publications include advancements in high-level synthesis tools, FPGA architecture evaluation, and timing-driven design methodologies. His contributions often intersect with design automation , resource sharing , and embedded systems . Scientific Awards : NSERC 1992 Doctoral Prize Hart Professorship for Innovation in Teaching (2017) Multiple teaching excellence awards Best Paper Award at ICCAD 1990 Best Paper Award nomination at Canadian Conference on VLSI (1989) As Director of the FPGA University Program at Intel Corporation, he leads industry-academia initiatives. His teaching portfolio includes courses like ECE253 (Digital Logic) and ECE1733F (Switching Theory).

• Hyperdimensional Computing
• Neuromorphic Hardware
• In-Memory Computing
• +۳ مورد دیگر

Paul R. Genssler is a Dr.-Ing. researcher at the Chair of AI Processor Design (AI-Pro) within the Technical University of Munich (TUM), actively advancing hardware solutions for artificial intelligence under Prof. Hussam Amrouch. His work bridges computer engineering and emerging technologies, focusing on overcoming fundamental limitations in conventional computing architectures through brain-inspired paradigms. His research spans critical domains in next-generation computing: Hyperdimensional Computing for robust pattern recognition and bioinformatics applications Neuromorphic and In-Memory Computing architectures for energy efficiency Reliability engineering for emerging memory technologies (FeFET, etc.) Quantum computing support systems including cryogenic embedded electronics Machine learning-driven transistor aging prediction and mitigation Analysis of his 15 most recent publications (2023-2024) reveals a dominant trend toward hyperdimensional computing as a unifying framework for addressing reliability challenges in emerging technologies. His work consistently integrates in-memory computing techniques to bypass von Neumann bottlenecks while targeting real-world applications like genome matching and unsupervised learning. A significant portion focuses on error-resilient implementations for unreliable nanoscale devices, demonstrating exceptional cross-stack expertise from transistor physics to algorithm design. As a core member of TUM's AI Processor Design group affiliated with the Munich Institute of Robotics and Machine Intelligence (MIRMI), Genssler collaborates extensively on projects spanning cryogenic quantum control systems, FPGA-based AI resilience, and monolithic 3D integration. The team operates at the intersection of semiconductor physics, computer architecture, and machine learning, with strong industry connections evident through publications at DATE, ASP-DAC, and ICCAD.

• Electrical and Computer Engineering laboratory curriculum
• Digital systems design
• CAD for VLSI
• +۴ مورد دیگر

Mark C. Johnson is a Senior Lecturer at the Elmore Family School of Electrical and Computer Engineering at Purdue University, West Lafayette. He serves as Director of Instructional Laboratories and Associate Director for Design - Semiconductor Degree Program , overseeing laboratory infrastructure, CAD software administration, and curriculum development for courses like ECE337, ECE437, and ECE364. Education: Ph.D. in Electrical Engineering (1998), Purdue University M.S. in Electrical Engineering (1991), Wichita State University B.S. in Electrical Engineering (1983), Purdue University - Calumet His research focuses on electrical and computer engineering laboratory curriculum innovation , digital systems design , and CAD for VLSI . Over 15 recent publications highlight his work in SoC prototyping , low-power circuit design , and educational technology , spanning projects like FPGA filter optimization, dual-core processor experiments, and active learning strategies. Leadership Roles: Proceedings Chair (2003), MSE Program Chair (2005), MSE General Chair (2007), MSE Steering Committee Member, MSE & European Workshop on Microelectronics Education Chair, ECE Instructional Innovation Group (2004-2012) Secretary/Webmaster, ASEE Illinois/Indiana Section (2002-2011) He directs the ECE437 Computer Architecture Prototyping Lab and System on Chip Extension Technologies (SoCET) team , and co-advises the STARS semiconductor readiness program. Outside academia, he is an organist at Faith Presbyterian Church and composes keyboard music.

• Reconfigurable Computing
• FPGA Architectures
• Hardware Acceleration
• +۱ مورد دیگر

Prof. Dr. Andreas Koch leads research on reconfigurable computing at TU Darmstadt, focusing on FPGA-based acceleration, heterogeneous architectures, and hardware/software co-design for database systems and embedded applications.

• Power Electronics
• Electrical Engineering
• Energy Conversion
• +۷ مورد دیگر

Kamal Al Haddad is a Lecturer in the Department of Electrical Engineering at École de technologie supérieure (ÉTS). He holds a Doctorate from INTP, Toulouse, and advanced degrees from UQTR. His research focuses on power electronics, renewable energy integration, and smart grid technologies. He leads the GREPCI research group, specializing in Power Electronics and Industrial Control. Education: B.Eng., M.Sc.A. (UQTR), Doctorate (INTP, Toulouse). Research interests span energy conversion, industrial electronics, power quality, and electromagnetic interference. He emphasizes sustainable energy solutions, electric traction systems, and high-efficiency power sources. His work includes developing advanced power electronic converters and grid stability solutions. Recent articles highlight advancements in modular converters for STATCOM, AI-driven fault detection in hydrogenerators, and renewable energy policy frameworks. He has received notable awards, including the 2014 IEEE Eugene Mittelmann Prize and Fellowships from IEEE and other institutions. Supervised over 60 students, including doctoral theses on topics like hydrogenerator diagnostics, EV charging systems, and renewable energy integration. His research also involves real-time simulation of power systems and FPGA-based implementations. Labs/Teams: GREPCI – Power Electronics and Industrial Control Research Group, leading projects on smart grids and energy efficiency.

Trevor E. Carlsonمشاهده پروفایل

استادیار

• Computer Architecture
• Hardware/Software Co-Design
• Performance Modeling
• +۴ مورد دیگر

Trevor E. Carlson is an Assistant Professor at the School of Computing, National University of Singapore (NUS), focusing on high-efficiency microarchitectures, hardware/software co-design, and secure chip design for IoT and server applications. He earned his Ph.D. in Computer Science from Ghent University (2014) and B.Sc./M.Sc. in Electrical & Computer Engineering from Carnegie Mellon University (2002/2003). Research Interests include energy-efficient processors, secure computing platforms, neuromorphic accelerators, and fast simulation methodologies. He co-developed the Sniper Multi-Core Simulator used globally for performance/power evaluation. Scientific Awards : Best Paper Award, International Conference on Embedded Computer Systems (2016) Best Paper Award, International Symposium on Performance Analysis of Systems and Software (2013) Heidelberg Laureate Forum participation (2015) HiPEAC Technology Transfer Award for Sniper Simulator (2013) Current Research involves secure Systems-on-Chip (SOCure project), hardware security for IoT, and simulation methodologies. He leads a lab with researchers working on topics like Capstone for trustless secure memory access and LABS for laser fault injection benchmarks.

Andrea Fumagalliمشاهده پروفایل

استاد

• Optical Networking
• Photonic Slot Routing
• Wavelength Routing and Protection
• +۷ مورد دیگر

Andrea Fumagalli is a Professor in the Department of Electrical Engineering at the Erik Jonsson School of Engineering and Computer Science , The University of Texas at Dallas. He earned his Ph.D. (1992) and Laurea (1987) in Electrical Engineering from Politecnico di Torino, Italy. Research Interests: All-Optical Network Architectures, Photonic Slot Routing, Wavelength Routing and Protection, Sensor Networks, Cooperative Wireless Networks, Network Optimization, Next Generation Internet (NGI), and Multi-hop Optical Networks. Education: Ph.D., Electrical Engineering, Politecnico di Torino (1992) Laurea, Electrical Engineering, Politecnico di Torino (1987) Key Research Trends: His recent publications focus on 5G networking, optical network automation, elastic optical networks, network reliability, and cross-layer optimization. He explores FPGA acceleration in 5G Low-PHY functions, live migration of containerized network components, and spectral fragmentation mitigation in EONs. Scientific Awards: Best Teaching Award, Electrical Engineering, UTD (2002) Best Thesis Award for Ph.D. Advisee Isabella Cerutti (2002) IEEE ComSoc Distinguished Lecturer Tour (2000) Best Paper Award (1999): 'An Optimal Design Algorithm for Photonic Slot Routing Networks Migrating to Optical Packet Switching' Advising and Grants: He advised Ph.D. student Isabella Cerutti. In 2001, he secured a $300,000 grant from FUNDACAO CPqD for optical network reliability research. He leads the Optical Networking Advanced Research (OpNeAR) Lab at UTD, collaborating on international projects like the Italian government-funded grid computing initiative (2002) and the OMEGA Test-bed for differentiated reliability. Laboratories and Teams: He directs the OpNeAR Lab , which develops tools for optical network emulation and reliability testing. His projects involve partnerships with institutions in Brazil (Unicamp), Sweden (KTH), Italy (Politecnico di Torino, Scuola Superiore Sant'Anna), and CNR/CNIT.

Kenneth Zickمشاهده پروفایل

استاد پژوهشی

• Unconventional computing
• Bio-inspired compute systems
• Ising machines
• +۷ مورد دیگر

Dr. Kenneth Zick is a Research Professor at the University of Southern California's Information Sciences Institute (USC ISI), where he serves as Research Director of Transformational Computing. His work focuses on game-changing computer architectures, hardware, and systems for solving critical government problems, with expertise in unconventional computing, quantum computing, and bio-inspired systems. Ph.D. in Computer Science & Engineering, University of Michigan-Ann Arbor M.S. in Electrical Engineering, University of Texas at Dallas Bachelor's in Electrical Engineering, University of Michigan-Ann Arbor Dr. Zick's research interests span unconventional computing , bio-inspired systems , Ising machines , quantum annealing , FPGA-based solutions , and neuromorphic computing . His group develops hardware-centric algorithm discovery and Cosm, a heuristic algorithm for sparse Ising optimization. Current projects include superconducting digital architectures, analog-digital hybrid computing, and human-AI co-design for breakthrough hardware. His team leverages advanced facilities such as USC ISI's MOSIS 2.0 and the California DREAMS hub in the DoD Microelectronics Commons, with expertise in high-speed I/O, FPGA prototyping, and radiation-hardened systems. He has received a NASA Fellowship for his Ph.D. work and mentored students like Aditi, who won the USC ECE Outstanding Academic Achievement Award.

• Computer Architecture
• Hardware Acceleration
• Approximate Computing
• +۳ مورد دیگر

Akash Kumar is a Professor at Ruhr University Bochum, Germany, with affiliations to multiple institutions including TU Dresden and National University of Singapore. His research focuses on computer architecture, hardware acceleration, and approximate computing, with a strong emphasis on FPGA-based systems and neural network optimization. He has contributed extensively to embedded systems, mixed-criticality systems, and security in emerging technologies like reconfigurable nanodevices. His work spans cross-layer approximation methodologies, graph neural networks, and energy-efficient processing for edge AI. Collaborations with industry and academia highlight his leadership in VLSI design and secure hardware implementations. Notable contributions include frameworks for bounding time in mixed-criticality systems and resilient logic locking techniques. Research interests include hardware-software co-design, real-time systems, and efficient neural network architectures. His publications in top-tier conferences (DAC, DATE, FCCM) and journals (IEEE Trans. CAD, ACM TECS) underscore his impact in the field.

Kimia Zamiri Azarمشاهده پروفایل

استادیار

• Hardware Security
• Verification Formal Methods
• Advanced VLSI Testing
• +۳ مورد دیگر

Kimia Zamiri Azar serves as an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida, focusing on hardware security and verification methodologies. Her research bridges theoretical formal methods with practical security implementations in semiconductor design and testing. Her educational background includes: Ph.D. in Electrical and Computer Engineering, George Mason University (2021) Postdoctoral Research, University of Florida Dr. Azar's research spans hardware security with emphasis on system-level verification, VLSI design-for-trust, and advanced IC testing. She pioneers techniques in logic locking, secure heterogeneous integration, and IC supply chain security, developing frameworks for authenticated encryption in Systems-in-Package and runtime security monitoring. Her work integrates formal verification with innovative testing methodologies to address hardware trust challenges across the semiconductor lifecycle. Analysis of her recent publications reveals two dominant trends: (1) Application of large language models (LLMs) to hardware design tasks including high-level synthesis code generation and RTL optimization, and (2) Advancement of secure heterogeneous integration techniques for System-in-Package architectures with focus on counterfeit prevention and split-test security protocols. These directions address critical gaps in hardware trustworthiness amid increasingly complex semiconductor supply chains. Her scientific contributions have earned significant recognition: Best Paper Award at ICCAD 2019 Best Paper Award at ISVLSI 2020 Best Paper Award at ICCAD 2020 Best Paper Award at IEEE DCAS 2020 Best Paper Award at HOST 2022 Best Paper Award at DATE 2023 Dr. Azar secures substantial research funding from premier agencies including NSF, SRC, DARPA, AFRL, DoD (NG), and Microsemi. Her grants support projects spanning hardware security validation frameworks, secure heterogeneous integration, and AI-augmented verification methodologies. She actively mentors students in her research group, guiding publications in top venues like IEEE D&T, IEEE TC, and DAC while fostering industry-academic collaborations. Her work directly impacts semiconductor security standards through patented innovations and open-source verification tools. As an active IEEE and ACM member, she contributes to community advancement through conference organization (HOST, DATE), journal editorial roles, and workshop leadership on hardware security standards. Her research group collaborates with semiconductor industry leaders to translate theoretical security frameworks into practical design-for-trust methodologies for next-generation integrated circuits.

Yiorgos Makrisمشاهده پروفایل

استاد

• Hardware Security
• Trusted Systems
• Machine Learning in Semiconductor Manufacturing
• +۹ مورد دیگر

Yiorgos Makris is a Professor in the Department of Electrical and Computer Engineering at the Erik Jonsson School of Engineering & Computer Science, The University of Texas at Dallas, since July 2011. Previously, he was a faculty member at Yale University for over a decade. He holds a Ph.D. in Computer Engineering from the University of California, San Diego, and a Diploma in Computer Engineering from the University of Patras, Greece. Education: Ph.D. in Computer Engineering, University of California, San Diego (2001) M.S. in Computer Engineering, University of California, San Diego (1997) Diploma in Computer Engineering and Informatics, University of Patras, Greece (1995) Research Interests: Hardware Security and Trustworthiness Statistical Side-Channel Fingerprinting Machine Learning in Semiconductor Manufacturing Trusted and Reliable Integrated Circuits Hardware Trojans in Wireless Cryptographic ICs On-Die Learning and Emergent Technologies His work focuses on enhancing hardware security through statistical methods, machine learning, and formal verification, with applications in analog/RF ICs, post-production calibration, and secure IC design. Key Contributions: Co-Founder and Site-PI of NSF CHEST I/UCRC (Hardware and Embedded System Security and Trust) Leader of the Safety, Security, and Healthcare Thrust at TxACE (Texas Analog Center of Excellence) Director of the Trusted and RELiable Architectures (TRELA) Lab Grants and Funding: NSF, NIH, SRC, ARO, AFRL, AFWERX, DARPA, DOE, and industry partnerships with Boeing, Northrop Grumman, IBM, Intel, Qualcomm, etc. Recent grants include projects on DNA storage security, analog neural networks, and malicious hardware detection. Awards and Recognition: IEEE Fellow (2025) Best Paper Awards at DATE'13, VTS'15, DCAS'22 Best Hardware Demonstration Awards at HOST'16 and HOST'18 Erik Jonsson School Faculty Research Award (2020) Labs and Teams: TRELA Lab (Focus: Secure Hardware Design, Trusted Architectures) CHEST I/UCRC (Industry-University Collaboration)

Jason D. Bakosمشاهده پروفایل

استاد

• Computer Architecture
• Reconfigurable Computing
• High-Performance Computing
• +۴ مورد دیگر

Dr. Jason D. Bakos is a Professor in the Department of Computer Science and Engineering at the University of South Carolina's Molinaroli College of Engineering and Computing. His research focuses on high-performance domain-specific architectures, including reconfigurable computing, embedded systems, and machine learning acceleration. He has held academic positions since 2005, progressing from Assistant to Associate Professor before becoming a full Professor in 2017. Education : Ph.D., Computer Science, University of Pittsburgh (2005) B.S., Computer Science, Youngstown State University (1999) Research Interests : Dr. Bakos specializes in computer architecture at multiple levels (circuit, micro-architectural, and system) with a focus on VLSI design, reconfigurable computing, high-performance computing, and applications in embedded systems. His recent work includes FPGA acceleration of machine learning algorithms, structural health monitoring systems, and real-time signal processing. Awards : 2018 Teaching Award in Computer Science and Engineering 2009 NSF CAREER Award Multiple design competition awards for innovative chip and circuit designs Grants & Funding : He leads and co-leads projects funded by NSF, Savannah River National Laboratory, and industry partners like Texas Instruments. Recent grants focus on edge computing for real-time machine learning, FPGA-based accelerators, and corrosion analysis of nuclear materials. Labs & Teams : His research group collaborates on projects involving embedded systems, FPGA design, and interdisciplinary applications in structural engineering and bioinformatics. He advises a dynamic team of graduate students and post-doctoral researchers.