جست‌وجوی استاد و پژوهشگر

Oliver Diesselمشاهده پروفایل

دانشیار

• Reconfigurable Hardware
• Computer Architecture
• Digital Systems
• +۶ مورد دیگر

Associate Professor Oliver Diessel is a faculty member at the University of New South Wales (UNSW) within the School of Computer Science and Engineering. He has been actively teaching and conducting research at UNSW since at least 2000, with teaching experience spanning various computer architecture and digital systems courses. Dr. Diessel completed his education at the University of Newcastle, Australia, earning a B.E. (Computer, Hons) and B.Math. in 1991, followed by a PhD in 1998. His academic career has focused on reconfigurable computing systems and computer architecture. His primary research interests center around the design, test, and implementation of digital systems in reconfigurable logic devices called Field-Programmable Gate Arrays (FPGAs). Specifically, he focuses on dynamically reconfigurable digital systems where circuits can be modified while the system is operational. His work aims to develop architectures, design methods, and tools that enhance the benefits and reduce the costs of reconfigurable systems. Current research projects include fault-tolerant FPGA-based systems for space applications and fine-grained accelerators for heterogeneous devices. Dr. Diessel has published extensively with 2 books, 1 book chapter, 16 journal articles, 67 conference papers, 1 edited conference proceedings, and 7 conference presentations to his credit. His publications reflect a strong emphasis on reconfigurable technology, computer architecture, and electronic design automation. As a supervisor, Dr. Diessel currently mentors two MPhil students: Tong Wu working on Runtime reconfiguration and Junning Fan working on Fault-tolerance of FPGA-based applications. He has previously supervised six students to completion. His supervision interests include reconfigurable technology and systems, electronic design automation, and computer architecture. Dr. Diessel is an active member of the professional community, serving on the Editorial Board of ACM Transactions on Reconfigurable Technology and Systems and as an IEEE Member. He has taught numerous courses including Configurable Systems (COMP4601), Computer Architecture (COMP3211, COMP4211), Digital Systems (COMP3222), and FPGA Implementation of Digital Systems using Verilog.

Justine Sherryمشاهده پروفایل

استادیار

• Computer Networking
• Networked Systems
• Middleboxes
• +۵ مورد دیگر

Justine Sherry is the A. Nico Habermann Associate Professor of Computer Science at Carnegie Mellon University, affiliated with the College of Engineering. She holds a PhD (2016) and MS (2012) from UC Berkeley and a BS/BA (2010) from the University of Washington. Her research focuses on networked systems, including middleboxes, cloud computing, congestion control, and hardware acceleration (e.g., SmartNICs/FPGAs). Notable projects include Pigasus (open-source 100Gbps IDS), APLOMB (cloud-based middlebox scaling), and BlindBox (encrypted traffic scanning). Her academic roles include serving on the SIGCOMM CARES Committee, DARPA ISAT Study Group, and ACM CoNEXT Steering Committee. Awards include the Alfred P. Sloan Fellowship, VMware Systems Award, and IETF Applied Networking Prize. She advises over 15 students and collaborates with industry partners like Intel and VMware. Research highlights include radical shifts in datacenter architectures (SmartNIC compute control), fairness in congestion algorithms (BBR analysis), and database-proxy innovations (Tigger with eBPF). Her teaching emphasizes systems as science labs, integrating experimental design and hypothesis testing into projects. Education: PhD UC Berkeley (2016), MS UC Berkeley (2012), BS/BA University of Washington (2010) Labs/Teams: CyLab, SNAP Research Group, CMU Portugal Collaboration Grants: NSF, Intel, Google Faculty Awards

• Electrical and Electronic Engineering
• Computer Hardware
• Computer Software
• +۷ مورد دیگر

Professor Peter Y. K. Cheung is a Professor of Digital Systems at Imperial College London, holding dual affiliations within the Department of Electrical and Electronic Engineering and the Dyson School of Design Engineering. His work focuses on reconfigurable systems, FPGA architectures, and high-level synthesis tools. He co-founded one of the UK's leading FPGA research groups with Professor Wayne Luk, addressing challenges in variability mitigation, reliability, and application-specific FPGA deployments. His research spans Field-Programmable Gate Arrays (FPGAs) Reconfigurable computing Neural network acceleration Cryptographic protocols Embedded systems He has pioneered techniques such as logic shrinkage for FPGA-based neural networks and developed frameworks like LUTNet for efficient inference. His contributions also include fault-tolerant FPGA designs and methodologies for distributed computation protocols. Key collaborations include work with the Department of Computing on FPGA-based AI acceleration and cybersecurity applications. His recent work explores edge computing, secure decentralized systems, and pandemic modeling using adaptive control strategies. Notable projects include the DSCS protocol for secure distributed computation, acceleration of gravitational wave detection algorithms, and energy-efficient CNN implementations. His research bridges hardware-software co-design with real-world applications in healthcare, finance, and aerospace.

Callie Haoمشاهده پروفایل

استادیار

• Software/Hardware Co-design
• Reconfigurable Computing
• Graph Computing
• +۵ مورد دیگر

Callie Hao is an Assistant Professor in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology since 2021, holding the ON Semiconductor Junior Professorship. Her research bridges hardware efficiency and algorithmic innovation with significant industry and federal recognition. Education: Ph.D. in Electrical Engineering, Waseda University (2017) M.S. and B.S. in Computer Science and Engineering, Shanghai Jiao Tong University Research Focus: Dr. Hao pioneers software/hardware co-design for edge AI, specializing in hardware-efficient machine learning algorithms, FPGA-based reconfigurable computing, graph neural networks, and electronic design automation (EDA). Her work emphasizes neural architecture search, high-level synthesis optimization, and memory-efficient systems for embedded and IoT applications, driven by the philosophy that "1 + 1 > 2" for transformative efficiency gains. Publication Impact: Her 15 most recent publications (2023-2026) reveal a strategic shift toward machine learning-driven EDA tools, with 60% focused on high-level synthesis frameworks and 40% on graph neural network acceleration. Key trends include simulation speed breakthroughs (LightningSim), automated accelerator generation (GNNBuilder), and cryptographic hardware innovations (Cryptonite), predominantly published in top-tier venues like MICRO, ICCAD, and DAC. Awards & Recognition: NSF CAREER Award (2024) and Intel Rising Star Faculty Award (2023) Best Paper Awards at MLCAD 2024 and GLSVLSI 2021 ON Semiconductor Junior Professorship (2025) and Sutterfield Family Early Career Professorship (2022) DAC-SDC competition championships (2018-2020) Mentorship & Funding: Dr. Hao advises 8+ Ph.D. students in the Sharc Lab, with Rishov Sarkar winning the Oscar P. Cleaver Award and Qualcomm Innovation Fellowship. Her research is funded by DARPA (2021) for ultra-light video intelligence systems and supported by industry awards from Amazon and Sony. She actively serves on program committees for DAC, ICCAD, and DATE conferences. Lab Leadership: As director of the Sharc Lab (Software/Hardware Co-design lab), she cultivates interdisciplinary research at the intersection of FPGA design, machine learning, and EDA, requiring expertise in Verilog/HLS, GNNs, and compiler technologies while maintaining strict focus on real-world hardware implementation.

Jonathan Shihao Jiمشاهده پروفایل

دانشیار

• Deep Learning
• Computer Vision
• Natural Language Processing
• +۵ مورد دیگر

Jonathan Shihao Ji is an Associate Professor in the School of Computing at the University of Connecticut (UConn), leading the Intelligent Systems Lab. He holds a Ph.D. in Electrical and Computer Engineering from Duke University and previously served as an Associate Professor at Georgia State University and Director of the DoD Center of Excellence (CiARE). His research focuses on deep learning applications in computer vision, NLP, robotics, and high-performance computing, with over 50 publications in top venues like CVPR, NeurIPS, and IEEE journals. He has secured grants from NSF, NIH, DoD, and industry partners including VMware and Nvidia. His work emphasizes efficient algorithms for large-scale data processing, parameter-efficient model fine-tuning (e.g., VB-LoRA), and 3D perception benchmarks for UAVs (UAV3D). Notable contributions include sparse network optimization (Dep-L0), energy-based models (M-EBM), and robust defenses against adversarial attacks (Defense-VAE). He is a Senior Member of IEEE and has developed open-source tools like Parallel Word2Vec and WordRank. Recent projects include accelerating Llama2 models on FPGAs (LlamaF) and improving text-to-image synthesis via contrastive learning. His research spans theoretical advancements and practical applications, with industry collaborations in healthcare, robotics, and embedded systems.

Jing Liمشاهده پروفایل

دانشیار

• Computer Architecture
• Compiler Design
• Distributed Systems
• +۷ مورد دیگر

Dr. Jing Li is an Associate Professor and Eduardo D. Glandt Faculty Fellow at the University of Pennsylvania , holding dual appointments in the Electrical and Systems Engineering and Computer and Information Science departments. As co-director of the CyberSavvy nationwide security research center and director of the Penn Computational Intelligence Lab (PennCIL) , she pioneers innovations in non-von Neumann computing paradigms. Her research spans post-CMOS technologies, in-memory computing, and hardware-software co-design for security and AI applications. PhD in Computer Engineering, Purdue University (2009) BSc in Electrical Engineering, Shanghai Jiaotong University (2004) Research Focus: Dr. Li's work addresses fundamental challenges in computer systems across the stack. Key areas include: In-Memory Computing: Liquid Silicon architecture combining RRAM with silicon CMOS through monolithic 3D integration Security Engineering: Transforming computer security from "Art" to formal "Engineering" discipline within CyberSavvy Virtualization: Cloud FPGA abstraction layers decoupling compilation from runtime resource management Graph Analytics: Degree-aware optimization techniques for massive-scale graph processing Deep Learning Systems: Roofline model extensions for FPGA-based CNN acceleration Scientific Impact: Awarded DARPA Young Faculty Award , NSF CAREER Award , and IBM CEO Milestone Award , her team has achieved world records in energy-efficient computing (ENIAD supercomputer). With 46 U.S. patents and over 80 publications, she leads ecosystem development for emerging computing architectures through initiatives like the open-source MEG simulation platform . Community Leadership: Dr. Li serves on program committees for flagship conferences ( ISCA , FPGA Symposium ), chairs the International Memory Workshop , and contributes to the MLsys conference's inaugural committee. She actively mentors through multiple PhD openings and industry collaborations.

Jason Congمشاهده پروفایل

استاد

• Electronic Design Automation
• VLSI CAD
• FPGA Synthesis
• +۶ مورد دیگر

Jason Cong is the Volgenau Chair for Engineering Excellence and Distinguished Chancellor's Professor in the Computer Science Department at UCLA's Samueli School of Engineering. He directs the Center for Domain-Specific Computing (CDSC) and the VLSI Architecture, Synthesis, and Technology (VAST) Laboratory, and serves as Associate Vice Provost for Internationalization and Co-Director of UCLA/PKU Student and Scholar Program. Dr. Cong's research spans electronic design automation, customizable computing for machine learning and big-data applications, quantum computing, and highly scalable algorithms. His work has produced over 500 publications with more than 41,000 citations and an H-index of 106. His recent work focuses on quantum computing compilation, domain-specific acceleration for AI workloads, and high-level synthesis optimization techniques that leverage machine learning. His publication trend shows a strong emphasis on quantum computing and machine learning acceleration in recent years, with numerous papers on quantum layout synthesis, LLM acceleration, and high-performance FPGA implementations. His team has developed frameworks like TAPA for task-parallel dataflow programming and RapidStream for automated parallel implementation of FPGA designs. Member of National Academy of Engineering (2017) IEEE Robert N. Noyce Medal recipient (2022) Phil Kaufman Award recipient (2024) ACM Chuck Thacker Breakthrough Award recipient (2024) 18 Best Paper Awards across major conferences Multiple 10-Year Retrospective Most Influential Paper Awards Dr. Cong has graduated 50 PhD students, many of whom are now faculty at major research universities or hold key positions at leading tech companies. He has led over 100 research projects funded by DARPA, NSF, SRC, and industry sponsors. His entrepreneurial activities include founding three successful companies (Aplus Design Technologies, AutoESL, and Falcon Computing Solutions), all acquired by major EDA players. His VAST Laboratory continues to push boundaries in domain-specific computing, with active research in quantum computing, AI acceleration, and high-performance FPGA implementations.

• High-Performance Computing
• Reconfigurable Computing
• FPGA Acceleration
• +۷ مورد دیگر

Carlos Alvarez Martinez is a faculty member at the Universitat Politècnica de Catalunya (UPC), affiliated with the Department of Computer Architecture at the Barcelona School of Informatics (FIB). He is a key member of the Programming Models (PM) research group and collaborates closely with the Barcelona Supercomputing Center (BSC). His research focuses on high-performance computing, FPGA acceleration, task-based programming models like OmpSs, and hardware-software co-design for heterogeneous systems. His research interests center on advancing parallel computing through innovative programming models and hardware acceleration. He investigates efficient task scheduling, resource management in multicore and FPGA-based systems, and runtime support for dataflow models. His work enables high-performance execution of complex applications in domains such as scientific computing and cyber-physical systems. He actively contributes to European initiatives like TEXTAROSSA and AXIOM, aiming to develop next-generation exascale supercomputing technologies. The trend in his recent publications shows a strong focus on leveraging FPGAs for HPC, optimizing SpMV operations, improving task scheduling with hardware support, and developing frameworks for multi-FPGA clusters. His work consistently bridges theoretical models with practical implementations, emphasizing performance, scalability, and energy efficiency in heterogeneous computing environments. Scientific Awards: Premi UPC al Compromís Social 2019 Premi Disseny per al Reciclatge 2013 Alvarez Martinez has advised or collaborated with several doctoral students, including Jaume Bosch, Xubin Tan, and Fahimeh Yazdanpanah. He has been involved in numerous competitive R&D projects, often related to high-performance computing and parallel programming models. His work includes significant contributions to educational innovation, particularly in active learning methodologies and formative assessment using interactive systems. He leads and participates in research labs and teams focused on programming models and computer architecture, notably the PM group at UPC/BSC. These teams develop runtime systems, compilers, and hardware accelerators to push the boundaries of parallel computing efficiency and programmability.

• Neuromorphic Computing
• Hardware Accelerators
• VLSI Circuits
• +۵ مورد دیگر

Prof. Dr. Tobias Gemmeke is a University Professor at RWTH Aachen University's Faculty of Electrical Engineering and Information Technology, leading the Chair of Integrated Digital Systems and Circuit Design. His work focuses on neuromorphic computing, hardware accelerators, and energy-efficient electronics. He has pioneered advancements in FPGA-based computational neuroscience simulators, neuromorphic processor architectures, and sensor integration for industrial and medical applications. Research interests include time-domain computing, ReRAM reliability, and co-optimization of neural networks with hardware. Notable contributions include the neuroAIx framework for accelerated neuroscience simulations and energy-efficient ASIC designs for post-quantum cryptography. He actively explores memristive devices and domain generalization techniques for edge computing. Recent publications highlight innovations in spiking neural networks, sensor systems for plain bearings, and time-domain compute-in-memory engines. His work bridges theoretical neuroscience with practical hardware implementations, emphasizing scalability and real-time performance.

Kenneth Rossمشاهده پروفایل

استاد

• Database Systems
• Query Processing
• Query Language Design
• +۷ مورد دیگر

Kenneth Ross is a Professor in the Computer Science Department at Columbia University in New York City. His primary appointment is within the Department of Computer Science, with affiliations including the Foundations of Data Science Committee. His work bridges theoretical database research and practical system implementation. His research focuses on database systems with particular expertise in query processing, query language design, data warehousing, and architecture-sensitive database system design. Additional research spans computational biology, especially analysis of large genomic data sets. Current projects include Linear Algebra Operators in Databases for machine learning workloads and Repeats and Somatic Mutation analysis in genomics. His work consistently addresses the intersection of hardware capabilities and database system design. Ross leads the Database Research Lab at Columbia, which has produced significant work on query optimization, GPU database processing, and hardware-conscious database systems. His recent publications demonstrate strong focus on adapting database systems to modern hardware including GPUs, SIMD processors, and persistent memory. His scientific recognition includes: Packard Foundation Fellowship Sloan Foundation Fellowship NSF Young Investigator Award Distinguished Faculty Teaching Award (2008) Ross actively advises undergraduate engineering students (juniors with last names P-Z) and has taught foundational courses including Introduction to Databases and Programming and Problem Solving for over two decades. His teaching portfolio shows consistent engagement with both theoretical concepts and practical implementation challenges in computer science education.

Shantanu Duttمشاهده پروفایل

استاد

• VLSI CAD
• Discrete Optimization
• FPGA Testing and Trusted Design
• +۲ مورد دیگر

Shantanu Dutt is a full Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Chicago , located in Chicago, IL. His office is in 930 SEO at 851 S. Morgan St, and he can be reached at dutt@uic.edu . Education Ph.D. in Computer Science and Engineering, University of Michigan, Ann Arbor (1990) M.Tech. in Computer Engineering, Indian Institute of Technology Kharagpur (1984) B.E. in Electronics and Communication Engineering, Maharaja Sayajirao University of Baroda (1983) Research Interests Professor Dutt’s research agenda centers on VLSI Computer-Aided Design (CAD) , with particular emphasis on physical design and incremental synthesis targeting both ASICs and FPGAs. He explores discrete optimization techniques to solve placement, routing, and partitioning problems. Another major thrust is FPGA built-in self-test (BIST) and trusted design , ensuring provable diagnosability and security against hardware Trojans. He also investigates fault-tolerant computing at both chip and system levels, and develops parallel and distributed computing algorithms for scalable performance. Scientific Awards 1996 Best Paper Award , ACM/IEEE Design Automation Conference, for “A probability-based approach to VLSI circuit partitioning” 1995 Most Influential Paper Award , Fault-Tolerant Computing Symposium, for “Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures” Research Impact and Funding Professor Dutt has published extensively in top-tier journals (IEEE TVLSI, ACM TRETS, IEEE TCAD) and premier conferences (ICCAD, DAC, DATE, FTCS). His work has shaped incremental placement, timing-driven routing, FPGA security, and fault-tolerant multiprocessor architectures. While specific grant numbers are not listed, the breadth and longevity of his publication record indicate sustained funding from NSF, industry, and other agencies. Laboratory and Collaborations Although no formal laboratory name is provided, Professor Dutt’s research is conducted within the ECE department’s VLSI CAD and Fault-Tolerance groups, collaborating with graduate students and colleagues across the US and internationally.

• Computer Engineering
• Embedded Systems
• Fault Tolerance
• +۴ مورد دیگر

Corrado De Sio is a Fixed-term Researcher at the Department of Control and Computer Science (DAUIN) , Politecnico di Torino , affiliated with the College of Computer, Film, and Mechatronics Engineering . His academic roles include course instruction and collaboration for Reconfigurable Computing , High Performance Computing (HPC) , and Operating Systems for High-Performance Supercomputers across multiple academic years (2020-2025). Research Interests focus on: Reliability of reconfigurable systems and FPGAs under radiation effects Hardware-software co-design for fault tolerance Embedded systems in aerospace and safety-critical applications Machine learning acceleration on reconfigurable hardware Radiation effects on real-time operating systems and CNN implementations Recent publications address: 2025: Selective hardening of RISCV soft-processors for space applications 2025: Real-time 'signal for help' gesture recognition systems 2024: Reliability analysis of RISC-V processors and CNN placement algorithms 2023: Fault tolerance in FPGA-based CNNs and radiation effects on RTOS Patents include: PyXEL - Python Toolkit for Reconfigurable Hardware Surveillance Software for Real-Time Violence Detection Academic Supervision : Co-supervisor for PhD candidate Arash Amini Bardpareh in Computer and Systems Engineering .

Michela Becchiمشاهده پروفایل

دانشیار

• Computer Architecture
• Systems Software
• Heterogeneous Computing
• +۵ مورد دیگر

Michela Becchi is an Associate Professor in the Department of Electrical and Computer Engineering at North Carolina State University. She specializes in computer architecture, systems software, and applications, with a focus on heterogeneous systems, parallel algorithms, and acceleration techniques for bioinformatics, pattern recognition, and quantum computing. Her work spans multi-core CPUs, GPUs, FPGAs, and distributed clusters, emphasizing the boundary between hardware and software design. Dr. Becchi holds a Ph.D. and Master’s degree in Computer Engineering from Washington University in St. Louis (2009) and a Bachelor’s degree in Computer Engineering from Politecnico di Milano, Italy (2000). Her research has been recognized with prestigious awards, including the NSF CAREER Award (2015) and the University of Missouri System President Award for Early Career Excellence (2016). Her research interests include compiler and runtime techniques for heterogeneous systems, acceleration of bioinformatics algorithms, and high-speed networking applications. She has pioneered frameworks for efficient data transformation, GPU-accelerated compression, and memory-efficient graph algorithms for quantum computing. Her work also explores thread coarsening, mixed-precision auto-tuning, and secure multi-core processor design. Key contributions include the PILOT runtime system for GPU memory management, the GPU-FPtuner auto-tuner for floating-point applications, and innovative approaches to automata processors for genomic analysis. Her publications emphasize reproducible accuracy in scientific simulations and the optimization of irregular applications on many-core platforms.

Vyas Sekarمشاهده پروفایل

استاد

• Networking
• Cybersecurity
• Network Security
• +۹ مورد دیگر

Vyas Sekar is the Tan Family Professor of Electrical and Computer Engineering at Carnegie Mellon University (CMU), with a courtesy appointment in the Computer Science Department. He is affiliated with CyLab and co-directs the Future of Enterprise Security initiative. His research focuses on networking, cybersecurity, distributed systems, and IoT security, with an emphasis on data-driven approaches and network verification. Education: Ph.D. in Computer Science (2010) from CMU; B.Tech. from IIT Madras (President of India Gold Medal recipient). Professional roles include Chief Scientist at Conviva and co-founder of Rockfish Data. Research Interests: Cybersecurity, network security, software-defined networking (SDN), IoT security, DDoS defense, privacy-preserving data sharing, and network performance optimization. Recent work includes developing tools like Pigasus (FPGA-accelerated intrusion detection), Nomad (cloud side-channel mitigation), and frameworks for anomaly detection in IoT networks. Articles Trends: Recent publications address advanced threats like LLM-driven network attacks, stealthy automotive network exploits (CANDid), and optical-layer DDoS defenses. Emphasis on practical solutions (e.g., SketchPlan for telemetry, Pryde for firewall evasion detection). Awards: ACM SIGCOMM Test of Time Award (2022), IIT Madras Young Alumni Achiever Award (2022), Intel Outstanding Researcher Award (2021), and NSF CAREER Award (2016). Recognized for contributions to intrusion prevention, network security, and IoT resilience. Grants & Projects: Led NSF-funded ONSET project (optical-layer DDoS defense), CyLab's Secure IoT Initiative, and collaborations with industry partners like Intel, Facebook, and Nokia Bell Labs. Advises graduate students in cybersecurity and networking. Labs & Teams: Active contributor to CyLab, co-developer of frameworks like Lumos (hidden IoT device detection) and KalKi (IoT security platform). Engages in interdisciplinary research across CMU’s Robotics Institute and Software Engineering Institute.

Austin Rovinskiمشاهده پروفایل

استادیار

• Computer Architecture
• VLSI
• Electronic Design Automation (EDA)
• +۵ مورد دیگر

Austin Rovinski is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University’s Tandon School of Engineering. He specializes in chip design, electronic design automation (EDA), and open-source hardware methodologies. His research focuses on VLSI design, domain-specific accelerators, and chiplet-based systems. Prior to NYU, he held a postdoctoral position at Cornell University and earned all his degrees (Ph.D., M.S., and B.S.) from the University of Michigan. Education: Ph.D., Electrical Engineering, University of Michigan - Ann Arbor Master’s, Electrical Engineering, University of Michigan - Ann Arbor Bachelor’s, Electrical Engineering, University of Michigan - Ann Arbor Research Focus: Developing open-source EDA frameworks like OpenROAD Optoelectronic interconnect systems for 2.5D packaging Agile hardware design methodologies Reconfigurable sparse matrix accelerators RISC-V-based manycore processors (e.g., Celerity project) Key Contributions: Austin led the development of the OpenROAD RTL-to-GDS flow and contributed to the Sirius and Celerity projects. His work emphasizes reproducibility, democratizing chip design through open-source tools. Awards: IEEE Micro Top Picks (2015) Michigan EECS Outstanding Research Award (2016) NSF Graduate Research Fellowship Honorable Mention (2017, 2018) Advising & Grants: Actively mentors graduate students in chip design and EDA. His research is supported by NYU’s Tandon School of Engineering and collaborations with industry partners. Labs & Teams: Core contributor to the OpenROAD project, part of NYU’s hardware design and EDA initiatives, and collaborator on the Celerity manycore processor project.