Takeshi Ikenaga is a Professor at Waseda University’s School of Fundamental Science and Engineering and Graduate School of Information, Production and Systems . He earned his Ph.D. in Information & Computer Science from Waseda University in 2001, following B.E. and M.E. degrees in Electrical Engineering (1988–1990). His career spans roles at NTT LSI Laboratories (1990–2002), Kitakyushu Foundation for Advancement of Industry, Science and Technology (FAIS) (1999–2002), and visiting researcher at the University of Massachusetts (1999–2000). Research Interests : Application-specific SoCs for video/image processing, including compression (H.264/AVC, H.265/HEVC), filters (super-resolution, noise reduction), recognition systems (feature detection, object tracking), and communication (UWB, LDPC). He also works on many-core processor design, ultra-low-delay vision systems, and sports analytics (volleyball, figure skating) with real-time 3D pose estimation and ball tracking. Awards : Recipient of the Furukawa Sansui Award (Waseda University, 1988) IEICE Research Encouragement Award (1992) Multiple Best Paper/Presentation Awards (2006–2022) at conferences including DAC/ISSCC, LSI IP Design, ISOCC, ISPACS, and CVIT APSIPA Distinguished Lecturer Certificate (2015) Waseda University Presidential Teaching Award (2020)
Dr. Zhenman Fang is an Associate Professor at the School of Engineering Science , Simon Fraser University (SFU) , where he founded and directs the HiAccel Lab . He also holds an associate membership in the School of Computing Science at SFU. His research focuses on customizable computing with software-defined hardware acceleration , addressing performance, energy-efficiency, and reliability in post-Moore’s law computing across domains like machine learning , big data analytics , quantum chemistry , and precision medicine . Education: Ph.D. in Computer Science from Fudan University (2014), with a visit to University of Minnesota during his studies. Postdoctoral Work: University of California, Los Angeles (UCLA) (2014-2017). Industry Experience: Staff Software Engineer at Xilinx (2017-2019). Dr. Fang’s research spans the entire computing stack , including application characterization , accelerator-rich architecture design , and programming/tool support . He has developed frameworks like HiSpMV , SyncNN , and SQL2FPGA , emphasizing FPGA acceleration for vision transformers , quantum chemistry , and spiking neural networks . His work has been recognized with 3 best paper awards (FPL 2024, TCAD 2019, MEMSYS 2017) and 3 best paper nominees (FCCM 2025, HPCA 2017, ISPASS 2018). Recent publications highlight trends in low-precision machine learning ( ShiftQuant , ESRU ), quantum chemistry acceleration ( SERI ), and vision transformer optimization ( Quasar-ViT ). His HiAccel Lab actively mentors PhD and MASc students , with notable graduates like Alec Lu (PhD 2024, now at Meta) and Philip Stachura (MASc, now with BC Graduate Scholarship). Scientific Awards: Inaugural SFU Research Excellence Award - Horizon Award (2025) FPL 2024 Stamatis Vassiliadis Best Paper NSERC Alliance Award (2020) CFI JELF Award (2019) Xilinx University Program Award (2019) IEEE Senior Member (2023) Grants: NSERC Discovery Grant (2019) CFI JELF Funding (2019) Huawei and Xilinx sponsorships Dr. Fang leads open-source initiatives like SyncNN , PASTA , and SQL2FPGA , and serves as General Chair for ASAP 2025 and Program Co-Chair for RAW 2025 . His lab collaborates globally with institutions such as UCLA , Northeastern University , and Xidian University .
Dr. Hiren Patel is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. He holds a Doctorate in Computer Engineering from Virginia Tech and previously worked as a postdoctoral fellow at UC Berkeley under Edward A. Lee. His research focuses on real-time embedded systems, computer architecture, machine learning hardware, and cybersecurity. He teaches courses like ECE 150 (Programming), ECE 320/429 (Computer Architecture), and ECE 327 (Digital Systems). Research Interests: Cyber-physical systems and hybrid architectures Hardware/software co-design methodologies Predictable cache coherence protocols IoT and edge computing systems Security in embedded and real-time systems Recent work emphasizes cache coherence solutions for safety-critical systems and GPU acceleration strategies. His publications address challenges in multicore predictability, FPGA bandwidth optimization, and autonomous robotics orchestration. No specific awards are listed, though his extensive publication record indicates significant contributions to embedded systems research. He currently oversees graduate student applications focusing on his core research areas.
Marco Platzner is a Professor for Computer Engineering at Paderborn University , Germany. He serves as the Dean of Research for the Faculty of Computer Science, Electrical Engineering and Mathematics and heads the Department of Computer Science. Previously, he held research positions at ETH Zurich, Stanford University, GMD (now Fraunhofer IAIS), and Graz University of Technology. Education: Diploma and PhD in Telematics (Graz University of Technology, 1991 and 1996), Habilitation in Hardware-Software Co-Design (ETH Zurich, 2002) Research Interests focus on reconfigurable computing, approximate computing, self-* computing, and embedded systems. His work addresses hardware security, FPGA design, and sustainable AI in data centers. Current projects include energy-efficient AI through deep neural network approximation for FPGAs (EKI-App) and lifecycle sustainability of socio-technical systems (SAIL). Publication Trends show expertise in FPGA security, approximate circuit synthesis, robotics, and hardware acceleration. Collaborations span robotics (ROS 2 integration), AI (transformer optimization), and cybersecurity (Trojan detection). Scientific Awards: ACM SIGDA Hall of Fame (2020) Significant Paper Award (FPL 2015) Best Paper Awards at IEEE ISVLSI (2024), ARC (2018), IEEE ReConFig (2015), and others Weierstraß Prize for Teaching (2008) Leadership Roles include membership in the board of Paderborn Center for Parallel Computing (PC2) and the Jenny Aloni Centre for Early Career Researchers. He has contributed to EU FP7 FET project EPiCS and German priority programs on embedded systems and organic computing.
Holger Fröning is a full professor at Heidelberg University’s Institute of Computer Engineering (ZITI), where he leads the Hardware and Artificial Intelligence (HAWAII) Lab. His research focuses on embedded machine learning , high-performance computing , and hardware-software co-design , with emphasis on resource efficiency, power optimization, and emerging architectures like analog , photonic , and resistive memory systems. He has held leadership roles including Managing Director of ZITI (2023–present) and Dean of Studies for Computer Science (2019–2022) , and has collaborated with institutions such as NVIDIA Research, Chinese Academy of Sciences, and Graz University of Technology. Research Trends : His recent publications explore Bayesian neural networks , green machine learning , analog computing noise mitigation , and GPU/FPGA optimization . Articles highlight photonic computing for AI , memory-efficient training , and hardware-aware DNN compression . Scientific Awards : 2025 HiPEAC Paper Award (Nature Computational Science) 2014 Google Faculty Research Award Multiple Best Paper Awards (IPDPS, ICPP, ECML-PKDD workshops) Leadership & Service : Organized workshops (WEML, ITEM, F4HD), chaired tracks at EuroPar and ISC, and served on program committees for ICPR, ECAI, and FPL. Education & Affiliations : PhD and MSc from University of Mannheim (2007/2001). Sponsors include DFG, FWF, FFG, NVIDIA, SAP, and XILINX.
Swiss Federal Institute of Technology in LausanneSwitzerland
Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.
Chita R. Das is a Professor at Pennsylvania State University, known for extensive contributions in computer architecture, machine learning, and high-performance computing. Their research focuses on optimizing hardware-software co-design for edge computing, cloud infrastructure, and energy-efficient systems. Key areas include FPGA acceleration, GPU optimization, and serverless computing frameworks. Das collaborates frequently with institutions like AMD and Intel, addressing challenges in parallel computing and distributed systems. Their work bridges theoretical advancements with practical applications in recommendation systems, bioinformatics, and real-time video processing. Research interests span across hardware acceleration techniques, cloud resource management, and sustainable computing. Notable projects include adaptive training frameworks for intermittent power environments and neural-augmented game streaming for mobile platforms. Das's publications often address performance bottlenecks in modern architectures and propose novel solutions for latency and energy efficiency. Recent articles highlight innovations in serverless computing cost optimization, low-bandwidth VR streaming, and FPGA-based bioinformatics tools. Their contributions are characterized by interdisciplinary approaches combining computer architecture with machine learning and embedded systems.
Jingtong Hu is an Associate Professor at the Swanson School of Engineering, University of Pittsburgh, where he also holds the William Kepler Whiteford Faculty Fellowship. His research focuses on Cyber-Physical Systems and Infrastructure Security, with significant contributions to embedded systems, non-volatile memory architectures, and hardware/software co-design for energy-constrained environments. Dr. Hu received his PhD from the University of Texas at Dallas (2007-2013) and his Bachelor of Engineering from Shandong University (2003-2007). His research spans multiple interdisciplinary areas including energy harvesting systems, non-volatile processors, FPGA acceleration, and machine learning at the edge. His recent publications demonstrate a strong focus on algorithm-hardware co-design, particularly for vision transformers, federated learning, and non-volatile memory systems. His work often addresses the challenges of implementing AI on resource-constrained edge devices, with emphasis on energy efficiency, reliability, and performance optimization. The trend in his publications shows increasing focus on sustainable AI processing, heterogeneous computing architectures, and personalized machine learning for IoT applications. Selected Awards: IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award (2021) ACM SIGDA Meritorious Service Award (2019) Multiple Best Paper Award nominations at top conferences including DAC, ASP-DAC, and CODES+ISSS Dr. Hu's research has been supported by multiple grants focusing on energy-efficient computing, non-volatile memory systems, and hardware acceleration for machine learning. His collaborative work spans numerous institutions and involves interdisciplinary teams working at the intersection of computer architecture, embedded systems, and artificial intelligence. His publications show extensive collaboration with researchers at the University of Pittsburgh, particularly with Albert K. Jones and Yiyu Shi. His laboratory work focuses on implementing practical systems for energy harvesting powered devices, non-volatile processors, and hardware accelerators for machine learning applications. Current projects appear to emphasize sustainable AI processing at the edge, heterogeneous FPGA acceleration, and personalized federated learning for health monitoring applications.
Hadi Esmaeilzadeh is an Associate Professor at the University of California, San Diego in the Department of Computer Science and Engineering . He previously served as an Assistant Professor at Georgia Tech (2013-2017) and holds the Halicioğlu Chair in Computer Architecture . As founder/director of the Alternative Computing Technologies (ACT) Laboratory and associate director of UCSD's Center for Machine Integrated Computing and Security (MICS) , his research drives cross-stack solutions for next-generation computer systems. Early tenure recipient at UCSD Coined the term "dark silicon" in computer architecture Developed Tabla/DnnWeaver open-source frameworks Research Interests span: Approximate Computing Neural Acceleration FPGA/ASIC Hardware Design Machine Learning Systems Dark Silicon Challenges Security/Privacy in Accelerated Systems Scientific Recognition : 4 CACM Research Highlights 4 IEEE Micro Top Picks Distinguished Paper Award (HPCA 2016) Inducted to ISCA Hall of Fame (2018) Teaching : Developed courses on accelerator design (CSE 240D) and alternative computing (CS 8803 ACT) Advocates for hands-on FPGA-based learning in Processor Design with FPGAs courses
Soheil Salehi is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at the University of Arizona, with a joint appointment in Systems and Industrial Engineering. He is the Director of the Privacy-preserving, Intelligent, and Secure Computing (PRISM) Lab, established in August 2022. Prior to this, he was an NSF-Sponsored Computing Innovation Fellow and Postdoctoral Research Fellow at the University of California, Davis. Ph.D., Electrical and Computer Engineering, University of Central Florida, 2020 M.S., Electrical and Computer Engineering, University of Central Florida, 2016 B.S., Isfahan University of Technology, Iran, 2014 Dr. Salehi's research focuses on the intersection of hardware, AI, and security. His work spans hardware and AI-enabled security in IoT , Generative AI for hardware design and security , neuromorphic and biologically-inspired AI hardware , emerging spin-based devices , reconfigurable architectures , low-power VLSI circuits , and digital twins and mixed reality for semiconductor workforce development . He also explores the application of Generative AI in personalized education . His recent publications, spanning 2023–2025, reveal a strong trend toward integrating AI and machine learning into hardware security and design. Key themes include automated secure IC design flows , AI-driven hardware obfuscation , firmware and side-channel attack analysis , security in neuromorphic and spiking neural networks , and educational frameworks using digital twins and generative models . His work appears in top venues like DAC, ICCAD, USENIX Security, IEEE TCAS-I, and ISCAS. Outstanding Reviewer Award, IEEE/ACM Design Automation Conference (DAC), 2023 Best Presentation of the Symposium Award, UC Davis Postdoctoral Research Symposium, 2021 UCF Excellence by a Graduate Teaching Assistant (University-Level), 2016 Nominated for 30-under-30 Award, UCF, 2020 Nominated for Postdoctoral Research Excellence Award, UC Davis, 2022 Dr. Salehi has secured significant research funding as PI and Co-PI, including a $300K NSF SaTC EAGER grant on Generative AI-based Personalized Cybersecurity Tutor, a $174,000 University of Arizona PIF Award, and multiple RII grants totaling over $198K. He has also received industry funding from CHEST. He actively mentors students and leads the PRISM Lab, which focuses on privacy-preserving and intelligent secure computing. His service includes roles as Technical Program Committee (TPC) Member and Session Chair at premier conferences such as DAC, ICCAD, CCS, NDSS, and GLSVLSI. The PRISM Lab, under his direction, conducts cutting-edge research in secure and intelligent hardware systems, with applications in IoT, edge computing, and workforce development. The lab emphasizes interdisciplinary collaboration and innovation in both research and education.
Prof. Baker Mohammad serves as Professor and Director of the System on Chip Lab in the Department of Computer and Information Engineering at Khalifa University. With over 15 years of industrial experience at Intel and Qualcomm designing microprocessors and DSP chips, he bridges academic research with real-world engineering challenges in high-performance computing and low-power systems. His educational background includes: Ph.D. in Electrical and Computer Engineering, University of Texas at Austin (2008) M.S. in Electrical and Computer Engineering, Arizona State University B.S. in Electrical Engineering, University of New Mexico Dr. Mohammad's research spans cutting-edge domains where VLSI design converges with AI acceleration and emerging memory technologies . His work pioneers Memristor applications in environmental sensing (radiation, vacuum, glucose) and neuromorphic computing, while advancing energy harvesting systems for wearable electronics. The integration of in-memory computing with security primitives represents a paradigm shift in hardware design, moving beyond traditional CMOS limitations. His publication trajectory reveals accelerating focus on self-powered neuromorphic systems and RRAM-based architectures, with recent work (2021-2023) emphasizing hardware-software co-design for edge AI. Over 75% of his recent publications involve cross-disciplinary collaborations spanning materials science, chemistry, and biomedical engineering. Notable scientific recognition includes: IEEE TVLSI Best Paper Award 2016 IEEE MWSCAS Myrill B. Reed Best Paper Award Qualcomm Qstar Award for Performance Leadership KUSTAR IP Excellence Award Multiple SRC Techon Best Session Papers As a dedicated mentor, he has supervised over 15 graduate students while securing competitive funding from Khalifa University, ADEK, Qualcomm, Tii, and UAE space agencies. His grant portfolio demonstrates exceptional translational impact, converting fundamental research in memristive devices into drone flight computers and medical sensors. Current projects integrate academic rigor with industrial deployment timelines. The System on Chip Lab operates as a multidisciplinary hub where semiconductor physicists collaborate with AI researchers to develop RISC-V-based secure processors and piezoelectric nanogenerator systems. Recent expansions include partnerships with Tii for aerospace applications and medical device startups for glucose monitoring technology.
Professor Tulika Mitra is the Dean of the School of Computing and Vice Provost (Special Projects) at the National University of Singapore (NUS). She holds the Provost’s Chair Professor in the Department of Computer Science and has been instrumental in shaping academic policies and strategic initiatives at NUS since joining in 2001. PhD in Computer Science, Stony Brook University (2000) M.E. in Computer Science, Indian Institute of Science (1997) B.E. in Computer Science, Jadavpur University (1995) Her research focuses on hardware-software co-design for energy-efficient computing systems, particularly in real-time embedded systems, heterogeneous architectures, and AI accelerators. She leads major research programs such as the NRF Competitive Research Programme on Low-Power Edge Accelerators and the MOE Tier-3 Programme on Green AI , collaborating with industry leaders like ARM, AMD, and Meta. Her recent publications highlight innovations in CGRA optimization , sparse attention mechanisms , photonic-digital hybrid architectures , and low-power ML inference . These works often integrate compiler techniques, architectural design, and real-time constraints for edge computing applications. Scientific Awards : ESWEEK Test-of-Time Award (2022), ACM SIGDA Distinguished Service Award, IEEE CEDA Outstanding Service Recognition Award, Teaching Excellence Award (2006), and multiple best paper recognitions. Education Leadership : Spearheaded the Computer Engineering (CEG) Programme at NUS, a joint initiative between Engineering and Computing. As a mentor , she has supervised over 25 PhD students , many now in prominent academic or industrial roles. Her research group eCO Lab focuses on embedded computing challenges, while her grant collaborations include projects on 5G base stations, reconfigurable architectures, and IoT-optimized SoCs.
Hadi Esmaeilzadeh is an Associate Professor at the University of California, San Diego in the Department of Computer Science and Engineering . He leads the Alternative Computing Technologies (ACT) Laboratory and serves as Associate Director of the Center for Machine Integrated Computing and Security (MICS) . Previously, he was an Assistant Professor at Georgia Institute of Technology. Ph.D., Computer Science and Engineering, University of Washington (2013) Research focuses on computer architecture , machine learning acceleration , and approximate computing His work has produced 15+ publications spanning IEEE Micro Top Picks , CACM Research Highlights , and ISCA . Key projects include: Tabla : Cross-stack ML acceleration framework DnnWeaver : Open-source DNN acceleration platform Major honors include: IEEE TCCA Young Computer Architect Award ISCA Hall of Fame Qualcomm Innovation Fellowship Georgia Tech PURA Award Teaching roles: CSE 141: Introduction to Computer Architecture CSE 240D: Accelerator Design for Deep Learning CSE 240A: Principles of Computer Architecture
Professor Wayne Luk is a Professor of Computer Engineering at the Department of Computing, Faculty of Engineering, Imperial College London. He leads the Programming Languages and Systems Section and the Custom Computing Research Group, and directs the EPSRC Centre for Doctoral Training in High-performance Embedded and Distributed Systems and the Centre for Advanced Financial Engineering. He previously served as a Visiting Professor at Stanford University from 2006 to 2009. His research spans FPGA acceleration, quantum computing, deep learning optimization, and algorithm-hardware co-design, with affiliations to the CRUK Convergence Science Centre and the Engineering Secure Software Systems group. His research interests include computational modeling for particle physics, causal discovery in agent-based systems, and high-throughput digital electronics. Notable contributions include FPGA-accelerated algorithms for neural networks, quantum circuit simulation, and Bayesian optimization frameworks. His work emphasizes practical applications of reconfigurable hardware in fields like medical imaging, high-energy physics, and financial systems. Professor Luk is a Fellow of the Royal Academy of Engineering, IEEE, and BCS. His publications focus on advancing hardware-aware machine learning, FPGA-based acceleration techniques, and scalable design methodologies. His research bridges theoretical computer science with applied engineering, addressing challenges in real-time systems, embedded computing, and next-generation computing architectures. His academic leadership includes directing interdisciplinary centers and training programs, fostering collaboration across computing, engineering, and physics. Current projects explore quantum computing tools, causal inference systems, and high-performance graph neural networks for particle physics applications.
Associate Professor Oliver Diessel is a faculty member at the University of New South Wales (UNSW) within the School of Computer Science and Engineering. He has been actively teaching and conducting research at UNSW since at least 2000, with teaching experience spanning various computer architecture and digital systems courses. Dr. Diessel completed his education at the University of Newcastle, Australia, earning a B.E. (Computer, Hons) and B.Math. in 1991, followed by a PhD in 1998. His academic career has focused on reconfigurable computing systems and computer architecture. His primary research interests center around the design, test, and implementation of digital systems in reconfigurable logic devices called Field-Programmable Gate Arrays (FPGAs). Specifically, he focuses on dynamically reconfigurable digital systems where circuits can be modified while the system is operational. His work aims to develop architectures, design methods, and tools that enhance the benefits and reduce the costs of reconfigurable systems. Current research projects include fault-tolerant FPGA-based systems for space applications and fine-grained accelerators for heterogeneous devices. Dr. Diessel has published extensively with 2 books, 1 book chapter, 16 journal articles, 67 conference papers, 1 edited conference proceedings, and 7 conference presentations to his credit. His publications reflect a strong emphasis on reconfigurable technology, computer architecture, and electronic design automation. As a supervisor, Dr. Diessel currently mentors two MPhil students: Tong Wu working on Runtime reconfiguration and Junning Fan working on Fault-tolerance of FPGA-based applications. He has previously supervised six students to completion. His supervision interests include reconfigurable technology and systems, electronic design automation, and computer architecture. Dr. Diessel is an active member of the professional community, serving on the Editorial Board of ACM Transactions on Reconfigurable Technology and Systems and as an IEEE Member. He has taught numerous courses including Configurable Systems (COMP4601), Computer Architecture (COMP3211, COMP4211), Digital Systems (COMP3222), and FPGA Implementation of Digital Systems using Verilog.
