جستجوی استاد راهنمای دانشگاهی

Benjamin Carrison-Schafer is an Associate Professor and Assistant Dean for Graduate Student Success at the Department of Electrical and Computer Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas. He leads the Design Automation and Reconfigurable Computing Laboratory (DARClab), focusing on systems, high-level design, and programming methodologies for VLSI computing systems and FPGAs. Education: MBA from McGill University, Canada (2012) PhD in Electrical and Electronic Engineering from University of Birmingham, UK (2003) Research Interests: His work spans modeling, analysis, synthesis, optimization, and implementation of VLSI systems. Current projects include: Approximate Computing, High-Level Synthesis Design Space Exploration, Hardware Security, Behavioral MPSoC Optimization, and Automatic Fault-Tolerant System Generation. His research blends theory and practice, using analytical and experimental techniques to solve real-world problems. Publication Trends: Recent publications demonstrate strong focus on hardware security, FPGA optimization, and automated design methodologies. Key themes include High-Level Synthesis innovations, hardware acceleration techniques, and cross-disciplinary applications of reconfigurable computing. His work frequently addresses challenges in hardware trustworthiness, energy efficiency, and design automation scalability. Professional Activities: Associate Editor: IEEE Transactions on Sustainable Computing (2022-present) Conference Chair: ICCD 2024, DCAS 2024 Program Committee: ASP-DAC, DATE, FCCM, GLSVLSI Advising & Labs: Supervises multiple PhD and Master's students at DARClab. Current research includes domain-specific architecture design, hardware security, sustainable computing, and ML for VLSI design. The lab collaborates with industry partners like Renesas Electronics and develops commercial tools through spin-off company highX Technologies.

• Reconfigurable Computing
• FPGAs
• Electronic Design Automation
• +۷ مورد دیگر

Larry Pileggi is the Coraluppi Head and Tanoto Professor of Electrical and Computer Engineering at Carnegie Mellon University (CMU). He is also the Department Head of CMU’s ECE Department and has held prior roles at Westinghouse Research and Development and the University of Texas at Austin. His work bridges academic research and industry innovation, with co-founding ventures like Fabbrix Inc., Extreme DA, and Pearl Street Technologies. Dr. Pileggi earned his Ph.D. in Electrical and Computer Engineering from CMU (1989), following an M.S. (1984) and B.S. (1983) in Electrical Engineering from the University of Pittsburgh. His research focuses on three core areas: secure integrated circuit hardware (mitigating supply-chain threats), integrated circuits design methodologies (supporting sub-20nm CMOS and heterogeneous technologies), and power systems simulation (developing robust grid analysis tools like SUGAR). He has been recognized with numerous awards, including the prestigious 2023 Phil Kaufman Award for contributions to electronic system design, and is an IEEE Fellow. His academic leadership includes fostering maker initiatives and interdisciplinary research programs to address future challenges in energy and computing systems. Pileggi’s advising record includes over 47 Ph.D. students, many of whom collaborate with him in industry ventures. Current and past grants support his work on resilient power grids and novel memory technologies, reflecting a commitment to both theoretical and applied research. His lab, the Pileggi Lab, develops cutting-edge solutions for energy and integrated systems, emphasizing scalable simulation, secure hardware design, and next-generation memory architectures. Collaborations span institutions like ETH Zurich and industry partners in EDA and semiconductor sectors.

• Secure Integrated Circuit Hardware
• Integrated Circuits Design Methodologies
• Power Systems Simulation and Optimization
• +۳ مورد دیگر

Giovanni De Micheli is a Full Professor at École Polytechnique Fédérale de Lausanne (EPFL), holding appointments in both the School of Computer and Communication Sciences (IC) and the School of Engineering (STI). He is affiliated with the Integrated Systems Laboratory (LSI) and serves as Scientific Director of EcoCloud. His primary office is located in INF 341 building at EPFL's Lausanne campus where he conducts research and teaching activities. Professor De Micheli's research spans multiple domains in electronic design automation and integrated circuit design. His primary interests include: Integrated Circuit Design and Hardware Synthesis Logic Optimization and Boolean Methods Nanoelectronics and 2D Electronics Quantum Computing and Emerging Technologies Low-Power Electronics and Energy-Efficient Systems Electronic Design Automation for Novel Computing Paradigms His recent publications demonstrate a strong focus on advancing logic synthesis techniques for both conventional and emerging technologies. Professor De Micheli's work bridges theoretical foundations with practical applications, particularly in adapting traditional EDA methods to novel computing paradigms like quantum computing and superconducting electronics. His research group has made significant contributions to the development of efficient algorithms for circuit optimization across multiple technology domains, with particular emphasis on area, power, and delay optimization while maintaining functional correctness. Professor De Micheli has supervised numerous doctoral students throughout his career at EPFL, mentoring over 40 PhD candidates whose research spans various aspects of electronic design automation, circuit design, and emerging technologies. His students have gone on to make significant contributions in both academia and industry. As Scientific Director of EcoCloud, Professor De Micheli leads research initiatives focused on energy-efficient computing systems and sustainable cloud infrastructure. His laboratory, the Integrated Systems Laboratory, serves as a hub for interdisciplinary research connecting computer science, electrical engineering, and materials science, with particular focus on next-generation computing technologies.

• Integrated Circuit Design
• Hardware Synthesis
• Logic Optimization
• +۵ مورد دیگر

Subhasish Mitra is the William E. Ayer Professor of Electrical Engineering and Computer Science at Stanford University, holding dual appointments in both departments. He leads the Stanford Robust Systems Group and serves on the leadership team of the Microelectronics Commons AI Hardware Hub under the US CHIPS and Science Act. His research spans Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences, with breakthroughs in X-Compact test compression, carbon nanotube computing, and 3D integration. He has held international roles like the Carnot Chair at CEA-LETI and Visiting Professorships globally. Education & Honors: Recipient of over 40 awards including the IEEE Computer Society’s Harry H. Goode Memorial Award, ACM/IEEE’s A. Richard Newton Technical Impact Award, and the Intel Achievement Award. He earned top academic accolades from IIT Kharagpur and Jadavpur University, and is a Fellow of ACM and IEEE. Research Impact: Pioneered first-of-their-kind systems like the carbon nanotube computer and monolithic 3D integration. His work on robust computing techniques like QED validation and X-Compact compression has industry-wide adoption, saving billions in manufacturing costs. Collaborates with industry leaders like Intel, Google, and Samsung. Publications & Grants: Over 400 publications, including award-winning papers in DAC, ISSCC, and IEEE journals. Leads grants from NSF, DoE, and industry partnerships. His lab explores cutting-edge topics like neuromorphic computing, 3D thermal scaffolding, and AI hardware acceleration. Administration & Outreach: Serves as Associate Chair (Faculty Affairs) for Stanford’s Computer Science Department. Recognized by students for mentorship, and frequently invited to global forums like the World Economic Forum and National Academy of Engineering.

• Robust Computing
• NanoSystems
• Electronic Design Automation (EDA)
• +۳ مورد دیگر

Kaveh Razavi is an Assistant Professor at ETH Zurich in the Department of Information Technology and Electrical Engineering, supervising the Computer Security Group. He is also affiliated with the Department of Computer Science. Research focuses on commodity hardware and operating systems security Teaching: Computer Engineering (BSc 2022–2025), Hardware Security (MSc 2016–2025), Advanced Operating Systems (MSc 2016–2019) Research Interests: Razavi's work bridges computer systems and security, emphasizing microarchitectural vulnerabilities, hardware exploitation, and security verification. His group develops tools for analyzing hardware-software interactions and mitigating memory attacks like Rowhammer. Scientific Awards: Distinguished/Best Paper Awards at IEEE S&P, USENIX Security, MICRO Five Pwnies Awards for innovative research Dutch Veni Grant, ERC Starting Grant Jochen Liedtke Young Researcher Award Golden Owl Teaching Award (2022) ETH Medal, Intel Bounty Reward, BlackHat USA Recognition

• Computer Systems
• Computer Security
• Hardware Security
• +۵ مورد دیگر

Geng Yuan is an Assistant Professor at the University of Georgia's School of Computing, specializing in AI systems, energy-efficient deep learning, and hardware-software co-design. His work bridges machine learning algorithms with emerging hardware technologies like superconducting circuits and ReRAM. He holds a Ph.D. in Computer Engineering from Northeastern University (2023) and a Master's in Electrical & Computer Engineering from Syracuse University (2016). Doctor of Philosophy (Ph.D.) in Computer Engineering, Northeastern University (2023) Master of Science (M.S.) in Electrical & Computer Engineering, Syracuse University (2016) Bachelor of Science (B.S.) in Electrical Engineering, Beijing University of Technology (2014) His research focuses on optimizing deep learning systems for edge computing and mobile platforms through techniques like model compression, sparse training, and hardware-aware neural architecture search. Recent projects include adapting large language models via hybrid-grained pruning and developing ultra-low-power AQFP circuits for binary networks. Geng Yuan's publications span top venues like NeurIPS, CVPR, ICML, ICLR, ISCA, and DAC, with notable awards including a Best Paper Award at ICLR Workshop 2021, Spotlight Papers at ICLR 2023 and NeurIPS 2021, and a Design Contest 1st Place at ISLPED 2020. Best Paper Award (ICLR Workshop'21) Spotlight Paper Award (ICLR'23, NeurIPS'21) Design Contest 1st Place (ISLPED'20) Best Paper Nomination (DATE'21, ISQED'18) He actively recruits Ph.D., Master's students, and interns to his research group, focusing on advancing AI systems through interdisciplinary approaches combining machine learning, computer architecture, and electronic design automation.

• Artificial Intelligence Systems
• Energy-Efficient Deep Learning
• Model Compression
• +۵ مورد دیگر

André DeHon is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering at the University of Pennsylvania, with affiliations in the Electrical and Systems Engineering (ESE) and Computer and Information Science (CIS) departments. He founded the Penn Computer Engineering (CMPE) program and directs the DARPA-sponsored CyberSavvy Security Center. His research spans reconfigurable computing, FPGA architecture, interconnect design, hardware security, and energy efficiency, with a focus on adapting to fabrication imperfections and runtime variability. His work explores programmable substrates (e.g., CMOS VLSI, molecular electronics) and algorithmic mappings to create resilient, efficient systems. Current projects include runtime feedback mechanisms (REFINE), partial reconfiguration (ExHiPR), and security frameworks like SCALPEL and μSCOPE. Recent publications highlight advancements in FPGA compilation (PLD, HiPR), security (SCALPEL, μSCOPE), and interconnect optimization (Asymmetry in NoC). These studies intersect computer architecture, security, and embedded systems. Scientific awards and recognitions: 2023 IEEE Fellow 2020 IEEE Mary Kenneth Keller Teaching Award 2018 ACM Fellow TCFPGA Hall of Fame (2019) Best Paper at ICFPT 2015 Academic leadership: He chairs the ACM/SIGDA Technical Committee on FPGAs and Reconfigurable Computing, previously held faculty roles at Caltech (1999–2006), and was a postdoc at UC Berkeley (1996–1999). Education includes MIT SB (1990), SM (1993), and PhD (1996) in Electrical Engineering and Computer Science.

• Reconfigurable Computing
• FPGA Architecture
• Interconnect Design
• +۶ مورد دیگر

Zhonghai Lu is a Professor of Electronic Systems Design (specializing in Dependable and Autonomous Systems) at KTH Royal Institute of Technology, part of the Department of Electrical Engineering in the School of Electrical Engineering and Computer Science (EECS). He serves as Program Director for KTH's Embedded Systems master's program and Director of Studies at the Division of Electronics and Embedded Systems. His research focuses on Network-on-Chip (NoC), computer architecture, embedded systems, and Prognostics and Health Management (PHM) of power electronics. He leads a research group exploring in-network processing and embedded intelligence, transforming passive networks into active computational frameworks. Lu holds a BSc from Beijing Normal University (1989), MSc and PhD from KTH (2002, 2007), and an MBA in Innovation and Growth from the University of Turku (2012). He has authored over 240 scientific papers, including journal articles and peer-reviewed conferences, with notable recognitions such as Best Paper Awards at NOCS’2015 and EU HiPEAC, and a Featured Paper in IEEE Transactions on Computers (2020). He serves as Associate Editor for ACM Transactions on Architecture and Code Optimization (TACO) and has chaired major conferences like HiPEAC’2017 and NOCS’2018. His research group’s recent work includes integrating AI into hardware acceleration, fault-tolerant neural networks, and RUL estimation for power electronics using recurrent neural networks. Lu has secured grants from the Swedish Research Council and Intel Corporation and developed courses like IL2230 (Hardware Architectures for Deep Learning) and IL2233 (Embedded Intelligence), pioneering embedded AI education at KTH. Education: BSc (Beijing Normal University), MSc/PhD (KTH), MBA (University of Turku) Awards: Best Paper Awards (NOCS, EU HiPEAC), Swedish Research Council Grants, Intel Research Gifts Labs/Teams: Research Group on In-Network Processing and Embedded Intelligence

• Computer Architecture
• Embedded Systems
• Network-on-Chip (NoC)
• +۷ مورد دیگر

Morteza Fayazi is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Utah, with an adjunct position in the Kahlert School of Computing. His research focuses on Electronic Design Automation (EDA), applying machine learning to automate analog and mixed-signal circuit design, and developing high-performance computing systems. He holds a B.Sc. from Sharif University of Technology, and M.S.E./Ph.D. degrees from the University of Michigan. His research interests include AI-driven EDA, RF/circuit automation, and energy-efficient processors. Key achievements include the MEDAL lab’s work on terahertz radars, systolic-array processors (e.g., DAP and Versa), and open-source frameworks like FASCINET and Tablext. He has received awards such as the 2024 College of Engineering Dean’s ETR Fund and the 2017 Outstanding Undergraduate Thesis Award. Teaching responsibilities include multiple iterations of the Digital System Design course (ECE/CS 3700). His work spans over 15 peer-reviewed articles in IEEE Transactions, ACM, and top conferences like ICCAD and VLSI-SOC, emphasizing automation, efficiency, and AI integration in hardware design.

• Electronic Design Automation (EDA)
• Machine Learning (ML) in Analog Circuit Design
• System-on-Chip (SoC) Design Automation
• +۳ مورد دیگر

Debjit Pal is a Post-Doctoral Associate at the School of Electrical and Computer Engineering, Cornell University, and a member of the Computer Systems Laboratory. His research focuses on machine learning techniques for hardware verification, SoC validation, and FPGA optimization. Education: Ph.D. in Computer Engineering (University of Illinois at Urbana-Champaign, 2019) M.S. in Computer Science (IIT Kharagpur, 2012) B.E. in Electronics Engineering (Jadavpur University, 2008) Research Interests: Machine Learning for Electronic Design Automation (EDA) System-on-Chip (SoC) Verification Edge Intelligence as a Service Compiler Optimizations for Reconfigurable and High-Performance Computing Scientific Awards: IEEE CEDA Student Research Award (2016) Best Paper Nomination (ICCAD 2015, DAC 2018, ASP-DAC 2019) E. J. McCluskey Best Doctoral Thesis Competition Semi-Finalist (2020) Travel Grants for ICCAD/DAC/ASPDAC (2018-2019) Professional Roles: Technical Program Committee Member (DAC, VLSID), Reviewer (IEEE TVLSI, DATE, ICCAD). Collaborates with researchers like Zhiru Zhang and Shobha Vasudevan.

• Machine Learning for Electronic Design Automation (EDA)
• System-on-Chip (SoC) Verification
• Hardware Verification
• +۶ مورد دیگر

Wolfgang Kunz is a Full Professor (C4, W3) and Chair of Electronic Design Automation at the Technische Universität Kaiserslautern since 2001. His academic career spans multiple prestigious institutions, including Goethe-University Frankfurt/Main and the University of Massachusetts, Amherst. He has held leadership roles such as Dean (2005-2007) and Vice-Dean (2007-2009) at TU Kaiserslautern. Habilitation (Dr. rer. nat. habil.), Computer Science, University of Potsdam (1996) Doctoral degree (Dr.-Ing.), Electrical Engineering, University of Hannover (1992) Dipl.-Ing. degree, Karlsruhe Institute of Technology (1989) His research focuses on hardware verification, security, and optimization, particularly in embedded systems and processors. His work on formal verification methods has been commercialized by companies like Synopsys, Mentor Graphics, and Siemens EDA. His 2016-2021 publications address critical security issues such as Spectre/Meltdown and introduce innovative verification frameworks adopted by industry leaders like Infineon and OneSpin Solutions. Scientific awards include the IEEE Fellow (2006), German IT Society Award (2005), and TU Kaiserslautern Distinguished Teaching Award (2016). He has served on editorial boards of major journals and coordinated the Erasmus Mundus European Master Program in Embedded Computing Systems since 2010. Key students: Jörg Bormann, Raik Brinkmann, Tobias Ludwig Collaborations: Siemens EDA, Infineon, AbsInt, Intel SCAP Spin-offs: LUBIS EDA, OneSpin Solutions

• Hardware Safety and Security
• Formal Hardware Verification
• Embedded Computing Systems
• +۵ مورد دیگر

Ronald G. Dreslinski is the Morris Wellman Faculty Development Assistant Professor in the Department of Electrical Engineering and Computer Science at the University of Michigan, within the College of Engineering. He leads the Computer Engineering Lab (CEL) and directs multiple government-funded research initiatives. His research focuses on Computer Architecture , Hardware Design Automation , and Electronic Design Automation (EDA) , specializing in autonomous system-on-chip synthesis and reconfigurable computing. His work aims to democratize hardware design by eliminating barriers of cost, expertise, and uncertainty through tools enabling no-human-in-the-loop implementation. Dr. Dreslinski manages significant funding from defense and science agencies. Current projects include: DARPA DSSoC (DASH) DARPA Space-BACN (Cochon) DARPA Prowess (Dr. Dash) IARPA Agile (PANDO) NSF Fuse (Regaining the Edge) Past projects encompass: DARPA CRAFT (CERTUS) DARPA PERFECT DARPA SDH (Transmuter) DARPA IDEA (FASoC, OpenROAD) NASA/AFRL (HPSC) He drives the OpenROAD project toward 24-hour autonomous chip design, with industrial adoption by Intel and IHP for shuttle services. His lab develops open-source tools like FASoC for synthesizable analog-digital SoC composition, advancing portability and correctness-by-construction methodologies.

• Computer Architecture
• Hardware Design Automation
• Electronic Design Automation (EDA)
• +۳ مورد دیگر

Mirjana Stojilovic is a Researcher at École Polytechnique Fédérale de Lausanne (EPFL) in the School of Computer and Communication Sciences (IC), specifically within the Institute of Computer Engineering (IINFCOM) and the Parallel Systems Architecture Laboratory (PARSA). She also serves as a Lecturer in the SSC - Teaching department at EPFL. Her office is located at INJ 235, Station 14, 1015 Lausanne, Switzerland. Mirjana Stojilović received her Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. Her academic journey includes collaborating with the Processor Architecture Laboratory at EPFL as a Guest Researcher from 2010 to 2013, working at the University of Applied Sciences Western Switzerland as a senior researcher from 2013 to 2016, and joining the Parallel Systems Architecture Lab at EPFL in October 2016. Dr. Stojilovic's research spans field-programmable technology, electronic design automation (EDA), and electrical-level attacks and countermeasures for reconfigurable hardware. Her work bridges the gap between hardware design and security, with a particular focus on vulnerability analysis and protection mechanisms for FPGA-based systems in cloud environments. She has made significant contributions to understanding side-channel attacks, fault injection techniques, and secure multi-tenancy solutions for shared hardware resources. Her extensive publication record reveals a clear research trajectory from traditional FPGA design and EDA topics toward increasingly security-focused investigations. Recent work demonstrates deep expertise in power analysis attacks, hardware trojans, and countermeasures for cloud-based FPGA systems, reflecting the growing importance of hardware security in distributed computing environments. Scientific Awards and Recognitions: Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016) Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016) Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012) EPFL School of Computer and Communication Sciences (IC) Teaching Award (2015) Nominated for Best Paper Award at the International Conference on Field-Programmable Technology (FPT) (2020) Dr. Stojilovic has advised numerous PhD students including Coulon Louis, Pirayadi Rouzbeh, and Shrivastava Shashwat, along with past EPFL PhD students Glamocanin Ognjen and Mahmoud Dina. She has supervised dozens of semester and diploma projects focusing on hardware security, FPGAs, design automation, side-channel attacks, and cloud computing. Her service to the academic community includes serving on program committees for FPGA, FCCM, FPL, and DATE conferences, reviewing for multiple IEEE and ACM journals, and acting as associate editor for IEEE ESL and ACM TRETS. As a member of the Parallel Systems Architecture Laboratory at EPFL, Dr. Stojilovic leads research projects investigating security aspects of reconfigurable hardware systems. Her team works at the intersection of computer architecture, electronic design automation, and hardware security, with particular emphasis on vulnerabilities and protections for shared FPGA resources in cloud environments.

• Field-programmable technology
• Electronic design automation (EDA)
• Hardware security
• +۵ مورد دیگر

Callie Hao is an Assistant Professor in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology since 2021, holding the ON Semiconductor Junior Professorship. Her research bridges hardware efficiency and algorithmic innovation with significant industry and federal recognition. Education: Ph.D. in Electrical Engineering, Waseda University (2017) M.S. and B.S. in Computer Science and Engineering, Shanghai Jiao Tong University Research Focus: Dr. Hao pioneers software/hardware co-design for edge AI, specializing in hardware-efficient machine learning algorithms, FPGA-based reconfigurable computing, graph neural networks, and electronic design automation (EDA). Her work emphasizes neural architecture search, high-level synthesis optimization, and memory-efficient systems for embedded and IoT applications, driven by the philosophy that "1 + 1 > 2" for transformative efficiency gains. Publication Impact: Her 15 most recent publications (2023-2026) reveal a strategic shift toward machine learning-driven EDA tools, with 60% focused on high-level synthesis frameworks and 40% on graph neural network acceleration. Key trends include simulation speed breakthroughs (LightningSim), automated accelerator generation (GNNBuilder), and cryptographic hardware innovations (Cryptonite), predominantly published in top-tier venues like MICRO, ICCAD, and DAC. Awards & Recognition: NSF CAREER Award (2024) and Intel Rising Star Faculty Award (2023) Best Paper Awards at MLCAD 2024 and GLSVLSI 2021 ON Semiconductor Junior Professorship (2025) and Sutterfield Family Early Career Professorship (2022) DAC-SDC competition championships (2018-2020) Mentorship & Funding: Dr. Hao advises 8+ Ph.D. students in the Sharc Lab, with Rishov Sarkar winning the Oscar P. Cleaver Award and Qualcomm Innovation Fellowship. Her research is funded by DARPA (2021) for ultra-light video intelligence systems and supported by industry awards from Amazon and Sony. She actively serves on program committees for DAC, ICCAD, and DATE conferences. Lab Leadership: As director of the Sharc Lab (Software/Hardware Co-design lab), she cultivates interdisciplinary research at the intersection of FPGA design, machine learning, and EDA, requiring expertise in Verilog/HLS, GNNs, and compiler technologies while maintaining strict focus on real-world hardware implementation.

• Software/Hardware Co-design
• Reconfigurable Computing
• Graph Computing
• +۵ مورد دیگر

Prof. Dan Jiao is the Synopsys Professor of Electrical and Computer Engineering at Purdue University's Elmore Family School. She leads the Rapid-Heterogeneous Integration (Rapid-HI) Design Institute and serves as Editor-in-Chief of the IEEE Journal on Multiscale and Multiphysics Computational Techniques. Her research focuses on computational electromagnetics, multiphysics modeling, and AI-driven design automation for advanced integrated circuits and quantum systems. She has held academic positions since 2005, progressing from Assistant to Full Professor, and has extensive industry experience at Intel Corporation (2001–2005). Education: PhD in Electrical Engineering, University of Illinois at Urbana-Champaign (2001) Senior Staff Engineer at Intel Corporation (2001–2005) Research Interests: Fast numerical methods for large-scale electromagnetic analysis AI/ML integration in design automation (EDA/MDA) Quantum circuits and spin qubit systems Heterogeneous integration and advanced packaging Multiphysics co-simulation for nano-scale devices Signal/power integrity in high-speed systems Key Projects: Leads the NSTC AIDRFIC program (first NSTC R&D Jump Start project), the DARPA NGMM Rapid-HI Design Institute, and the GENIE-RFIC generative design tool initiative. Also directs the Consortium for Electromagnetic Science and Technology. Awards & Honors: 2022 ACES Computational Electromagnetics Award IEEE Fellow (2016) Intel Outstanding Researcher Award (2019) MTT-S Distinguished Microwave Lecturer (2020–2023) 2013 Schelkunoff Prize Paper Award Advising & Grants: Advised over 30 PhD/master's students and led projects funded by NSF, DARPA, Intel, SRC, and industry partnerships. Key grants include NSF CAREER (2008), ONR Young Investigator (2006), and multiple industry-sponsored initiatives. Labs & Teams: Rapid-HI Design Institute (DARPA NGMM) Quantum device co-design group Multiphysics modeling team

• Computational Electromagnetics
• Computational Multiphysics
• Electronic Design Automation (EDA)
• +۸ مورد دیگر