Keiji Kimura is a Professor in the Department of Computer Science and Engineering at Waseda University's Faculty of Science and Engineering, School of Fundamental Science and Engineering. He earned his Doctor of Engineering from Waseda University and has held academic positions at the university since 1999, progressing from Research Associate to Assistant Professor (2004-2005), Associate Professor (2005-2012), and Professor (2012-present). He is affiliated with multiple professional organizations including ACM, IEEE Computer Society, The Institute of Electronics, Information and Communication Engineers, and Information Processing Society of Japan. His research focuses on computer architecture, particularly parallel computing systems and compiler technology. Kimura has made significant contributions to the development of the OSCAR (Optimally Scheduled Advanced Multiprocessor) automatic parallelizing compiler framework. His work spans multiple areas including multicore processor architecture, power reduction techniques for embedded systems, non-volatile memory systems, and parallelization methods for heterogeneous architectures. His research interests specifically include Multiprocessor Architecture and Parallelizing Compiler development, with applications in real-time systems and energy-efficient computing. Analysis of his recent publications reveals a strong focus on practical implementations of parallel computing technologies across diverse hardware platforms including RISC-V, ARM, and heterogeneous multicore systems. His work demonstrates a consistent trajectory from theoretical compiler development toward practical applications in embedded systems, security, and non-volatile memory technologies. The publications show increasing emphasis on RISC-V architecture, persistent memory programming, and power-efficient computing solutions. MEXT Award for Science and Technology (Research category), 2014.04 Ministry of Education, Culture, Sports, Science and Technology (MEXT) Kimura has served on numerous prestigious conference program committees including PACT, IPDPS, HPCA, and LCPC. His research has been supported through collaborations with major technology companies and government initiatives such as the METI/NEDO project entitled "Multicore Technology for Realtime Consumer Electronics." His work with the OSCAR compiler framework has demonstrated significant performance improvements and power reductions in real-world applications. He leads research in the APAL laboratory (http://www.apal.cs.waseda.ac.jp/) at Waseda University, focusing on advanced parallel processing technologies. His team works on compiler-directed approaches to solve challenges in heterogeneous multicore architectures, with particular emphasis on making parallel programming more accessible while optimizing for both performance and power efficiency. Current research directions include RISC-V secure boot verification, non-volatile memory systems, and GPU-based persistent memory solutions.