Ada Gavrilovska is a Professor at Georgia Tech's School of Computer Science under the College of Computing. Her work focuses on systems software for emerging technologies, including hybrid memory systems, edge computing, and cloud infrastructure. She leads projects in the PRISM Center and ADA Center , with funding from NSF, DoE, SRC, and industry leaders like Cisco and VMware. Education: PhD in Computer Science, Georgia Tech (2004) Research Interests: Designing systems for new hardware and applications, including edge computing, heterogeneous memory management, and LEO satellite platforms. Her work bridges low-level OS mechanisms with high-level distributed systems challenges. Recent Publications highlight trends in LEO satellite resource scheduling Edge-based ML preprocessing Hybrid memory OS abstractions Disaggregated graph analytics Compiler-assisted performance optimization Scientific Awards: Best paper, NFV World Congress (2016) Spotlight paper, IEEE Transactions on Cloud Computing (2014) ISCA-50 25-year retrospective (2023) Advising & Grants: Ada has mentored over 15 PhD students and 10 MS students, with research supported by NSF, DoE, SRC, and industry grants. She serves as PI in the SRC/DARPA PRISM Center.
Prof. Dr. Viktor Leis is a Professor in the Department of Computer Science at the Technical University of Munich (TUM), leading the Chair for Decentralized Information Systems and Data Management. His research focuses on cost-efficient data systems, particularly in cloud environments, with expertise in core database topics like query processing, transaction management, and storage optimization. He earned his PhD from TUM in 2016 and previously held professorships at Friedrich Schiller University Jena and Friedrich-Alexander-Universität Erlangen-Nürnberg before returning to TUM in 2022. His work has been recognized with prestigious awards, including the ACM SIGMOD Dissertation Award, VLDB Early Career Research Contribution Award, and an ERC Starting Grant. Research Interests: Cloud computing, database systems, query optimization, storage engines, transaction processing, and NVMe-optimized systems. Key Projects: Developed the LeanStore storage engine and contributed to the Hyper database system. His recent publications emphasize cloud-native architectures, high-performance storage solutions, and hybrid transactional/analytical processing. He actively teaches courses on distributed systems, cloud databases, and blockchain technologies.
Khanh Nguyen is an Assistant Professor in the Department of Computer Science & Engineering at Texas A&M University, part of the College of Engineering. His research focuses on improving scalability and efficiency in Big Data systems through compiler and runtime innovations, particularly in memory management and distributed computing. Education: Ph.D. in Computer Science, University of California, Los Angeles (2019) M.S. in Computer Science, University of California, Irvine (2015) B.S. in Computer Science, University of California, Irvine (2012) His research interests include programming languages, compiler design, memory management, and Big Data systems. He has developed techniques such as Gerenuk for thin computation over big data, Skyway for distributed heap connectivity, and Yak , a high-performance garbage collector. His work emphasizes resource efficiency and workload scalability, particularly for machine learning and data-parallel applications. Recent publications (2021–2024) highlight advancements in adaptive memory management for warehouse-scale computers, semantics-aware swapping in disaggregated systems, and query-driven distributed tracing. Awards: Google Ph.D. Fellowship (2017) Facebook Ph.D. Fellowship Finalist (2017) His research bridges compiler/runtime systems with large-scale data processing, addressing challenges in distributed systems and far-memory utilization. He collaborates with industry and academic partners to advance practical, scalable solutions for modern data-intensive workloads.
T. N. Vijaykumar is a Professor of Electrical and Computer Engineering at Purdue University's Elmore Family School of Electrical and Computer Engineering. His research focuses on computer architecture, VLSI design, and hardware acceleration for machine learning and datacenter systems. He holds a B.E. (Hons) in Electrical and Electronics Engineering and M.Sc.(Tech) in Computer Science from Birla Institute of Technology and Science, followed by M.S. and Ph.D. in Computer Science from the University of Wisconsin. His work spans GPU architecture optimization, memory systems, network security, and energy-efficient computing. Notable contributions include sparse tensor accelerators, disaggregated datacenter architectures, and secure speculative execution techniques. He has been actively involved in developing accelerators for machine learning inference and frameworks for distributed training of neural radiance fields. His publications address challenges in parallel computing, hardware-software co-design, and real-time systems, with applications in robotics, genomics, and microfluidics. He leads research initiatives funded by NSF and industry partnerships, emphasizing cross-layer optimizations across hardware, software, and networking layers.
Hokeun Kim is an Assistant Professor in the School of Computing and Augmented Intelligence (SCAI) at Arizona State University (ASU), part of the Ira A. Fulton Schools of Engineering. He previously held positions at Hanyang University (2021-2023) and worked in industry roles at Google, LinkedIn, and HP Labs. His research focuses on cyber-physical systems, IoT security, and computer architecture, with a particular emphasis on safety and security aspects of time-sensitive systems. Education: Ph.D. in EECS, University of California, Berkeley (2017) M.S. in EECS, Seoul National University (2012) B.S. in Computer Science and Engineering, Seoul National University (2010) Research Interests: Kim’s work spans secure IoT frameworks, real-time embedded systems, and edge computing. He develops tools like the Secure Swarm Toolkit (SST) and Lingua Franca, addressing challenges in distributed system security, interoperability, and performance. Key Contributions: Authored over 30 peer-reviewed publications in top venues like IEEE Transactions, ACM Conferences, and DATE. Received the ACM/IEEE Best Paper Award (IoTDI 2017) and IEEE Micro Top Picks Honorable Mention (2017). Active in organizing conferences (e.g., DATE, FDL) and serves on technical committees for top journals/conferences. Teaching: Courses include Computer Architecture I/II, Real-Time Embedded Systems, and IoT design at both undergraduate and graduate levels.
Ram Alagappan is an Assistant Professor at the University of Illinois Urbana-Champaign's Siebel School of Computing and Data Science, Department of Computer Science. He co-leads the Distributed And Storage Systems Laboratory (DASSL) and focuses on improving reliability and performance in computer systems. PhD from University of Wisconsin-Madison (2019) Postdoctoral researcher at VMware Research (2020-2022) Research interests span storage systems, distributed systems, and operating systems, with emphasis on: Crash consistency and reliability Consensus protocols and fault tolerance Non-volatile memory optimization Datacenter storage abstractions Recent publications highlight advancements in shared log abstractions (LazyLog, SOSP 2024), replication for KV stores (IONIA, FAST 2024), and fault tolerance in disaggregated datacenters (SplitFT, EuroSys 2024). His work also includes foundational studies on crash vulnerabilities and consistency models. Scientific recognitions include: Best Paper Awards at SOSP 2024, FAST 2020, FAST 2018, FAST 2017 NSF CAREER Award (2023) NetApp Faculty Fellowship (2024) Teaching honors: Listed as Excellent/Outstanding Teacher at UIUC (CS598 Storage Systems, 2022-2023) Ranked 1st in student evaluations for CS739 Distributed Systems at UW-Madison (2020) Grants and service: NSF CAREER Award, IBM-IL Discovery Grant Program Committee roles at OSDI, SOSP, EuroSys, HotStorage Labs & Teams: Co-leader of DASSL research group at UIUC.
Renaud Pacalet is a Researcher at Institut Mines-Télécom – Télécom Paris , affiliated with the Communications and Electronics (Comelec) Department and the System on Chip (LabSoc) research team under the Information Processing and Communication Laboratory (LTCI). His work spans hardware security, embedded systems, and software-defined radio (SDR) architectures. Current Research: Hardware security, side-channel attacks (power, timing, fault injection), RISC-V security analysis using gem5, FPGA scheduling for cloud data centers, and model-driven design methodologies. Past Research: Hardware acceleration for ray tracing, SDR front-end processing, SoC security, and memory bus protection (SecBus project). Teaching: Courses on Digital Systems, Computer Architecture, and Hardware Security at EURECOM, including lab sessions on side-channel attacks and fault analysis. Email: renaud.pacalet@telecom-paris.fr Contact: Télécom ParisTech, Campus SophiaTech, 450 route des Chappes 06410 Biot, France
Willy Zwaenepoel is a Professor and Dean of the Faculty of Engineering at the University of Sydney. He holds a B.S. from the University of Gent and M.S./Ph.D. from Stanford University. Previously, he served as Dean of the School of Computer and Communication Sciences at EPFL and was a faculty member at Rice University. His expertise spans operating systems, distributed systems, and high-performance computing. Education: B.S., University of Ghent, Belgium (1979) M.S., Stanford University (1980) Ph.D., Stanford University (1984) Research Interests: Dr. Zwaenepoel focuses on distributed systems, operating systems, and their applications in database replication, virtual machine performance, and software update mechanisms. His work includes foundational contributions to distributed shared memory (e.g., Treadmarks) and startups like iMimic Networking. Awards: ACM Fellow (2000) IEEE Fellow (1998) Fellow of the Australian Academy of Technical Sciences and Engineering (2020) Recipient of the IEEE Tsutomu Kanai Award (2007) Key Contributions: His research addresses challenges in distributed systems performance, such as latency reduction in key-value stores and efficient graph processing. Current projects explore I/O optimization in virtualized environments and causal consistency for geo-replicated systems. Students/Advising: Advises Ph.D. students and postdocs, including William in database replication. His mentorship led to the Rice University Teaching Award (2000).
Xin Wang is a Professor at Fudan University's School of Computer Science, specifically within the Department of Communication Science and Engineering and affiliated with the State Key Laboratory of ASIC and System in Shanghai, China. With 185 publications spanning two decades (2003-2025), Wang maintains an exceptionally active research profile, particularly evident in recent high-output years including 22 publications in 2019, 19 in 2021, and 13 in 2024. The research portfolio demonstrates deep collaboration networks, most notably with Yang Chen (45 co-authored papers), Yangfan Zhou, and Qingyuan Gong. Wang's research spans multiple critical areas in computer science, with significant contributions to networking systems (particularly CDN optimization, HTTP/3 implementation, and IPv6 infrastructure), software engineering (focusing on work rhythms, testing methodologies, and GUI analysis), mobile applications (including healthcare implementations and accessibility features), and security (especially account security and fraud detection in e-commerce). The interdisciplinary nature of the work is evident through applications in healthcare, e-commerce, campus safety, and IoT systems. Analysis of recent publications (2023-2025) reveals a strong trend toward practical system implementations addressing real-world challenges. The research demonstrates a consistent pattern of moving from theoretical foundations to deployable solutions, with particular emphasis on optimizing performance in networking systems, enhancing security in digital platforms, and improving user experience across diverse application domains. The work frequently incorporates machine learning techniques to solve complex system problems while maintaining practical applicability. While specific grant information isn't detailed in the publication records, the extensive collaboration network spanning multiple institutions in China and internationally suggests substantial research funding support. The consistent publication output across top venues including IEEE/ACM Transactions, INFOCOM, SIGCOMM, and ICSE indicates sustained research productivity and impact.
Nicholas Wright serves as the NERSC Chief Architect and Advanced Technologies Group Lead at Lawrence Berkeley National Laboratory's National Energy Research Scientific Computing Center (NERSC) since 2009. He holds a PhD in Chemistry from the University of Durham, United Kingdom. Role: Focuses on evaluating emerging technologies for scientific computing Key Contributions: Chief architect for NERSC-10 procurement (2026), optimized Perlmutter machine architecture His research explores performance analysis of HPC applications and architectural evaluation for future technologies. Recent publications address: GPU frequency optimization using DNN-based models FPGA acceleration for HPC workloads Quantum computing cost scaling Disaggregated memory system evaluation Scientific workflow characterization Scientific awards include: Co-investigator on SDCI HPC Improvement grant (2007-2012) His work bridges computer architecture and energy-efficient computing through rigorous performance modeling and technology evaluation for NERSC's diverse scientific users.
Miryung Kim is a Professor and Vice Chair of Graduate Studies in UCLA's Computer Science Department, where she directs the Software Engineering and Analysis Laboratory. She is renowned for her pioneering work in software evolution, code clone management, and establishing the emerging field of Software Engineering for Data Intensive Computing (SE4DA and SE4ML). Her research focuses on automated testing and debugging for Apache Spark, developer tools for heterogeneous computing, and conducting systematic studies of refactoring practices in industry. She led the first large-scale study of data scientists in industry and developed JDebloat, a Java bytecode debloating tool that made significant tech transfer impact to the Navy. Her recent publications demonstrate strong trends in fuzz testing for big data analytics and heterogeneous computing, with a focus on natural input generation, co-dependence awareness, and leveraging hardware probes for acceleration. Her work bridges software engineering with data-intensive and heterogeneous computing paradigms. ACM SIGSOFT Influential Educator Award (2022) ICSME Most Influential Paper Award (2023 and 2020) NSF CAREER award Google Faculty Research Award Okawa Foundation Research Award Humboldt Fellow ACM Distinguished Member As an academic advisor, she has produced eight tenure-track faculty members at institutions including Columbia, Purdue, and Virginia Tech. Her research has been supported by National Science Foundation, Air Force Research Laboratory, Google, IBM, Intel, Okawa Foundation, Samsung, and Office of Naval Research. She previously served as Program Co-Chair of ESEC/FSE 2022 and has delivered keynotes at ASE 2019 and ISSTA 2022. She maintains active industry collaborations, serving as an Amazon Scholar at Amazon Web Services and having spent time as a visiting researcher at Microsoft Research.
Pankaj Mehra is an Adjunct Professor in the Department of Computer Science and Engineering at the Jack Baskin School of Engineering, University of California, Santa Cruz (UCSC). He is affiliated with the Storage Systems Research Center (SSRC), now succeeded by the Center for Research in Storage Systems (CRSS). Alongside his academic role, he is the Founder and CEO of Elephance Memory, Inc., and serves as Workstream Lead for Computational x Programming (x = Memory or Storage) at the OpenCompute Project. Ph.D. in Computer Science, University of Illinois at Urbana-Champaign Former Faculty, IIT Delhi Adjunct Faculty, University of California, Wright State University Computer Scientist, NASA Ames Research Center Founder, HP Labs Russia Executive Roles: SVP & WW CTO at Fusion-io; VP at Samsung, SanDisk, Western Digital Pankaj Mehra's research centers on next-generation memory and storage systems. His work explores disaggregated memory architectures, computational storage, non-volatile memory (NVM), and data-centric operating systems. He investigates how to optimize data placement, improve system performance through intelligent caching, and restructure computing models around emerging memory technologies like CXL and persistent memory. His recent publications focus on far memory, tiered memory systems, and offloading computation to storage devices. His recent publications demonstrate a strong focus on memory disaggregation, computational storage, and non-volatile memory systems. Themes include rethinking data and pointer management in distributed memory environments, resource allocation in tiered systems, and designing operating systems that treat data as a first-class citizen. His work bridges academic research and industrial innovation, often involving collaboration with leading researchers at UCSC. Samsung R&D Award (2019) CES R&D Innovation Award (2021) Terabyte Sort Trophy by Jim Gray (1998) TPC-C Cluster Performance Records (1997) Pankaj Mehra has advised and collaborated with numerous researchers and engineers across academia and industry. His work has been supported by affiliations with HP Labs, Fusion-io, Samsung, and now Elephance Memory, Inc. He has led major research and development initiatives, including SmartSSD at Samsung and foundational work on persistent memory at HP. He has also contributed to standards efforts through the InfiniBand Trade Association. He has been a key contributor to the UCSC Storage Systems Research Center (SSRC/CRSS), collaborating with faculty and researchers including Ethan L. Miller, Heiner Litz, and Daniel Bittman. His industry leadership at Elephance Memory, Inc. and involvement in the OpenCompute Project further extend his influence in shaping future data infrastructure technologies.
Sarah Neuwirth is a tenured Professor for Computer Science at Johannes Gutenberg University Mainz (JGU) and a Visiting Researcher at the Jülich Supercomputing Centre. She manages JGU's High Performance Computing (HPC) division, coordinates regional/national HPC activities, and represents JGU in NHR, Gauss-Allianz, and HPC committees. Education : PhD (Dr. rer. nat.) in Computer Science (2018), Heidelberg University Diplom in Computer Science (2012), University of Mannheim Bachelor of Science in Computer Science (2010), University of Mannheim Research Interests : Parallel File and Storage Systems Modular Supercomputing (resource disaggregation/virtualization) Performance Engineering High Performance Computing Networking Reproducible Benchmarking Parallel I/O Publications Trends : Her work focuses on HPC performance modeling, parallel I/O optimization, modular supercomputing, network characterization, and reproducible benchmarks. Key themes include resource disaggregation, automated workflows, and data-intensive distributed applications. Scientific Awards : 2023 PRACE Ada Lovelace Award for HPC ZONTA Science Award 2019 Grants & Leadership : She leads the High Performance Computing division at JGU, participated in European DEEP projects, and serves on SC conference committees.
Professor Sang-Woo Jun is a leading researcher in systems and software for big data analytics, focusing on FPGA-based hardware acceleration and non-volatile memory (NVM) storage. His work spans applications such as graph analytics and bioinformatics, with a strong emphasis on cost-effective, high-performance computing architectures. He advises PhD students like Shengquan Ni and Yicong Huang, both of whom have achieved notable milestones (e.g., thesis defense, fellowship awards). Research Interests: Hardware Acceleration for Big Data FPGA-Based System Architectures Non-Volatile Memory Systems Graph Analytics and Bioinformatics Edge Computing and Low-Power Systems Recent Contributions: His articles highlight innovations in edge accelerators (e.g., IceSpy, Eciton), genomics acceleration (Bancroft), and scalable graph processing (Durin, Sting). These works emphasize reconfigurable systems, privacy-preserving techniques, and energy-efficient designs. Lab & Team: As part of the Intelligent Systems Group (ISG), he collaborates on events like the Southern California Database Day. His research bridges hardware-software co-design with real-world applications in IoT, environmental monitoring, and genomics.
Yuanchao Xu is an Assistant Professor in the Department of Computer Science and Engineering at the University of California Santa Cruz. He earned his Ph.D. from North Carolina State University, advised by Dr. Xipeng Shen and Dr. Yan Solihin, and is a student researcher at SystemResearch@Google since 2021. His research spans computer architecture, security, and ML systems.
