Yingyan (Celine) Lin is an Associate Professor in the School of Computer Science at Georgia Institute of Technology, leading the Efficient and Intelligent Computing (EIC) Lab. Her work focuses on cross-layer innovations in machine learning systems, from algorithms to chip design, aiming to advance green AI and ubiquitous machine learning. She holds a Ph.D. in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign (2017). Research interests include efficient machine learning, neural rendering (e.g., NeRF), hardware-software co-design for AI acceleration, and graph neural networks. Her lab has pioneered projects like RTML and 3DML, funded by NSF, NIH, DARPA, and industry partners (Qualcomm, Intel, Meta). Awards: NSF CAREER Award (2021), ACM SIGDA Outstanding Young Faculty (2022), Meta Faculty Research Award (2022) Grants: Multi-university projects funded by NSF, NIH, DARPA, SRC, ONR, and industry Recognition: First-place wins at DAC 2022 and TinyML Design Contest 2022, IEEE Micro Top Pick 2023 Her research bridges algorithmic innovation with hardware implementation, emphasizing energy efficiency and real-time performance for applications in AR/VR, computer vision, and neuro-symbolic AI systems.
Tushar Krishna is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology, with a courtesy appointment in the School of Computer Science. He earned his PhD in Electrical Engineering and Computer Science from MIT in 2014, an MSE in Electrical Engineering from Princeton University in 2009, and a B.Tech in Electrical Engineering from IIT Delhi in 2007. His research spans computer architecture, interconnection networks, networks-on-chip (NoC), and AI/ML accelerator systems, with a focus on optimizing data movement in modern computing platforms. His work is funded by NSF, DARPA, IARPA, SRC, Department of Energy, Intel, Google, Meta, Qualcomm, and TSMC. His papers have been cited over 17,000 times, with three receiving IEEE Micro's Top Picks recognition, one earning an honorable mention, and four winning best paper awards. Dr. Krishna leads the Synergy Lab at Georgia Tech and has developed several influential tools including ASTRA-sim for distributed AI/ML training, MAESTRO and SCALE-sim for accelerator design space exploration, and Garnet2.0 for NoC simulation. His recent work focuses on large language model acceleration, distributed training systems, and neuro-symbolic AI architectures. He has received numerous teaching and research awards including induction into the HPCA Hall of Fame (2022), the Class of 1940 Teaching Effectiveness Award (2018), and the Roger P. Webb Outstanding Mid-career Faculty Award (2024). HPCA Hall of Fame Inductee (2022) Roger P. Webb Outstanding Mid-career Faculty Award (2024) Richard M. Bass/Eta Kappa Nu Outstanding Junior Teacher Award (2023) Roger P. Webb Outstanding Junior Faculty Award (2021) Class of 1940 Course Survey Teaching Effectiveness Award (2018) Dr. Krishna currently serves as Associate Director for the Center for Research into Novel Computing Hierarchies (CRNCH) and co-chair of the Chakra Execution Traces and Benchmarks Working Group. He has held the ON Semiconductor (Endowed) Junior Professorship at Georgia Tech (2019-2021) and has been a visiting professor at MIT EECS, Harvard University CS, and a researcher at Intel's VSSAD group.
Priyanka Raina is an Assistant Professor of Electrical Engineering at Stanford University, with a courtesy appointment in Computer Science. She leads the Stanford Accelerate research group, focusing on domain-specific hardware architectures and agile hardware-software co-design. Her work emphasizes high-performance, energy-efficient accelerators for emerging technologies. Education: B.Tech. from IIT Delhi (2011), M.S. and Ph.D. from MIT (2013/2018). Postdoctoral experience includes NVIDIA Research (2018) and Amazon Visiting Academic (2023–present). Awards include the Sloan Research Fellowship (2024), NSF CAREER Award (2023), and Terman Faculty Fellowship (2018). Research Interests: Domain-specific architectures, near-memory computing, design productivity, and machine learning acceleration. Her group develops frameworks like AHA (Agile Hardware) for efficient accelerator design and compilers. Awards: Over 10 major awards, including best paper recognitions at VLSI, MICRO, and JSSC. Active roles as Associate Editor for IEEE JSSC and Program Chair for IEEE Hot Chips (2020). Advising & Teaching: Supervises multiple PhD and MS students in hardware design, CGRAs, and ML accelerators. Teaches VLSI design courses (EE271/272/372) and oversees independent studies in embedded systems and chip design. Labs & Collaborations: Affiliated with Stanford PORTAL Center, AHA Center, and SystemX Alliance. Projects include MINOTAUR (edge AI accelerator), Amber (CGRA-based SoC), and EMBER (RRAM macros).
Srijan Kumar is an Assistant Professor in the School of Computational Science and Engineering at Georgia Institute of Technology's College of Computing. His research focuses on data science, AI for security, and online safety, addressing challenges in detecting malicious users, misinformation, and enhancing AI robustness. His work has been deployed in platforms like Flipkart and Wikipedia, and recognized through awards such as the NSF CAREER and Forbes 30 Under 30. Education: B.Tech from Indian Institute of Technology, Kharagpur Ph.D. in Computer Science from University of Maryland, College Park Postdoctoral training at Stanford University Research Interests: Multi-modal/multi-lingual detection of harmful content and users Adversarial robustness of AI models Graph and network analysis for early detection Responsible recommender systems Awards & Grants: NSF CAREER Award (2023) Kavli Fellow (2022) Facebook/Adobe Faculty Awards NSF Convergence Accelerator Phase II grant ($5M) Advising & Labs: Leads the CLAWS Lab, advising over 20 students. Active in mentoring through conferences and NSF-funded projects.
David Wentzloff is a Professor of Electrical Engineering and Computer Science at the University of Michigan, where he has been on faculty since 2007. He directs the Wireless Integrated Circuits and Systems (WICS) group and serves as Director of the Michigan Integrated Circuits Laboratory (MICL). Wentzloff received his B.S.E. from the University of Michigan in 1999 and his S.M. and Ph.D. from MIT in 2002 and 2007. Wentzloff's research focuses on low-power integrated circuits for wireless communication in energy-constrained and volume-constrained applications. His work spans three primary areas: Synthesizable all-digital radios and radio building blocks Wireless body sensor networks (channel modeling, radios, and antennas) Radios and interfaces for millimeter-scale computing devices His innovations have significantly reduced power consumption in wireless communication for IoT devices, impacting standards including Bluetooth, WiFi, and 5G/6G. Analysis of his publication record reveals a consistent focus on ultra-low power wireless communication, with recent work emphasizing back-channel communication techniques that achieve 500x power reduction compared to conventional approaches. His research bridges theoretical circuit design with practical applications in healthcare, industrial monitoring, and consumer electronics. Wentzloff's scientific recognition includes: 2024 University of Michigan Faculty Recognition Award NSF CAREER Award (2012) DARPA Young Faculty Award (2009) Multiple best paper awards Two-time recipient of the Eta Kappa Nu Professor of the Year Award As an educator and mentor, Wentzloff has graduated 21 doctoral students and mentored dozens of master's and undergraduate researchers. He has taught courses ranging from introductory circuits to advanced graduate topics in analog and RF design. His entrepreneurial impact includes co-founding three successful companies: Everactive (formerly PsiKick), Movellus, and CubeWorks, which commercialize technologies developed in his research lab. Wentzloff leads the WICS research group, which operates within the Michigan Integrated Circuits Laboratory. His team develops cutting-edge technologies for batteryless sensing systems, millimeter-scale computing platforms, and ultra-low power wireless communication solutions that enable the next generation of Internet of Things applications.
Gert Cauwenberghs is a Professor of Bioengineering at the University of California San Diego (UCSD), affiliated with the Jacobs School of Engineering. He co-directs the Institute for Neural Computation and holds a visiting professorship at MIT. His research focuses on neuromorphic engineering, energy-efficient neural interfaces, and wearable biosensors. Key contributions include silicon-based adaptive neural circuits, implantable neural recording systems, and in-ear biosensing devices. Education: M.Eng. in Applied Physics (University of Brussels, 1988), M.S. and Ph.D. in Electrical Engineering (Caltech, 1989–1994). Prior roles include Professorships at Johns Hopkins University and Visiting Professor at MIT. Research Interests: Biomedical integrated circuits, neuromorphic computing, brain-machine interfaces, and energy-efficient neural systems. His work bridges neuroengineering and clinical applications, emphasizing adaptive intelligence and low-power designs. Recent Work: Development of femtojoule-efficient neural chips, high-density neural interfaces, and closed-loop wearable systems. Projects include neurobench benchmarking frameworks and RRAM-based neuromorphic hardware. Awards: NSF Career Award (1997), ONR Young Investigator (1999), PECASE (2000), IEEE Distinguished Lecturer (2003–2004). Grants & Labs: Active in NIH and DoD-funded projects, co-directs the UCSD Institute for Neural Computation. Collaborates with industry on neural interface technologies. Labs/Teams: Cauwenberghs Lab at UCSD focuses on integrated neuroengineering systems, including neural recording systems and neuromorphic computing architectures.
Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology and serves as the Director of the 3D Systems Packaging Research Center. His research focuses on heterogeneous integration of microsystems, including 2.5D and 3D ICs and packaging technologies, with significant contributions to advanced cooling systems, electrical and photonic interconnects, and biosensor integration with CMOS. Dr. Bakir's research interests span heterogeneous microsystem design and integration, advanced cooling and power delivery for emerging architectures, electrical and photonic interconnect technologies, biosensor technologies, and nanofabrication. His work addresses critical challenges in next-generation electronics, enabling polylithic integration that concatenates heterogeneous ICs of various functionalities while mimicking monolithic-like densities. His research particularly focuses on co-design of thermal technologies, power delivery networks, and signaling networks for silicon nanoelectronic systems. His recent publications demonstrate strong trends in fused-silica stitch-chip technology for heterogeneous integration, with particular emphasis on RF and mm-wave applications, power delivery for AI accelerators, and thermal management solutions. His work bridges electrical engineering, materials science, and thermal management to solve critical bottlenecks in computing performance and efficiency. 2013 Intel Early Career Faculty Honor Award 2012 DARPA Young Faculty Award 2011 IEEE CPMT Society Outstanding Young Engineer Award 2012 National Academy of Engineering Frontiers of Engineering Symposium Invited Participant 2015 IEEE CPMT Society Distinguished Lecturer 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology More than 25 conference and student paper awards Twelve issued US Patents Dr. Bakir leads the Integrated 3D Systems Lab (I3DS) at Georgia Tech, which is actively researching advanced packaging, interconnects, electrical and thermal design, and system integration. His team has received significant recognition for their work, including multiple best paper awards from major conferences like ECTC, IITC, and CICC. The lab is currently seeking postdoctoral researchers and research faculty to advance next-generation electronics through collaborative research. His lab focuses on enabling the next phase of Moore's Law through polylithic integration, which concatenates heterogeneous ICs of various functionalities (digital, analog, photonic, and mm-wave) using advanced off-chip '2.5D' and '3D' heterogeneous interconnects and packaging. This work impacts applications in high-performance computing, machine learning, edge intelligence, autonomous vehicles, augmented/virtual reality, and healthcare.
Sumeet Kumar Gupta is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University. His academic career spans from his current role to a prior Assistant Professorship at Pennsylvania State University (2014-2017) and an engineering position at Qualcomm Inc. (2012-2014). He holds a PhD in Electrical and Computer Engineering from Purdue University (2012), an M.S. from the same institution (2008), and a B.Tech in Electrical Engineering from IIT Delhi (2006). B.Tech, Electrical Engineering, IIT Delhi (2006) M.S., Electrical and Computer Engineering, Purdue University (2008) PhD, Electrical and Computer Engineering, Purdue University (2012) Dr. Gupta's research focuses on neuromorphic computing, low power variation-aware VLSI design in emerging nanotechnologies, device-circuit co-design, and nano-scale device modeling/simulations. His work addresses challenges in ferroelectric materials, crossbar arrays for deep neural networks, and energy-efficient AI hardware. Recent publications (2025-2024) highlight trends in: Ferroelectric HfO2/HZO thin films Compute-in-memory architectures Variability/stochasticity analysis Machine learning for device optimization Interconnect resistance/temperature effects AI hardware fault tolerance Scientific Awards & Recognitions: DARPA Young Faculty Award (2016) Early Career Professorship, Penn State (2014) 6th TSMC Outstanding Student Research Bronze Award (2012) Magoon Award (Purdue) Outstanding Teaching Assistant Award (Purdue, 2007) Intel PhD Fellowship (2009) His professional journey includes academic appointments at Purdue University (2020-present, Associate Professor) and Pennsylvania State University (2014-2017, Assistant Professor) after industry experience at Qualcomm Inc. (2012-2014). He maintains IEEE and EDS membership while publishing over 100 refereed works.
Jan Madsen is a Professor at DTU Compute, Technical University of Denmark, and Head of the Embedded Systems Engineering section. His research focuses on system-level modeling and design of embedded computing systems, particularly cyber-physical systems, microfluidic biochips, and synthetic biology applications. Develops design automation tools and methodologies for embedded systems Supervises numerous PhD students and leads major research projects Research Interests Key areas include: Embedded systems-on-a-chip Cyber-Physical Systems (Internet-of-Things) Microfluidic Lab-on-Chip devices Synthetic biology with molecular computing Design, modeling, and optimization of complex systems Scientific Awards DATE Fellow (2019) IEEE CEDA Outstanding Recognition (2019) DTU Scientific Advise Award (2013) Best Paper Awards at MECO (2013) and CASES (2009) Jorck’s Foundation Research Award (1995) Publications His 14+ journal papers and 115+ conference papers demonstrate expertise in: SystemC-based modeling frameworks Energy-aware sensor networks Self-healing eDNA architectures Microfluidic biochip synthesis RTOS modeling and MPSoC exploration
Giacomo Indiveri is a dual Professor at the Faculty of Science of the University of Zurich and the Department of Information Technology and Electrical Engineering of ETH Zurich . He serves as the Director of the Institute of Neuroinformatics at both institutions. Indiveri holds an M.Sc. in Electrical Engineering (1992) from the University of Genoa and a Ph.D. in Computer Science (2004) from the same university. Primary Affiliation: University of Zurich (Faculty of Science, Institute of Neuroinformatics) Secondary Affiliation: ETH Zurich (Department of Information Technology and Electrical Engineering) Indiveri's research bridges neuroscience , computer science , and machine learning to develop neuromorphic cognitive systems . His work focuses on spike-based learning , recurrent neural networks , and analog/digital circuit design for real-time sensory-motor systems . He integrates emerging memory technologies into fault-tolerant event-based architectures, enabling brain-inspired computing paradigms in applications like robotics and medical monitoring. His recent publications emphasize neuromorphic hardware for epileptic seizure detection , spiking neural networks in robotic painting , and scalable processors with on-chip learning . These works explore biologically plausible neurons , delay lines , and memory arrays for temporal processing, with applications in healthcare , edge computing , and adaptive control . Scientific Awards & Recognitions: 2021 IEEE Biomedical Circuits and Systems Best Paper Award Senior Member of IEEE Society ERC Fellow with three European Research Council grants Indiveri's group at the Institute of Neuroinformatics develops event-based systems for real-world validation of brain-inspired computing. His work includes multi-core processors , feedback optimizers , and dynamic routing architectures , supported by grants for advancing neuromorphic technologies .
James C. Hoe is Professor of Electrical and Computer Engineering at Carnegie Mellon University (College of Engineering). He is on sabbatical at MangoBoost and directs research in computer architecture, reconfigurable computing, and high-level hardware design. Education Ph.D., Electrical Engineering and Computer Science, MIT (2000) M.S., Electrical Engineering and Computer Science, MIT (1994) B.S., Electrical Engineering and Computer Science, UC Berkeley (1992) Research Interests Professor Hoe’s work spans computer architecture , reconfigurable computing , FPGA architectures , and high-level hardware synthesis . His group created the CoRAM abstraction for virtualized FPGA computing and leads efforts in power-efficient accelerators, in-network computing, and security-oriented FPGA systems. Scientific Awards IEEE Fellow (2013) Intel Outstanding Researcher Award (2021) Research Funding & Projects Intel / VMware Crossroads 3D-FPGA Academic Research Center – co-leading exploration of FPGA roles in future datacenters. DARPA BRASS program ($2.7 M, 4 years) – ensuring long-lived software systems remain robust to resource changes. Pigasus open-source IDS – world’s fastest FPGA-accelerated intrusion-detection system (100 Gb/s on one server). Labs & Teams He heads activities within the Computer Architecture Lab at Carnegie Mellon (CALCM) , supervising graduate researchers on CoRAM++, SPIRAL autotuning, and FPGA overlays for stream processing.
André DeHon is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering at the University of Pennsylvania, affiliated with Electrical and Systems Engineering (ESE) and Computer and Information Science (CIS). He chairs the Computer Engineering (CMPE) program and directs the CyberSavvy Security Center. His research focuses on reconfigurable computing, FPGA architectures, computer security, and energy-efficient hardware design. He holds a Ph.D. and M.S. from MIT and a B.S. from MIT's Lincoln School. Research interests include reconfigurable computing, FPGA interconnect, hardware security, and fault-tolerant systems. Notable achievements include the SEVER & PROTECT DARPA award and IEEE/ACM Fellowships. Recent work addresses fast FPGA compilation (HiPR, PLD), security through compartmentalization (μSCOPE, SCALPEL), and partial reconfiguration techniques. Teaching includes courses on hardware security, system-on-chip architecture, and digital audio basics. Over 200 publications span FPGA design, network-on-chip optimization, and molecular-scale computing. His labs (Implementation of Computation Group) explore physical implementation of computations through hardware-software co-design.
Di Zhu is a Presidential Young Professor in the Department of Materials Science and Engineering at the National University of Singapore (NUS). He holds a B.Eng. from Nanyang Technological University and M.Sc./Ph.D. from MIT, both in Electrical Engineering. His postdoctoral research at Harvard focused on lithium niobate integrated photonics and superconducting detectors. He previously worked as a research scientist and PI at A*STAR's Institute of Materials Research and Engineering (IMRE). Research Interests : Integrated quantum photonics, superconducting detectors, nonlinear optics, and nanofabrication. His group develops scalable quantum photonic devices using lithium niobate and superconducting materials, emphasizing applications in quantum computing, communication, and sensing. Awards : National Research Foundation (NRF) Fellowship Harvard Quantum Initiative (HQI) Postdoctoral Fellowship MIT Jin-Au Kong Thesis Award Advising & Recruitment : Actively recruiting postdocs, PhD students, and interns in areas like integrated photonics, quantum optics, and superconducting detectors. Positions include work on thin-film lithium niobate, quantum simulation, and microwave-optical transduction. Group website: dizhulab.org .
Burak Ozdoganlar is a Ver Planck Endowed Chair Professor of Mechanical Engineering at Carnegie Mellon University (CMU) and Associate Director of the Engineering Research Accelerator. He holds courtesy faculty positions in Biomedical Engineering and Materials Science and Engineering. Ozdoganlar earned his Ph.D. in Mechanical Engineering from the University of Michigan (1999), M.S. degrees from Ohio State University (1993, 1995), and a B.S. in Aeronautical Engineering from Istanbul Technical University (1991). Ph.D., Mechanical Engineering, University of Michigan (1999) MS, Mechanical Engineering, Ohio State University (1995) MS, Aeronautical and Astronautical Engineering, Ohio State University (1993) BS, Aeronautical Engineering, Istanbul Technical University (1991) Ozdoganlar’s research focuses on multi-scale manufacturing processes (macro/micro/nano), precision engineering , structural dynamics , and modal testing , with applications in biomedical device fabrication , microneedle arrays , soft electronics , and 3D ice printing for vascular networks. His work bridges computational modeling with experimental validation. Recent scientific awards include the 2023 AIMBE College of Fellows induction, ASME Fellow (2019), and NSF CAREER Award (2006). He served as interim CTO of the Advanced Robotics for Manufacturing (ARM) Institute and chaired the ASME-MED Manufacturing Equipment Technical Committee. Ozdoganlar leads projects in scalable manufacturing for implantable medical devices , bioelectric medicine , and wearable robotics . His lab develops 3D ice-printed vascular templates for tissue engineering and liquid metal circuits for soft electronics, funded by institutions like the Manufacturing Futures Institute and ARPA-H.
University of Illinois Urbana-ChampaignUnited States
Naresh R. Shanbhag is the Jack Kilby Professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. He serves as Director of the Systems on Nanoscale Information fabriCs (SONIC) Center and held the D.J. Gandhi Distinguished Visiting Professorship at IIT Mumbai from 2015-2020. Previously, he was a visiting faculty member at National Taiwan University (2007) and Stanford University (2014). Dr. Shanbhag received his doctorate from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories as the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. His research focuses on the design of energy-efficient machine learning, communications, and signal processing systems on resource-constrained embedded platforms. He explores fundamental trade-offs between energy efficiency, latency and accuracy of decision-making systems implemented in nanoscale technologies, with applications to computer vision, biomedicine, automatic target recognition, and imaging. His work spans four primary focus areas: Resource-efficient Machine Learning for the Edge, In-memory Computing (IMC), Energy-efficient High Data Rate Communications, and Shannon-inspired Statistical Error Compensation (SEC). Analysis of his recent publications reveals a strong emphasis on in-memory computing architectures (SRAM, MRAM, RRAM) for machine learning acceleration. His work consistently addresses energy-accuracy trade-offs, with increasing attention to security aspects of hardware implementations and applications to MIMO signal processing and edge AI systems. His research demonstrates a progression from theoretical foundations to practical silicon implementations. 2024 Semiconductor Research Corporation Innovation Award 2018 Semiconductor Industry Association/Semiconductor Research Corporation University Researcher Award 2018 IEEE International Symposium on Circuits and Systems Best Paper Award 2006 IEEE Fellow 1996 National Science Foundation CAREER Award Professor Shanbhag has mentored over 50 graduate students who now work at leading technology companies including Qualcomm, Amazon, Nvidia, Intel, and Apple. His research has been generously supported by the National Science Foundation, DARPA, AFRL, Semiconductor Research Corporation, Texas Instruments, Sandia National Laboratories, and industry partners including IBM, GlobalFoundries, and Intel Corporation. He led the Alternative Computational Models research theme (2006-2012) and was the founding Director of the SONIC Center (2013-2017), a 5-year multi-university center funded by DARPA and SRC. Currently, he leads research themes in the SRC and DARPA funded JUMP 2.0 Program's Center for Co-Design of Cognitive Systems and the Center for Ubiquitous Connectivity, and in the NSF IUCRC Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). As Director of the Systems on Nanoscale Information fabriCs (SONIC) Center, Professor Shanbhag leads a multidisciplinary team exploring novel computing paradigms for the nanoscale era. His group has benchmarked an extensive collection of in-memory computing and digital accelerator IC designs, maintaining a publicly available IMC benchmarking repository of metrics extracted from published IC prototypes. His research philosophy integrates concepts from information theory, statistical signal processing, detection and estimation, VLSI architectures, and digital and analog integrated circuits to develop energy-efficient systems from algorithms to silicon implementations.
