جست‌وجوی استاد و پژوهشگر

Jean-Yves Marionمشاهده پروفایل

استاد

• Computer Security
• Cybersecurity
• Malware Analysis
• +۴ مورد دیگر

Jean-Yves Marion is a Professor at the University of Lorraine and director of LORIA (Laboratoire Lorrain de Recherche en Informatique et ses Applications) since 2013. He is a Senior Member of the Institut Universitaire de France (IUF) with appointments in both 2015 and 2025. He teaches at the École Nationale Supérieure des Mines de Nancy (ENSMN) and serves as a scientific advisor for the Cyber Campus. His educational background includes a PhD in Computer Science from the University of Paris 7 (1991), followed by post-doctoral research at Indiana University (1992-1993), and Habilitation to Direct Research (2000). He served as a lecturer at the University of Nancy 2 from 1995-2002 before becoming a professor at the University of Lorraine in 2002. Marion specializes in computer security with a focus on distinguishing malicious code from ordinary software through morphological analysis techniques. His research involves extracting the internal structure of code as if giving it an 'X-ray' to identify signatures of malicious behavior. He works extensively with the High Security Laboratory which maintains a collection of 6 million computer viruses for research purposes. His publications demonstrate a consistent focus on binary code analysis, malware detection, and implicit computational complexity. His work bridges theoretical computer science concepts like Kleene's recursion theorem with practical cybersecurity applications. Senior Member of the Institut Universitaire de France (2015) Senior Member of the Institut Universitaire de France (2025) As director of LORIA, Marion leads research teams working on cybersecurity challenges. His approach to malware analysis, which examines the 'skeleton' of code rather than surface features, represents an innovative methodology in the field. He has presented his work internationally at venues including the International Symposium on Foundations & Practice of Security (FPS 2016) and the International Workshop on Logic and Computational Complexity in Kyoto.

Dongdong Sheمشاهده پروفایل

استادیار

• Security
• Machine Learning
• Fuzzing
• +۳ مورد دیگر

Dongdong She is an Assistant Professor in the Department of Computer Science and Engineering at The Hong Kong University of Science and Technology (HKUST). His research focuses on the intersection of security and machine learning, applying data-driven approaches to solve security problems. He has established himself as a prominent researcher in software security and fuzzing techniques with publications in top conferences including IEEE S&P, CCS, and USENIX Security. Dr. She received his Ph.D. from Columbia University's Department of Computer Science, where he worked with Professors Suman Jana and Baishakhi Ray. Prior to Columbia, he conducted research with Zhiyun Qian on Android Security at the University of California, Riverside. He completed his undergraduate studies at Huazhong University of Science and Technology. His research spans two main areas: LLM Security, which investigates the security of large language models and LLM-powered systems, and LLM for Traditional Security, which leverages LLMs to solve traditional security problems such as program analysis and vulnerability discovery. His work often combines machine learning techniques with traditional security approaches to develop innovative solutions for software security challenges. Dr. She's publication record shows a consistent evolution from foundational work in neural network-assisted fuzzing (NEUZZ) toward more advanced applications in LLM security and program analysis, demonstrating both theoretical rigor and practical impact with techniques adopted by the security community. Among his notable achievements: Distinguished Paper Award at ISSTA 2025 Distinguished Paper Award at IEEE S&P 2025 Best Paper Award Runner-Up at CCS 2022 Second Place in SBFT 2024 Fuzzing Competition Finalist in 2019 NYU CSAW Applied Research Competition Dr. She currently advises several Ph.D. students including Yuchong Xie, Shuangjie Yao, and Qiao Zhang, who began their studies in Fall 2024. He serves on program committees for major conferences including ASE 2025, where he is a PC Member for the Research Papers track. His research is supported by grants enabling his team to pursue innovative approaches at the intersection of machine learning and security. His research group maintains active collaborations with institutions worldwide and contributes to open-source security tools that are widely used in both academia and industry, with a particular focus on developing advanced techniques for software security analysis through the application of machine learning.

Jingling Xueمشاهده پروفایل

استاد

• Programming Languages
• Compilers
• Program Analysis
• +۵ مورد دیگر

Jingling Xue is a Scientia Professor at the School of Computer Science and Engineering at the University of New South Wales (UNSW) in Sydney, Australia. As an IEEE Fellow of the Computer Society, he leads the Programming Languages and Compilers research group, focusing on practical applications of compiler optimization and program analysis techniques. His work bridges theoretical foundations with real-world software systems, particularly in developing open-source tools for large-scale program analysis. Professor Xue received his B.Eng and M.Eng degrees from Tsinghua University in 1984 and 1987, respectively, followed by a PhD from the University of Edinburgh in 1992. His academic journey has established him as a leading figure in programming languages and compiler technology. Xue's research spans programming languages, compiler technology, and program analysis with emphasis on practical relevance. His current projects include compiler techniques for improving parallelism and locality, pointer/alias analysis for million-line-scale programs, and static/dynamic analysis for detecting bugs and security vulnerabilities in real-world applications like web browsers and Android apps. His group actively develops open-source tools to support scientific replicability and reproducibility in these areas. His recent publications demonstrate a strong focus on applying program analysis techniques to modern challenges including AI compilers, homomorphic encryption, security vulnerability detection, and graph processing systems. The work shows evolution from traditional compiler optimization to addressing emerging domains like privacy-preserving computation and deep learning systems while maintaining rigorous theoretical foundations. Scientific Awards: Best Paper Award at CGO'13 Best Paper Award at CGO'16 Distinguished Paper Award at ECOOP'16 Distinguished Paper Award at ICSE'18 Distinguished Paper Award at ISSTA'19 Distinguished Paper Award at ASE'19 Distinguished Artifact Award at ISSTA'23 Best Artifact Award at FSE'23 Distinguished Paper Award at ASE'23 Test-of-Time Award at CGO'21 Professor Xue has successfully supervised 30 PhD students to completion, many of whom now work as professors or researchers in academia and industry. He has served as Program Chair for major conferences including LCTES'13, CC'18, CGO'20, and General Chair for LCTES'20. His group currently focuses on memory safety in Rust, smart contract analysis, AI compilers, compilation for privacy-preserving computation, and adversarial attacks in deep learning. The Programming Languages and Compilers group maintains strong connections with industry partners, translating theoretical advances into practical tools for real-world software development challenges. Their work on pointer analysis, memory safety, and compiler optimizations continues to influence both academic research and industrial practice.

Xuan Zhangمشاهده پروفایل

دانشیار

• Artificial Intelligence Hardware
• Machine Vision Sensors
• Electronic Design Automation
• +۳ مورد دیگر

Xuan Zhang serves as Associate Professor in Electrical and Computer Engineering at Northeastern University, leading the Sensory AI Lab since joining in January 2024. Her research bridges computer architecture, integrated circuits, and artificial intelligence to develop miniaturized AI systems for autonomous physical platforms. She earned her PhD in Electrical and Computer Engineering from Cornell University in 2012. Her educational background forms the foundation for her interdisciplinary work spanning hardware and software co-design. Dr. Zhang's research focuses on artificial intelligence hardware, machine vision sensors, and security for autonomous systems. She pioneers techniques for efficient in-sensor computing, analog circuit optimization via machine learning, and hardware-level privacy preservation. Her work addresses critical challenges in energy efficiency, robustness, and security for edge AI deployment, particularly in resource-constrained environments like medical devices and autonomous vehicles. Analysis of her 2023-2025 publications reveals three dominant trends: (1) hardware-accelerated privacy mechanisms for sensors, (2) machine learning-driven analog circuit design automation, and (3) energy-efficient architectures for neural network inference. These works consistently target real-world applications in healthcare, autonomous systems, and semiconductor design. Her accolades include the prestigious NSF CAREER Award (2020) and leadership in a $10 million federal semiconductor initiative. She contributes to national efforts in AI-powered chip design through the National Center for the Advancement of Semiconductor Technology. Dr. Zhang advises graduate researchers in the Sensory AI Lab, securing significant funding for projects spanning hardware security, in-sensor computing, and autonomous system assurance. Her lab collaborates with federal agencies and industry partners on cutting-edge semiconductor research. The Sensory AI Lab operates at the hardware-software interface, developing novel architectures for intelligent edge devices. Current projects include optical privacy preservation, robust analog design tools, and energy modeling frameworks for in-sensor visual computing systems.

Linghao Songمشاهده پروفایل

استادیار

• Accelerator Architecture
• FPGAs
• Hardware Acceleration Systems
• +۴ مورد دیگر

Linghao Song is an Assistant Professor in the Department of Electrical & Computer Engineering at Yale University. His research focuses on accelerator architecture design, FPGA-based acceleration systems, and ReRAM-based computing. He is affiliated with the School of Engineering & Applied Science and holds expertise in sparse matrix processing, high-level synthesis, and task-parallel programming frameworks. Education: Ph.D. and M.S. from Duke University and University of Pittsburgh, respectively, with a B.S.E. from Shanghai Jiao Tong University. Research Interests: Song's work spans FPGA-accelerated computing, resistive memory (ReRAM) architectures for deep learning and graph processing, and high-performance sparse matrix operations. His recent projects include the TAPA framework for FPGA programming, ReFloat for iterative linear solvers, and the Sextans/Serpens accelerators for sparse matrix computations. Key Contributions: Over 20 peer-reviewed publications on topics like ReRAM-based accelerators (e.g., GraphR, PipeLayer), FPGA optimization frameworks (TAPA, RapidStream), and novel hardware designs for neural networks and graph analytics. His work emphasizes energy efficiency, scalability, and cross-domain applicability of hardware accelerators. Awards: Recipient of the Duke ECE Outstanding Dissertation Award (2021), EDAA Outstanding Dissertation Award (2020), and National Scholarship of China (2012). Labs/Teams: Leads research in FPGA acceleration and memory-based computing, collaborating on projects involving HBM integration, resistive memory architectures, and task-parallel dataflow frameworks.

• Logic-in-memory
• Machine learning
• Nanocomputing
• +۷ مورد دیگر

Marco Vacca is an Associate Professor in the Department of Electronics and Telecommunications (DET) at Politecnico di Torino and a member of the Interdepartmental Center PIC4SeR - PoliTO Interdepartmental Centre for Service Robotics. His work bridges electronics, nanotechnology, and computing architecture with a focus on innovative solutions to the memory wall problem. His research spans Logic-in-memory computing, Machine learning hardware acceleration, and Nanocomputing with specific emphasis on circuit architectures for probabilistic computing, magnetic devices, hybrid technologies integration, and CAD tools for emerging technologies. Dr. Vacca leads research in RISC-V extensions, hardware accelerators for AI, and autonomous robot systems for agricultural applications through the VLSILAB research group. Recent publications reveal a strong trend toward solving fundamental computing challenges through nanoscale innovations, particularly in memory-centric architectures, molecular field-coupled computing, and novel transistor technologies. His work demonstrates how logic-in-memory approaches can overcome traditional von Neumann limitations while improving energy efficiency for AI workloads. Editorial board member of ELECTRONICS (2021-2023) Program committee member for Design, Automation and Test in Europe Conference (DATE) 2020-2021 Dr. Vacca supervises PhD student Alessandro Varaldi working on 'Hardware AI Accelerators for Automotive Applications' and has led significant research projects including 'Device for Storage and Processing Data and Related Method' (2020-2021) and 'Quantum Computing and Quantum Communication: State of the Art and Applications in the Telco Sector' (2020). His grant portfolio shows strong industry and competitive funding support. As a core member of the VLSILAB research group, Dr. Vacca contributes to advancing VLSI theory and design applications with particular focus on implementing Big Data, Machine Learning, and Neural Networks in specialized hardware architectures that push the boundaries of conventional computing.

William Culhaneمشاهده پروفایل

پژوهشگر ارشد

• Big Data Processing
• Cloud Computing
• Distributed Systems
• +۷ مورد دیگر

William Culhane is a Post-doctoral Research Associate working with the Large-Scale Distributed Systems (LSDS) research group at Imperial College London under Dr. Peter Pietzuch. His research focuses on big data processing in cloud computing environments, with expertise spanning distributed systems architecture, network-aware algorithms, and practical implementation of theoretical models. His academic credentials include: PhD in Computer Science from Purdue University (2015), Thesis: "Optimal 'Big Data' Aggregation Systems – From Theory to Practical Application" Masters in Computer Science from Purdue University (2011) BS in Computer Science and Engineering with Music minor from Ohio State University (2008), Cum Laude with Distinction Culhane's research program bridges theoretical computer science with practical systems implementation. His early work established mathematical models for optimal aggregation overlays, demonstrating how specific properties of aggregation functions guide theoretically optimal overlay construction. This evolved into practical systems like LOOM that implement these models for real-world big data processing. His current research on Meta-Dataflows (MDF) enables users to specify solution spaces of data analysis approaches and automatically discover optimal outcomes without code changes. The SquirrelJoin project addresses network skew in distributed joins by dynamically rerouting traffic to underutilized network segments. His publication record shows consistent progression from theoretical foundations (INFOCOM'15, SIGCOMM'14) to applied systems (VLDB 2017, Middleware'14) with practical impact. His professional trajectory includes significant industry exposure through a Google Techstop internship and research at Qatar University, where he explored anonymized database relations for third-party cloud processing. These experiences informed his approach to balancing theoretical purity with practical constraints in distributed systems design. Culhane has developed numerous open-source tools for the research community including LaTeX macros for consistent document formatting, Linux deployment scripts for distributed system management, and JavaScript interactive graphing utilities. These practical contributions demonstrate his commitment to improving research infrastructure beyond his primary publications.

Tiark Rompfمشاهده پروفایل

استادیار

• Compiler Design
• Programming Languages
• Runtime Code Generation
• +۸ مورد دیگر

Tiark Rompf is an Assistant Professor at Purdue University , with research spanning programming languages, compilers, and systems. His work bridges domains including architecture, databases, machine learning, and AI through projects like Reachability Types and Rhyme. Co-director of the Purdue Center for Programming Principles and Software Systems (PurPL) Scientific Advisor at SambaNova Systems Previously a member of the Scala team at EPFL His research focuses on: Runtime code generation and advanced compiler technology Expressive data-centric query languages (Rhyme, Datalog) Reachability type systems for memory safety and effect handling Metaprogramming and logical relations for formal verification Recent publications highlight contributions to Datalog compilation (Flan), nested data structures (Rhyme), and polymorphic reachability types. He leads projects exploring: Compiler optimizations for emerging architectures (GPU, TPU, FPGA) ML-driven compiler improvements Secure multi-party computation via metaprogramming Scientific awards include: NSF CAREER Award (2016) Google Faculty Research Awards (2017, 2018) DOE Early Career Research Award (2017) ACM SIGPLAN PL Software Award (2019) GPCE Test of Time Award (2020) Students and alumni from his group have joined institutions like Databricks, DeepMind, Galois, and Meta. He teaches advanced compiler courses including: CS 590 - Advanced Topics in Compilers CS 352 - Compilers CS 502 - Graduate Compilers

Sandrine Blazyمشاهده پروفایل

استاد

• Formal verification
• Semantics of programming languages
• Compilers
• +۳ مورد دیگر

Sandrine Blazy is a Professor in the Computer Science Department at the University of Rennes, France. She is a member of CELTIQUE (also referred to as Epicure), a joint project-team with Inria Rennes Bretagne Atlantique and the IRISA laboratory. Since 2021, she has served as deputy director of the IRISA CNRS UMR 6074 laboratory and will be the general chair for POPL 2026, which will be held in Rennes. She is also a member of the editorial board of the LMCS journal. Dr. Blazy completed her PhD at CNAM (Conservatoire National des Arts et Métiers) in 1993 with a thesis titled "La spécialisation de programmes pour l'aide à la maintenance du logiciel" (Program Specialization for Software Maintenance Assistance). She later completed her Habilitation à diriger des recherches (HDR) in 2008 at the University of Évry Val d'Essonne with a thesis titled "Sémantiques formelles" (Formal Semantics). Her research focuses on the formal verification of program transformations and semantic properties of programming languages, particularly in the context of the CompCert compiler and Verasco static analyzer. She develops mechanized semantics using the Coq (or Rocq) proof assistant to ensure software correctness and security. A prime application domain of her work is software security, including constant-time programming for cryptographic applications and software obfuscation techniques. Her teaching includes mechanized semantics (in Coq), functional programming (in OCaml), formal methods (using Why3), and software vulnerabilities. Dr. Blazy's publication record from 2019-2025 shows a sustained focus on verified compilation techniques, particularly in preserving security properties during compilation. Her work bridges theoretical formal methods with practical compiler implementation, resulting in tools that have real-world impact in safety-critical systems. She has made significant contributions to the CompCert formally verified compiler project, with particular attention to constant-time preservation for cryptographic applications and JIT compilation verification. Her scientific achievements have been recognized with several major awards: CNRS Silver Medal (2023) Lucas Award from Formal Methods Europe (2023) ACM SIGPLAN Programming Languages Software Award for CompCert (2022) ACM Software System Award for CompCert (2021) Dr. Blazy has been actively involved in the programming languages research community, serving on numerous program committees for major conferences including POPL, ICFP, PLDI, and CPP. She has mentored students and contributed to education through teaching mechanized semantics and formal methods. Her work with the CompCert compiler has led to practical applications in safety-critical systems, with industry collaborations documented in publications like "CompCert: Practical experience on integrating and qualifying a formally verified optimizing compiler" (ERTS 2018). She leads research within the CELTIQUE project team, which focuses on developing trustworthy software using deductive verification. Her team works on advancing the state of the art in formal verification of compilers and static analyzers, with applications in security-critical domains including cryptographic implementations and safety-critical embedded systems.

• Edge Computing
• Fog Computing
• Cloud Computing
• +۴ مورد دیگر

Dragi Kimovski is a Habilitated Assistant Professor in Distributed Systems at Klagenfurt University, Austria, focusing on Edge Computing and AI. He previously held roles at the University of Innsbruck and the University of Information Science and Technology in Macedonia. His research spans Edge/Fog/Cloud computing, multi-objective optimization, and high-performance computing. He has coordinated major projects like 6GContinuum and KärtnerFog, and led initiatives such as DataCloud and ASPIDE. His teaching includes courses on Distributed Computing, Cloud Computing, and IoT. He is the co-creator of the Carinthian Computing Continuum and maintains a blog on Edge AI World. His work emphasizes sustainable and efficient computing solutions for emerging technologies. Education: Not explicitly listed in the provided text. Research Interests: Edge Computing, Fog Computing, Cloud Computing, Multi-objective Optimization, High-Performance Computing, AI in Distributed Systems. His work addresses challenges in resource management, latency reduction, and scalability across heterogeneous environments, with applications in healthcare, IoT, and 6G networks. Projects: 6GContinuum (Coordinator): Focuses on AI services over 6G networks. KärtnerFog (Scientific Coordinator): Develops adaptive Fog infrastructures over 5G. DataCloud (WP5 Leader): Manages Big Data pipelines on the Computing Continuum. ASPIDE (Scientific Coordinator): Advances exascale programming models for data processing. Teaching: Klagenfurt University: Courses include Distributed Computing, IoT, Cloud Computing, and Advanced Programming. University of Innsbruck: Taught Advanced Parallel and Distributed Systems. University of Information Science and Technology: Courses in High-Performance Computing and Network Architectures. Labs/Teams: Co-created the Carinthian Computing Continuum, an automated SDN testbed for Edge computing research. Active in interdisciplinary teams addressing extreme data processing and sustainable computing.

Shuvra S. Bhattacharyyaمشاهده پروفایل

استاد

• Signal Processing
• Embedded Systems
• Biomedical Engineering
• +۳ مورد دیگر

Shuvra S. Bhattacharyya is a Professor at the University of Maryland, College Park (UMD), Department of Electrical and Computer Engineering, with a joint appointment in UMIACS. He is also a part-time visiting professor at Tampere University (Finland) and INSA Rennes (France). His research focuses on signal processing systems, embedded systems, biomedical engineering, and machine learning. He has authored 7 books and over 300 papers, and directs the Maryland DSPCAD Research Group. He holds an NSF Career Award and is an IEEE Fellow. His honors include the Fulbright Senior Specialist and FiDiPro Professorship. He advises graduate students and leads projects in neural decoding, cyber-physical systems, and criminal justice AI. Education: B.S., University of Wisconsin-Madison Ph.D., University of California, Berkeley Research Interests: Signal processing architectures, biomedical circuits, embedded software, hardware/software co-design, and AI for healthcare and criminal justice. His work emphasizes real-time systems, energy efficiency, and interdisciplinary applications. Grants & Awards: NIH Grant for real-time neural decoding (2023) IEEE Fellow (2011) Jimmy Lin Entrepreneurship Award (2012) Labs & Teams: Maryland DSPCAD Research Group, collaborating on dynamic data-driven systems, neural interface technologies, and AI ethics in criminal justice. His work integrates academic and industrial partnerships, including roles at Hitachi America and Kuck & Associates.

Nikolaos Papaspyrouمشاهده پروفایل

استاد

• Programming Languages
• Software Engineering
• Formal Verification
• +۴ مورد دیگر

Nikolaos Papaspyrou is a Professor at the School of Electrical and Computer Engineering of the National Technical University of Athens (NTUA) and a member of the Software Engineering Laboratory . His research focuses on the theory and implementation of programming languages, including semantics, type systems, compilers, static analysis, and formal verification. Since October 2021, he has been on leave from NTUA, working as a Software Engineer for Google in the memory management team for the V8 JavaScript and WebAssembly engine. He previously served as Director of the Division of Computer Science (2017-2019) and was on sabbatical with Google's compiler group in Munich (2015-2016). His work includes the RELEASE project (EU FP7 STREP) for reliable large-scale server software and uncertainty handling in distributed databases (European Social Fund). Ph.D. and Diploma in Electrical and Computer Engineering from NTUA M.Sc. in Computer Science from Cornell University His research interests span programming languages , software engineering , and formal verification , with recent publications on coinductive proofs in Liquid Haskell, concurrency semantics, and quantum compilation. He has supervised over 50 diploma projects and mentored numerous students now at institutions like MIT, Princeton, and UC Berkeley. Awards include conference organizing and program committee roles, though no formal scientific prizes are listed.

• Computer Architecture
• Parallel Computing
• Compiler Technology
• +۳ مورد دیگر

Keiji Kimura is a Professor in the Department of Computer Science and Engineering at Waseda University's Faculty of Science and Engineering, School of Fundamental Science and Engineering. He earned his Doctor of Engineering from Waseda University and has held academic positions at the university since 1999, progressing from Research Associate to Assistant Professor (2004-2005), Associate Professor (2005-2012), and Professor (2012-present). He is affiliated with multiple professional organizations including ACM, IEEE Computer Society, The Institute of Electronics, Information and Communication Engineers, and Information Processing Society of Japan. His research focuses on computer architecture, particularly parallel computing systems and compiler technology. Kimura has made significant contributions to the development of the OSCAR (Optimally Scheduled Advanced Multiprocessor) automatic parallelizing compiler framework. His work spans multiple areas including multicore processor architecture, power reduction techniques for embedded systems, non-volatile memory systems, and parallelization methods for heterogeneous architectures. His research interests specifically include Multiprocessor Architecture and Parallelizing Compiler development, with applications in real-time systems and energy-efficient computing. Analysis of his recent publications reveals a strong focus on practical implementations of parallel computing technologies across diverse hardware platforms including RISC-V, ARM, and heterogeneous multicore systems. His work demonstrates a consistent trajectory from theoretical compiler development toward practical applications in embedded systems, security, and non-volatile memory technologies. The publications show increasing emphasis on RISC-V architecture, persistent memory programming, and power-efficient computing solutions. MEXT Award for Science and Technology (Research category), 2014.04 Ministry of Education, Culture, Sports, Science and Technology (MEXT) Kimura has served on numerous prestigious conference program committees including PACT, IPDPS, HPCA, and LCPC. His research has been supported through collaborations with major technology companies and government initiatives such as the METI/NEDO project entitled "Multicore Technology for Realtime Consumer Electronics." His work with the OSCAR compiler framework has demonstrated significant performance improvements and power reductions in real-world applications. He leads research in the APAL laboratory (http://www.apal.cs.waseda.ac.jp/) at Waseda University, focusing on advanced parallel processing technologies. His team works on compiler-directed approaches to solve challenges in heterogeneous multicore architectures, with particular emphasis on making parallel programming more accessible while optimizing for both performance and power efficiency. Current research directions include RISC-V secure boot verification, non-volatile memory systems, and GPU-based persistent memory solutions.

• Reconfigurable Computing
• Electronics Design Automation
• FPGA Design
• +۶ مورد دیگر

Andrea Guerrieri serves as an Associate Professor at the School of Engineering, University of Applied Sciences and Arts Western Switzerland Valais (HES-SO Valais-Wallis), specializing in reconfigurable computing and electronics design automation. His research has established significant industry impact through tools like DynaRapid and Dynamatic, with technology adopted by major semiconductor companies including MIPS, Intel, and AMD-Xilinx. BSc HES-SO in Industrial Systems - System-on-Chip specialization BSC HES-SO in Computer and Communication Systems - Digital Design specialization MSc HES-SO in Engineering - Embedded Hardware and Firmware specialization Professor Guerrieri's research focuses on reconfigurable computing, electronics design automation (EDA), and security, with particular emphasis on FPGA design, high-level synthesis, and post-quantum cryptography implementations. His work bridges the gap between theoretical computer architecture and practical hardware implementations, with strong applications in space technology and embedded security systems. His recent publications demonstrate increasing focus on energy-efficient implementations for space applications and quantum-resistant cryptographic systems. Analysis of his 15 most recent publications reveals a clear research trajectory toward optimizing FPGA implementations for post-quantum cryptography and space applications. His work consistently addresses the performance bottlenecks in high-level synthesis while maintaining practical applicability for industry partners like NASA, CERN, and major semiconductor companies. The recent surge in best paper awards (three in 2024 alone) reflects growing recognition of his contributions to efficient FPGA compilation techniques and cryptographic implementations. Scientific Awards: Best Paper Award at FPL 2024 Best Paper Award at HPEC 2024 Best Paper Award at ISFPGA 2020 Outstanding Short Paper Award at IEEE HPEC 2024 Outstanding TPC Member Award at DAC 2024 IEEE Senior Member (2021) Multiple Best Paper nominations (FCCM 2022, FPL 2022, HiPEAC 2022) Professor Guerrieri actively participates in international research projects including the DyReCte project (2019-2021) on dynamically reconfigurable cryptoengines for nano-satellites. He currently chairs the Onboard Computing topic for the Swiss consortium CHEESE affiliated with NASA SSERVI and collaborates extensively with industry partners including AMD-Xilinx, NVIDIA, Arm, NASA, and CERN, as well as academic institutions like ETH Zurich and University of Geneva. His current research focuses on developing next-generation EDA tools and reconfigurable computing platforms for both terrestrial and space applications. His laboratory work centers around FPGA-based prototyping and validation, with specialized facilities for space applications testing. Professor Guerrieri leads a research team that includes Andres Upegui, Quentin Berthet, Laurent Gantel, and Gabriel Da Silva Marques, focusing on practical implementations of reconfigurable architectures for security and space applications.

• Reconfigurable Computing
• Electronics Design Automation
• Post-Quantum Cryptography
• +۴ مورد دیگر

Dr. Andrea Guerrieri is an Associate Professor at the University of Applied Sciences and Arts Valais-Wallis - School of Engineering , specializing in Reconfigurable Computing, Electronics Design Automation (EDA), and Post-Quantum Cryptography . His work focuses on accelerating FPGA compilation through tools like DynaRapid and optimizing security protocols via Dynamatic , with technologies adopted by industry leaders including Intel, AMD-Xilinx, and CERN . He holds a BSc in Industrial Systems and a MSc in Engineering from HES-SO, and teaches courses in Digital Design and Embedded Hardware. BSc HES-SO in Industrial Systems (2019) BSc HES-SO in Computer and Communication Systems (2017) MSc HES-SO in Engineering (2021) Guerrieri’s research bridges High-Level Synthesis (HLS) and Reconfigurable Architectures to enhance FPGA performance for both terrestrial and space applications . His 2025 publications highlight advancements in heterogeneous computing , energy-efficient PQC , and rapid compilation frameworks . Notably, his 2024 work on DynaRapid achieved 20× speedup in C-to-FPGA implementation. Key scientific contributions span dataflow circuit optimization , dynamic scheduling , and automated code transformations . His 2023 book Applications Enabled by FPGA-Based Technology and 2021 textbook System-on-Chip Design with Arm established foundational references in embedded systems. Awards include Best Paper at FPL 2024 , Outstanding TPC Member at DAC 2024 , and IEEE Senior Membership (2021) . 2024: Best Paper Award (FPL), Outstanding Short Paper Award (HPEC) 2023: H-Saber publication on PQC optimization 2021: IEEE Senior Member recognition As Chair of Onboard Computing for the CHEESE-NASA SSERVI consortium, he leads international collaborations with ETH Zurich, University of Geneva, California State University , and companies like NVIDIA, Arm, and NASA . His projects include the Innosuisse-funded DyReCte initiative (2019–2021) for reconfigurable cryptoengines in nanosatellites.