Hadi Esmaeilzadeh is an Associate Professor at the University of California, San Diego in the Department of Computer Science and Engineering . He leads the Alternative Computing Technologies (ACT) Laboratory and serves as Associate Director of the Center for Machine Integrated Computing and Security (MICS) . Previously, he was an Assistant Professor at Georgia Institute of Technology. Ph.D., Computer Science and Engineering, University of Washington (2013) Research focuses on computer architecture , machine learning acceleration , and approximate computing His work has produced 15+ publications spanning IEEE Micro Top Picks , CACM Research Highlights , and ISCA . Key projects include: Tabla : Cross-stack ML acceleration framework DnnWeaver : Open-source DNN acceleration platform Major honors include: IEEE TCCA Young Computer Architect Award ISCA Hall of Fame Qualcomm Innovation Fellowship Georgia Tech PURA Award Teaching roles: CSE 141: Introduction to Computer Architecture CSE 240D: Accelerator Design for Deep Learning CSE 240A: Principles of Computer Architecture
Professor Wayne Luk is a Professor of Computer Engineering at the Department of Computing, Faculty of Engineering, Imperial College London. He leads the Programming Languages and Systems Section and the Custom Computing Research Group, and directs the EPSRC Centre for Doctoral Training in High-performance Embedded and Distributed Systems and the Centre for Advanced Financial Engineering. He previously served as a Visiting Professor at Stanford University from 2006 to 2009. His research spans FPGA acceleration, quantum computing, deep learning optimization, and algorithm-hardware co-design, with affiliations to the CRUK Convergence Science Centre and the Engineering Secure Software Systems group. His research interests include computational modeling for particle physics, causal discovery in agent-based systems, and high-throughput digital electronics. Notable contributions include FPGA-accelerated algorithms for neural networks, quantum circuit simulation, and Bayesian optimization frameworks. His work emphasizes practical applications of reconfigurable hardware in fields like medical imaging, high-energy physics, and financial systems. Professor Luk is a Fellow of the Royal Academy of Engineering, IEEE, and BCS. His publications focus on advancing hardware-aware machine learning, FPGA-based acceleration techniques, and scalable design methodologies. His research bridges theoretical computer science with applied engineering, addressing challenges in real-time systems, embedded computing, and next-generation computing architectures. His academic leadership includes directing interdisciplinary centers and training programs, fostering collaboration across computing, engineering, and physics. Current projects explore quantum computing tools, causal inference systems, and high-performance graph neural networks for particle physics applications.
Brandon Lucia is a Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University's College of Engineering. He holds the Kavčić-Moura Professorship and leads the Abstract research group. As CEO and co-founder of Efficient Computer Corp., he bridges academic research with commercial applications in energy-efficient computing. Dr. Lucia received his Ph.D. in Computer Science and Engineering from the University of Washington in 2013, following an MS from the same institution in 2010 and a BS in Computer Science from Tufts University in 2007. His research focuses on the intersection of computer architecture, computer systems, and programming languages, particularly in energy-constrained environments. His primary research interests include intermittent computing, energy harvesting computers, orbital edge computing, and parallel computing systems. Lucia's work addresses fundamental challenges in creating programmable, reliable computing devices that operate without batteries by harvesting energy from their environments, with applications in sensing, medical implants, and space systems. He also investigates software systems and architectures for making parallel computing correct, reliable, and efficient in the post-Moore's Law era. Lucia's publication record shows a clear trajectory toward orbital edge computing and nanosatellite systems, with recent work focusing on computational constellations, visual navigation for satellites, and energy-efficient processing in space. His research spans both theoretical foundations of intermittent computing and practical implementations in hardware and software. 2021 Sloan Research Fellowship 2018 NSF CAREER Award 2018 ASPLOS Best Paper Award IEEE MICRO Top Picks in Computer Architecture (2009, 2010, 2016) 2015 OOPSLA Best Paper Award 2019 IEEE TCCA Young Computer Architect Award 2022 Engineering Faculty Award As an advisor, Lucia has mentored numerous graduate students including Brad Denby, Zhuo Cheng, and Kyle McCleary, many of whom have become co-authors on his significant publications. His lab developed the world's first batteryless PocketQube nanosatellite (Tartan-Artibeus-1), which was deployed to low-Earth orbit aboard the SpaceX Transporter-3 Rocket. Lucia's research has received funding from sources including NSF, DARPA, Google, and VMware, supporting both fundamental research and practical implementations of energy-harvesting computing systems.
Andrew Rice is a Professor of Computer Science at the University of Cambridge's Department of Computer Science and Technology, and holds the Hassabis Fellowship in Computer Science. He is also the Director of Studies in Computer Science at Queens' College. His research focuses on programming languages, software engineering, and machine learning applications in software development. He leads projects like Isaac Computer Science and ALTA (Automated Language Teaching and Assessment), advancing adaptive learning technologies. His work includes static analysis tools such as Error Prone at Google, energy efficiency studies in computing infrastructure, and contributions to the Computing for the Future of the Planet initiative. His teaching emphasizes practical skill development through flipped classrooms and video lectures, earning him the 2014 Pilkington Prize for teaching excellence. He has held visiting roles at Google and collaborated on energy consumption research for mobile devices and data centers. His research spans systems, networking, and natural language processing, with a strong focus on applying computational methods to real-world challenges. Key Projects: Isaac Physics/Computer Science, ALTA, Error Prone Static Analysis Research Themes: Programming Languages, Machine Learning, Energy Efficiency Awards: Pilkington Prize (2014)
Jason Cong is the Volgenau Chair for Engineering Excellence and Distinguished Chancellor's Professor in the Computer Science Department at UCLA's Samueli School of Engineering. He directs the Center for Domain-Specific Computing (CDSC) and the VLSI Architecture, Synthesis, and Technology (VAST) Laboratory, and serves as Associate Vice Provost for Internationalization and Co-Director of UCLA/PKU Student and Scholar Program. Dr. Cong's research spans electronic design automation, customizable computing for machine learning and big-data applications, quantum computing, and highly scalable algorithms. His work has produced over 500 publications with more than 41,000 citations and an H-index of 106. His recent work focuses on quantum computing compilation, domain-specific acceleration for AI workloads, and high-level synthesis optimization techniques that leverage machine learning. His publication trend shows a strong emphasis on quantum computing and machine learning acceleration in recent years, with numerous papers on quantum layout synthesis, LLM acceleration, and high-performance FPGA implementations. His team has developed frameworks like TAPA for task-parallel dataflow programming and RapidStream for automated parallel implementation of FPGA designs. Member of National Academy of Engineering (2017) IEEE Robert N. Noyce Medal recipient (2022) Phil Kaufman Award recipient (2024) ACM Chuck Thacker Breakthrough Award recipient (2024) 18 Best Paper Awards across major conferences Multiple 10-Year Retrospective Most Influential Paper Awards Dr. Cong has graduated 50 PhD students, many of whom are now faculty at major research universities or hold key positions at leading tech companies. He has led over 100 research projects funded by DARPA, NSF, SRC, and industry sponsors. His entrepreneurial activities include founding three successful companies (Aplus Design Technologies, AutoESL, and Falcon Computing Solutions), all acquired by major EDA players. His VAST Laboratory continues to push boundaries in domain-specific computing, with active research in quantum computing, AI acceleration, and high-performance FPGA implementations.
Callie Hao is an Assistant Professor in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology since 2021, holding the ON Semiconductor Junior Professorship. Her research bridges hardware efficiency and algorithmic innovation with significant industry and federal recognition. Education: Ph.D. in Electrical Engineering, Waseda University (2017) M.S. and B.S. in Computer Science and Engineering, Shanghai Jiao Tong University Research Focus: Dr. Hao pioneers software/hardware co-design for edge AI, specializing in hardware-efficient machine learning algorithms, FPGA-based reconfigurable computing, graph neural networks, and electronic design automation (EDA). Her work emphasizes neural architecture search, high-level synthesis optimization, and memory-efficient systems for embedded and IoT applications, driven by the philosophy that "1 + 1 > 2" for transformative efficiency gains. Publication Impact: Her 15 most recent publications (2023-2026) reveal a strategic shift toward machine learning-driven EDA tools, with 60% focused on high-level synthesis frameworks and 40% on graph neural network acceleration. Key trends include simulation speed breakthroughs (LightningSim), automated accelerator generation (GNNBuilder), and cryptographic hardware innovations (Cryptonite), predominantly published in top-tier venues like MICRO, ICCAD, and DAC. Awards & Recognition: NSF CAREER Award (2024) and Intel Rising Star Faculty Award (2023) Best Paper Awards at MLCAD 2024 and GLSVLSI 2021 ON Semiconductor Junior Professorship (2025) and Sutterfield Family Early Career Professorship (2022) DAC-SDC competition championships (2018-2020) Mentorship & Funding: Dr. Hao advises 8+ Ph.D. students in the Sharc Lab, with Rishov Sarkar winning the Oscar P. Cleaver Award and Qualcomm Innovation Fellowship. Her research is funded by DARPA (2021) for ultra-light video intelligence systems and supported by industry awards from Amazon and Sony. She actively serves on program committees for DAC, ICCAD, and DATE conferences. Lab Leadership: As director of the Sharc Lab (Software/Hardware Co-design lab), she cultivates interdisciplinary research at the intersection of FPGA design, machine learning, and EDA, requiring expertise in Verilog/HLS, GNNs, and compiler technologies while maintaining strict focus on real-world hardware implementation.
Brandon Reagen is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University's Tandon School of Engineering, with affiliations in Computer Science, the Center for Advanced Technology in Telecommunications (CATT), and the NYU Center for Cybersecurity (CCS). He holds a PhD in Computer Science from Harvard (2018) and undergraduate degrees in Computer Systems Engineering and Applied Mathematics from the University of Massachusetts, Amherst (2012). His research focuses on computer architecture, hardware acceleration for deep learning and privacy-preserving computation, and VLSI design. He pioneered efficient deep learning accelerator designs through unsafe optimizations and contributed to benchmarking frameworks like Aladdin and MachSuite. His work spans privacy-preserving machine learning, secure computing systems, and hardware-software co-design for cryptographic protocols. Key achievements include the NSF CAREER Award (2024) and Siebel Scholar recognition (2018). His research centers on advancing secure computing through innovations like zero-knowledge proof accelerators (e.g., zkSpeed), fully homomorphic encryption frameworks (Orion), and entropy-guided privacy techniques for large language models. He leads interdisciplinary efforts at CATT and CCS to bridge hardware design and cybersecurity challenges. Reagen's contributions include over 50 publications in top-tier conferences (e.g., ISCA, ASPLOS, MLSys) and industry collaborations at Facebook AI. His work emphasizes practical solutions for encrypted computation efficiency, privacy-preserving inference, and scalable secure systems.
Prof. Dr. Tobias Gemmeke is a University Professor at RWTH Aachen University's Faculty of Electrical Engineering and Information Technology, leading the Chair of Integrated Digital Systems and Circuit Design. His work focuses on neuromorphic computing, hardware accelerators, and energy-efficient electronics. He has pioneered advancements in FPGA-based computational neuroscience simulators, neuromorphic processor architectures, and sensor integration for industrial and medical applications. Research interests include time-domain computing, ReRAM reliability, and co-optimization of neural networks with hardware. Notable contributions include the neuroAIx framework for accelerated neuroscience simulations and energy-efficient ASIC designs for post-quantum cryptography. He actively explores memristive devices and domain generalization techniques for edge computing. Recent publications highlight innovations in spiking neural networks, sensor systems for plain bearings, and time-domain compute-in-memory engines. His work bridges theoretical neuroscience with practical hardware implementations, emphasizing scalability and real-time performance.
Emmett Witchel is a Professor of Computer Science at the University of Texas at Austin , with research spanning computer architecture, systems, networking, security, and privacy . His work focuses on low-level systems optimization and secure concurrent execution. Research Interests: Concurrent systems, secure execution environments, GPU integration, distributed systems. Teaching: CS 380L (Advanced Operating Systems), CS 371M (Mobile Computing). Scientific Awards: Runner-up Best Paper, ASPLOS 2013 Runner-up Award for Outstanding Research, USENIX Symposium 2012 IEEE Micro Top Pick Award 2007 ACM Honorable Mention 2004 George M. Sprowls Award, MIT EECS 2004 Recent Publications demonstrate leadership in CXL pod databases ( Tigon ), stateful serverless computing ( Boki ), SmartNIC-accelerated file systems ( LineFS ), and GPU security ( Telekine ). His work bridges hardware-software co-design and practical systems implementation.
Azad J Naeemi is a Professor holding the Dean's Professorship in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He serves as Editor-in-Chief of the IEEE Journal on Exploratory Computational Devices and Circuits and Associate Director for Computation of the NSF-supported National Nanotechnology Coordinated Infrastructure (NNCI). His educational background includes a B.S. in Electrical Engineering from Sharif University (1994) and M.S./Ph.D. in Electrical and Computer Engineering from Georgia Tech (2001/2003). Prior to academia, he worked as a design engineer in Tehran (1994-1999) and as a research engineer at Georgia Tech's Microelectronics Research Center (2004-2008). Professor Naeemi's research spans nanotechnology with focus on emerging nanoelectronic devices, spintronics, ferroelectric devices, and design technology co-optimization for CMOS/beyond-CMOS technologies. His work bridges materials, devices, circuits, and systems, particularly investigating integrated circuits based on nanoscale devices and interconnects. Educational research includes experiential learning environments for engineering education. Recent publications (2024-2025) demonstrate strong emphasis on spin-orbit torque MRAM, ternary content addressable memories, ferroelectric/antiferroelectric devices, and plasmonic circuits. Key trends include energy-efficient hardware accelerators, neuromorphic computing applications, and compact modeling for advanced technology nodes. His scientific honors include: IEEE Solid-State Circuits Society James Meindl Innovators Award (2022) IEEE Electron Devices Society Paul Rappaport Award (2008) NSF CAREER Award (2013) SRC Inventor Recognition Award (2010) Multiple Georgia Tech teaching awards Professor Naeemi leads research supported by NSF (including NNCI infrastructure) and SRC. His editorial role with IEEE JXCDC positions him at the forefront of exploratory computational devices. He previously served as General Co-Chair for the IEEE International Interconnect Technology Conference (2013). His work connects with Georgia Tech's Microelectronics Research Center and national nanotechnology initiatives through the NNCI network, focusing on computational infrastructure for nanoscale device characterization and design.
Stephen W. Keckler is an Adjunct Professor at the Department of Computer Science , The University of Texas at Austin , and serves as Vice President of Architecture Research at NVIDIA . He is an ACM Fellow , IEEE Fellow , and Sloan Foundation Research Fellow . Education: BS in Electrical Engineering, Stanford University (1990) SM in Computer Science, Massachusetts Institute of Technology (1992) PhD in Computer Science, MIT (1998) Research Interests focus on computer architecture for deep learning , GPU computing , and energy-efficient systems . His work explores memory compression , network-on-chip designs , and heterogeneous computing . Publication Trends highlight advancements in deep learning accelerators , GPU memory systems , and energy-efficient architectures . Notable themes include sparsity exploitation , multi-chip modules , and fault-tolerant GPU pipelines . Scientific Recognition : ACM Fellow IEEE Fellow Sloan Foundation Research Fellow Best Paper Awards at ASPLOS 2009 and ISPASS 2011 Laboratory Affiliations : Computer Architecture and Technology Laboratory (CART) TRIPS Project (Tera-Op Reliable Intelligently adaptive Processing System) NVIDIA Research
Dr. Ameer Abdelhadi is an Assistant Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on application-specific custom-tailored computer architectures, hardware-efficient deep learning, neurotechnology, and reconfigurable computing. He holds a PhD from the University of British Columbia and has held academic positions at the University of Toronto, Imperial College London, and Simon Fraser University, alongside industry experience in semiconductor design. Education: PhD in Computer Engineering (University of British Columbia, 2016). Research Interests: Hardware acceleration for machine learning and neurotechnology Reconfigurable computing and FPGAs/ASICs Asynchronous circuits and synchronization protocols VLSI physical design and CAD algorithms Publications span high-impact venues such as IEEE Journal of Solid-State Circuits, IEEE Hot Chips, and IEEE Micro. Notable achievements include the 2017 Best Paper Award at ASYNC for work on synchronization FIFOs. Teaching includes COMPENG 4DV4 (VLSI System Design) and ELECENG 4OI6B (Engineering Design). His lab focuses on advancing hardware systems for next-generation applications in AI and biomedical engineering.
Arrvindh Shriraman is an Associate Professor and Program Director of Software Systems at Simon Fraser University's School of Computing Science in Surrey. His research focuses on energy-efficient software, multicore memory systems, and optimizing hardware/software interfaces for parallel programming. He holds a Ph.D. (2010) and M.S. (2006) in Computer Science from the University of Rochester, and a B.Eng. (2004) from the University of Madras. He teaches courses on parallel programming and energy-conscious software design. His research interests include synchronization mechanisms for domain-specific architectures, cache optimization, and FPGA-based acceleration. He has contributed to frameworks like Mu-grind for HLS-generated RTL instrumentation and TAPAS for parallel accelerator generation. Notable projects include RANGE-BLOCKS for synchronization in domain-specific systems and TapeFlow for gradient computation in neural networks. His work emphasizes real-time verification of autonomous systems and safety-critical trajectory planning for underwater vehicles. Shriraman collaborates closely with the Tangent Lab, exploring cutting-edge solutions in hardware-software co-design and embedded systems. His teaching and research bridge theoretical computer science with applied engineering challenges, addressing scalability, efficiency, and safety in modern computing systems.
Muhammad Ali Gulzar is an Assistant Professor in the Computer Science Department at Virginia Tech and an Amazon Scholar at Amazon Web Services. His research focuses on improving developer productivity through automated debugging and testing for applications in emerging domains, including data-intensive software such as dataflow programs, ML/AI applications, and computational notebooks. Education Ph.D. in Computer Science from University of California, Los Angeles (Google Ph.D. Fellow 2017-2020) Research Interests Gulzar's research spans three primary areas: (1) automated tracking-code localization techniques in web applications, (2) re-engineering testing and debugging for data-intensive applications, and (3) advancing current testing and debugging practices in Federated Learning Applications. His work addresses the challenges of debugging in complex systems where traditional approaches fail due to the scale and distributed nature of modern applications. His research has significant implications for improving software quality, developer productivity, and accessibility in web applications. Research Trends Recent publications demonstrate a strong focus on debugging and testing challenges in emerging application domains. His work bridges traditional software engineering with machine learning, data-intensive systems, and web technologies. Notably, he has made significant contributions to Federated Learning debugging (FedDebug), accessibility challenges in ad-driven web applications, and semantic caching for Large Language Models. His approach often combines novel algorithmic insights with practical implementations that address real-world challenges in software development and maintenance. Scientific Awards Google Ph.D. Fellow (2017-2020) $1.1 million NSF award for Federated Learning research ACM CCS 2024 Distinguished Artifact Award Advising and Grants Gulzar leads a productive research group with multiple students contributing to publications in top-tier venues. His NSF-funded research on Federated Learning demonstrates his ability to secure competitive funding for innovative projects. His advising style appears to emphasize practical impact alongside theoretical contributions, with students often taking lead roles in publications. Current research directions include debugging techniques for Large Language Models, accessibility challenges in modern web applications, and novel testing approaches for distributed data processing systems.
Bryan Parno is a Professor at Carnegie Mellon University in the Departments of Electrical & Computer Engineering and Computer Science . He is the recipient of the Kavčić-Moura Chair and leads the Secure Foundations Lab , focusing on end-to-end secure systems through formal verification. Research spans secure systems , applied cryptography , distributed systems , and zero-knowledge proofs Developed Verus (verified Rust systems) and Project Everest (verified HTTPS stack) Key contributions include Ironclad , Flicker , and Pinocchio , with impacts on Intel CPUs and Windows/iOS security models His work emphasizes open-source tools and reproducibility , often published in top venues like POPL, PLDI, and IEEE S&P. Recent projects address WebAssembly security and formal verification of complex distributed systems . Major Awards Jay Lepreau Best Paper Award (OSDI 2025) IEEE Cybersecurity Award for Practice (2024) Sloan Research Fellowship (2018) Test-of-Time Awards (IEEE S&P 2023, IEEE S&P 2020) Best Paper Awards at USENIX Security, OOPSLA, and PLDI
