Prof. Dr. rer. nat. Rainer Leupers is a faculty member at RWTH Aachen University, chairing the Department of Software for Systems on Silicon. His research focuses on embedded systems, hardware-software co-design, virtual prototyping, and security in computing-in-memory architectures. He has published extensively on RRAM accelerators, logic locking, and neuromorphic security. Chair of Software for Systems on Silicon Research in hardware security and deep learning accelerators Recent publications on cross-tool virtual frameworks and thermal side-channel attacks His work bridges system-level modeling with practical security implementations, emphasizing reliability and performance in heterogeneous computing environments. Key trends in his 2025-2023 articles include compute-in-memory optimization, neural network inference efficiency, and security vulnerabilities in emerging hardware. Awards and formal recognitions are not explicitly detailed in the provided materials. He has not directly mentioned advising students or research grants in the given text fragments. The chair's contact information includes an office at ICT Cube 1, Electrical Engineering, Aachen, with direct email and website links.
Vivienne Sze is a Professor at MIT's Department of Electrical Engineering and Computer Science (EECS), part of the School of Engineering. Her research focuses on energy-efficient computing systems for machine learning, computer vision, and video compression, with applications in autonomous systems, healthcare, and IoT. She leads projects integrating algorithmic innovations with hardware design to achieve low-power solutions for embedded and mobile devices. Her work has been recognized through prestigious awards, including the Primetime Engineering Emmy Award for co-developing the HEVC video compression standard and multiple faculty awards from tech giants like Google and Qualcomm. She co-authored the book *Efficient Processing of Deep Neural Networks*, emphasizing practical hardware-software co-design strategies. Research Interests: Energy-Efficient Machine Learning Accelerators Video Coding and Compression Standards Embedded Systems and Mobile Computing Processing-in-Memory (PIM) Architectures AI for Health Monitoring and Digital Health Sustainability in AI Infrastructure Publications highlight trends in: Optimizing DNNs for edge devices Innovations in entropy coding and CABAC Memory-efficient Gaussian-based algorithms Energy-aware design for photonic computing Awards include IEEE conference best paper awards and industry recognitions for her contributions to video coding and hardware acceleration. Her lab's collaborative efforts span academia and industry, aiming to bridge theoretical research with real-world deployable systems.
Sergi Abadal Cavalle is a distinguished Professor in the Department of Computer Architecture at the Universitat Politècnica de Catalunya (UPC), affiliated with the Escola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona (ETSETB). He leads a dynamic research group focused on revolutionary computing architectures through wireless chip-scale networks and quantum interconnects. His work is supported by prestigious grants including an ERC Starting Grant and an ERC Proof of Concept Grant. Education: PhD in Computer Architecture, Universitat Politècnica de Catalunya (2016) MSc in Telecommunication Engineering, UPC (2011) BSc in Telecommunication Engineering, UPC (2010) Sergi's research focuses on overcoming the limitations of traditional wired interconnects in computing systems by pioneering wireless communication at the chip and package level. His work spans terahertz communications, graphene-based antennas, reconfigurable metasurfaces, and quantum-coherent networks. He has led major EU projects such as WINC, EWiC, QUADRATURE, and WiPLASH, aiming to revolutionize classical and quantum computing architectures. His research integrates electromagnetics, materials science, and computer architecture to enable ultra-fast, scalable, and energy-efficient systems. His recent publications demonstrate a strong trend toward integrating wireless technologies within computing systems, particularly using novel materials like graphene and software-defined metasurfaces. The articles highlight advancements in on-chip wireless communication, channel modeling, and the application of these technologies in 6G and quantum computing. His work bridges theoretical modeling with experimental validation and practical emulation. Scientific Awards: ERC Starting Grant (2022) ERC Proof of Concept Grant (2024) ACM NanoCom Outstanding Milestone Award (2022) NanoComNet Young Investigator Award (2019) UPC Outstanding Thesis Award (2016) IN-NOVA Award to Best Master Thesis (2021) IBM Award to Best Academic Record (2021) Medal from Real Academia de la Ingeniería (2024) IEEE Senior Member (2025) Sergi actively mentors a large group of PhD and Master's students, many of whom have received awards for their thesis work. He leads the N3Cat research group and collaborates with institutions such as IBM Research, NEC Labs Europe, RWTH Aachen, EPFL, University of Nottingham, and Intel Labs. His lab is at the forefront of experimental validation of wireless interconnects and quantum architectures, with ongoing projects focusing on emulation and commercialization of chiplet communication technologies.
Twan Basten is a Full Professor in the Electronic Systems group at Eindhoven University of Technology (TU/e). He leads research on embedded and cyber-physical systems, focusing on model-driven design, computational models, and system dependability. He holds an MSc (1993) and PhD (1998) in Computing Science from TU/e, advancing from Assistant to Full Professor by 2009, and became the Electronic Systems group chair in 2013. His research spans international projects (FP5-7, H2020, ECSEL) and Dutch initiatives (STW, NWO, RVO), with over 200 publications and seven best paper awards. He has co-supervised 21 PhD students and actively participates in program committees and conferences. His work contributes to UN Sustainable Development Goals through innovations in smart systems. Education: MSc in Computing Science, TU/e (1993) PhD in Computing Science, TU/e (1998) Research Interests: Explores design methodologies for embedded systems, including scenario-based design, real-time scheduling, and performance analysis. Specializes in model-driven engineering and computational models to ensure system dependability. Active in projects like TRANSACT (real-time systems) and SAM-FMS (flexible manufacturing). Key Contributions: Co-author of 1 book and over 200 scientific publications Recipient of seven best paper awards Co-supervised 21 PhD degrees Senior member of IEEE and lifetime member of ACM Labs & Teams: Leads the Model-Based Design Lab and contributes to EAISI High Tech Systems initiatives. Collaborates on tools like TRACE4CPS for execution trace analysis and CReTS for vehicle platooning simulation.
Yue Li is an Associate Professor at the School of Computer Science, Nanjing University, where they co-run the PASCAL Research Group with Tian Tan. Their work focuses on static program analysis techniques and tools for programming languages, software engineering, security, and hardware verification. PhD in Computer Science from UNSW Sydney (2016) Postdoctoral research at Aarhus University (Denmark) and UNSW Sydney B.Eng and M.Eng from Northwestern Polytechnical University (2010, 2012) Research interests center on Program Analysis and Programming Languages , with a focus on: Pointer analysis for database-backed applications Context sensitivity optimization Reflection analysis in Java/Android Operational semantics for hardware languages Distributed dataflow analysis frameworks Developer-friendly static analysis tools Key publication trends (2016-2025) span static analysis , pointer precision , reflection handling , and tool frameworks across conferences like OOPSLA, PLDI, ICSE, ISSTA, and journals including TOPLAS and IEEE TSE. Notable artifacts include Tai-e and Chianina systems. 2025: ICSE Best Artifact & Distinguished Paper Awards 2024: IEEE TSE Publication on Generic Sensitivity 2023: OOPSLA Distinguished Artifact, SPLASH/ECOOP committees 2021: National Youth Talent Support Program, ZiJin Scholar 2016: ECOOP Distinguished Paper, CGO Best Paper As co-PI of PASCAL Research Group, they lead projects on precision-guided analysis, microservice systems, and cloud-based dataflow frameworks, with teaching awards for SICP and Software Analysis courses.
Maurizio Zamboni is a Full Professor at the Department of Electronics and Telecommunications (DET) at the Polytechnic University of Turin, where he also serves as Student Ombudsman. His academic career spans over three decades with continuous teaching and research contributions in electronics and computing fields. Professor Zamboni's research interests focus on cutting-edge areas including CMOS integrated circuits, computer architecture, quantum computing, semiconductor devices, and VLSI design. His work particularly emphasizes emerging nanotechnologies for digital microelectronic architectures and the design of high-performance or low-consumption processing systems. He has developed expertise in circuit architectures for probabilistic computing, logic-in-memory computing, magnetic devices, and quantum architectures. His recent publications (2021-2025) reveal a strong trend toward quantum computing applications, in-memory processing architectures, and novel approaches to overcoming the memory wall problem. These works span both theoretical algorithm development and practical hardware implementations, with significant focus on quantum annealing, FPGA-based quantum emulation, and memory-mapped processing architectures. Professor Zamboni has been actively supervising PhD students working on quantum computing algorithms, hardware AI accelerators for automotive applications, and quantum-related optimization approaches. He leads research within the VLSILAB Group at DET, focusing on the intersection of nanoelectronics, quantum computing, and advanced computer architectures. His work bridges theoretical computer science with practical electronic design, creating novel solutions for next-generation computing challenges.
Nectarios Koziris is a Professor at the Department of Computer Science , National Technical University of Athens (NTUA) , and former Dean of the School of Electrical and Computer Engineering . His research focuses on Parallel and Distributed Systems , Computer Architecture , and Cloud Computing . Key Research Themes: Compiler-OS-Architecture Interaction, Datacenter Hyperconvergence, Sparse Matrix Optimization, Quantum Computing, FPGA Virtualization Leadership: Founder of ~okeanos (Europe's largest public Cloud IaaS), Co-founder of GFOSS , Member of IEEE Computer Society Greece, Advisor to Arrikto Inc. His work has led to over 180 publications with 5800+ citations (h-index 33) , including two Best Paper Awards (IPDPS 2001, CCGRID 2013) and Intel Recognition (2015). He has supervised 12 PhD students and participated in 15+ EU projects as coordinator or consortium partner. Scientific Leadership: Program Co-Chair for Europar 2012 , Organizer for IPDPS , ICPP , SC conferences, and active member in Cloud Computing Expert Groups for the European Commission.
Xuan Zhang serves as Associate Professor in Electrical and Computer Engineering at Northeastern University, leading the Sensory AI Lab since joining in January 2024. Her research bridges computer architecture, integrated circuits, and artificial intelligence to develop miniaturized AI systems for autonomous physical platforms. She earned her PhD in Electrical and Computer Engineering from Cornell University in 2012. Her educational background forms the foundation for her interdisciplinary work spanning hardware and software co-design. Dr. Zhang's research focuses on artificial intelligence hardware, machine vision sensors, and security for autonomous systems. She pioneers techniques for efficient in-sensor computing, analog circuit optimization via machine learning, and hardware-level privacy preservation. Her work addresses critical challenges in energy efficiency, robustness, and security for edge AI deployment, particularly in resource-constrained environments like medical devices and autonomous vehicles. Analysis of her 2023-2025 publications reveals three dominant trends: (1) hardware-accelerated privacy mechanisms for sensors, (2) machine learning-driven analog circuit design automation, and (3) energy-efficient architectures for neural network inference. These works consistently target real-world applications in healthcare, autonomous systems, and semiconductor design. Her accolades include the prestigious NSF CAREER Award (2020) and leadership in a $10 million federal semiconductor initiative. She contributes to national efforts in AI-powered chip design through the National Center for the Advancement of Semiconductor Technology. Dr. Zhang advises graduate researchers in the Sensory AI Lab, securing significant funding for projects spanning hardware security, in-sensor computing, and autonomous system assurance. Her lab collaborates with federal agencies and industry partners on cutting-edge semiconductor research. The Sensory AI Lab operates at the hardware-software interface, developing novel architectures for intelligent edge devices. Current projects include optical privacy preservation, robust analog design tools, and energy modeling frameworks for in-sensor visual computing systems.
Marco Vacca is an Associate Professor in the Department of Electronics and Telecommunications (DET) at Politecnico di Torino and a member of the Interdepartmental Center PIC4SeR - PoliTO Interdepartmental Centre for Service Robotics. His work bridges electronics, nanotechnology, and computing architecture with a focus on innovative solutions to the memory wall problem. His research spans Logic-in-memory computing, Machine learning hardware acceleration, and Nanocomputing with specific emphasis on circuit architectures for probabilistic computing, magnetic devices, hybrid technologies integration, and CAD tools for emerging technologies. Dr. Vacca leads research in RISC-V extensions, hardware accelerators for AI, and autonomous robot systems for agricultural applications through the VLSILAB research group. Recent publications reveal a strong trend toward solving fundamental computing challenges through nanoscale innovations, particularly in memory-centric architectures, molecular field-coupled computing, and novel transistor technologies. His work demonstrates how logic-in-memory approaches can overcome traditional von Neumann limitations while improving energy efficiency for AI workloads. Editorial board member of ELECTRONICS (2021-2023) Program committee member for Design, Automation and Test in Europe Conference (DATE) 2020-2021 Dr. Vacca supervises PhD student Alessandro Varaldi working on 'Hardware AI Accelerators for Automotive Applications' and has led significant research projects including 'Device for Storage and Processing Data and Related Method' (2020-2021) and 'Quantum Computing and Quantum Communication: State of the Art and Applications in the Telco Sector' (2020). His grant portfolio shows strong industry and competitive funding support. As a core member of the VLSILAB research group, Dr. Vacca contributes to advancing VLSI theory and design applications with particular focus on implementing Big Data, Machine Learning, and Neural Networks in specialized hardware architectures that push the boundaries of conventional computing.
Sandrine Blazy is a Professor in the Computer Science Department at the University of Rennes, France. She is a member of CELTIQUE (also referred to as Epicure), a joint project-team with Inria Rennes Bretagne Atlantique and the IRISA laboratory. Since 2021, she has served as deputy director of the IRISA CNRS UMR 6074 laboratory and will be the general chair for POPL 2026, which will be held in Rennes. She is also a member of the editorial board of the LMCS journal. Dr. Blazy completed her PhD at CNAM (Conservatoire National des Arts et Métiers) in 1993 with a thesis titled "La spécialisation de programmes pour l'aide à la maintenance du logiciel" (Program Specialization for Software Maintenance Assistance). She later completed her Habilitation à diriger des recherches (HDR) in 2008 at the University of Évry Val d'Essonne with a thesis titled "Sémantiques formelles" (Formal Semantics). Her research focuses on the formal verification of program transformations and semantic properties of programming languages, particularly in the context of the CompCert compiler and Verasco static analyzer. She develops mechanized semantics using the Coq (or Rocq) proof assistant to ensure software correctness and security. A prime application domain of her work is software security, including constant-time programming for cryptographic applications and software obfuscation techniques. Her teaching includes mechanized semantics (in Coq), functional programming (in OCaml), formal methods (using Why3), and software vulnerabilities. Dr. Blazy's publication record from 2019-2025 shows a sustained focus on verified compilation techniques, particularly in preserving security properties during compilation. Her work bridges theoretical formal methods with practical compiler implementation, resulting in tools that have real-world impact in safety-critical systems. She has made significant contributions to the CompCert formally verified compiler project, with particular attention to constant-time preservation for cryptographic applications and JIT compilation verification. Her scientific achievements have been recognized with several major awards: CNRS Silver Medal (2023) Lucas Award from Formal Methods Europe (2023) ACM SIGPLAN Programming Languages Software Award for CompCert (2022) ACM Software System Award for CompCert (2021) Dr. Blazy has been actively involved in the programming languages research community, serving on numerous program committees for major conferences including POPL, ICFP, PLDI, and CPP. She has mentored students and contributed to education through teaching mechanized semantics and formal methods. Her work with the CompCert compiler has led to practical applications in safety-critical systems, with industry collaborations documented in publications like "CompCert: Practical experience on integrating and qualifying a formally verified optimizing compiler" (ERTS 2018). She leads research within the CELTIQUE project team, which focuses on developing trustworthy software using deductive verification. Her team works on advancing the state of the art in formal verification of compilers and static analyzers, with applications in security-critical domains including cryptographic implementations and safety-critical embedded systems.
Shuvra S. Bhattacharyya is a Professor at the University of Maryland, College Park (UMD), Department of Electrical and Computer Engineering, with a joint appointment in UMIACS. He is also a part-time visiting professor at Tampere University (Finland) and INSA Rennes (France). His research focuses on signal processing systems, embedded systems, biomedical engineering, and machine learning. He has authored 7 books and over 300 papers, and directs the Maryland DSPCAD Research Group. He holds an NSF Career Award and is an IEEE Fellow. His honors include the Fulbright Senior Specialist and FiDiPro Professorship. He advises graduate students and leads projects in neural decoding, cyber-physical systems, and criminal justice AI. Education: B.S., University of Wisconsin-Madison Ph.D., University of California, Berkeley Research Interests: Signal processing architectures, biomedical circuits, embedded software, hardware/software co-design, and AI for healthcare and criminal justice. His work emphasizes real-time systems, energy efficiency, and interdisciplinary applications. Grants & Awards: NIH Grant for real-time neural decoding (2023) IEEE Fellow (2011) Jimmy Lin Entrepreneurship Award (2012) Labs & Teams: Maryland DSPCAD Research Group, collaborating on dynamic data-driven systems, neural interface technologies, and AI ethics in criminal justice. His work integrates academic and industrial partnerships, including roles at Hitachi America and Kuck & Associates.
Stephen A. Edwards is an Associate Professor at the Computer Science Department of Columbia University , where he explores automating software for embedded systems and real-time control . His work focuses on compiler techniques for languages like Esterel and domain-specific solutions for device drivers and communication protocols . Education : PhD in Electrical Engineering, University of California, Berkeley (1997) MS in Electrical Engineering, UC Berkeley (1994) BS in Electrical Engineering, California Institute of Technology (1992) Research Interests span hardware synthesis , functional programming , and synchronous languages . He develops domain-specific languages to bridge software and hardware, emphasizing determinism and timing precision in embedded systems. His group's work includes projects like the FHW compiler and the Sparse Synchronous Model . Article Trends show a focus on FPGA-based systems , garbage collection for accelerators, and parallel functional programming . These reflect his broader interests in hardware-software co-design and compiler optimization for real-time applications. Students : John Hui (2021-2024, Apple) Max Levatich (2020-) Richard Townsend (2013-2019, Tufts) Nalini Vasudevan (2007-2011, Google) Marcio Buss (2004-2008) Jia Zeng (2002-2008) Cristian Soviani (2002-2007, Synopsys) Consulting & Expert Services : He provides litigation support and expert witness services in patent cases involving software architecture and computer design , including ITC cases. Labs & Projects : Leads research on sparse synchronous systems and hardware synthesis , with initiatives like the GAPS CLOSURE Project and FHW Compiler for translating Haskell to System Verilog.
Nikolaos Papaspyrou is a Professor at the School of Electrical and Computer Engineering of the National Technical University of Athens (NTUA) and a member of the Software Engineering Laboratory . His research focuses on the theory and implementation of programming languages, including semantics, type systems, compilers, static analysis, and formal verification. Since October 2021, he has been on leave from NTUA, working as a Software Engineer for Google in the memory management team for the V8 JavaScript and WebAssembly engine. He previously served as Director of the Division of Computer Science (2017-2019) and was on sabbatical with Google's compiler group in Munich (2015-2016). His work includes the RELEASE project (EU FP7 STREP) for reliable large-scale server software and uncertainty handling in distributed databases (European Social Fund). Ph.D. and Diploma in Electrical and Computer Engineering from NTUA M.Sc. in Computer Science from Cornell University His research interests span programming languages , software engineering , and formal verification , with recent publications on coinductive proofs in Liquid Haskell, concurrency semantics, and quantum compilation. He has supervised over 50 diploma projects and mentored numerous students now at institutions like MIT, Princeton, and UC Berkeley. Awards include conference organizing and program committee roles, though no formal scientific prizes are listed.
Dr. Andrea Guerrieri is an Associate Professor at the University of Applied Sciences and Arts Valais-Wallis - School of Engineering , specializing in Reconfigurable Computing, Electronics Design Automation (EDA), and Post-Quantum Cryptography . His work focuses on accelerating FPGA compilation through tools like DynaRapid and optimizing security protocols via Dynamatic , with technologies adopted by industry leaders including Intel, AMD-Xilinx, and CERN . He holds a BSc in Industrial Systems and a MSc in Engineering from HES-SO, and teaches courses in Digital Design and Embedded Hardware. BSc HES-SO in Industrial Systems (2019) BSc HES-SO in Computer and Communication Systems (2017) MSc HES-SO in Engineering (2021) Guerrieri’s research bridges High-Level Synthesis (HLS) and Reconfigurable Architectures to enhance FPGA performance for both terrestrial and space applications . His 2025 publications highlight advancements in heterogeneous computing , energy-efficient PQC , and rapid compilation frameworks . Notably, his 2024 work on DynaRapid achieved 20× speedup in C-to-FPGA implementation. Key scientific contributions span dataflow circuit optimization , dynamic scheduling , and automated code transformations . His 2023 book Applications Enabled by FPGA-Based Technology and 2021 textbook System-on-Chip Design with Arm established foundational references in embedded systems. Awards include Best Paper at FPL 2024 , Outstanding TPC Member at DAC 2024 , and IEEE Senior Membership (2021) . 2024: Best Paper Award (FPL), Outstanding Short Paper Award (HPEC) 2023: H-Saber publication on PQC optimization 2021: IEEE Senior Member recognition As Chair of Onboard Computing for the CHEESE-NASA SSERVI consortium, he leads international collaborations with ETH Zurich, University of Geneva, California State University , and companies like NVIDIA, Arm, and NASA . His projects include the Innosuisse-funded DyReCte initiative (2019–2021) for reconfigurable cryptoengines in nanosatellites.
Andrea Guerrieri serves as an Associate Professor at the School of Engineering, University of Applied Sciences and Arts Western Switzerland Valais (HES-SO Valais-Wallis), specializing in reconfigurable computing and electronics design automation. His research has established significant industry impact through tools like DynaRapid and Dynamatic, with technology adopted by major semiconductor companies including MIPS, Intel, and AMD-Xilinx. BSc HES-SO in Industrial Systems - System-on-Chip specialization BSC HES-SO in Computer and Communication Systems - Digital Design specialization MSc HES-SO in Engineering - Embedded Hardware and Firmware specialization Professor Guerrieri's research focuses on reconfigurable computing, electronics design automation (EDA), and security, with particular emphasis on FPGA design, high-level synthesis, and post-quantum cryptography implementations. His work bridges the gap between theoretical computer architecture and practical hardware implementations, with strong applications in space technology and embedded security systems. His recent publications demonstrate increasing focus on energy-efficient implementations for space applications and quantum-resistant cryptographic systems. Analysis of his 15 most recent publications reveals a clear research trajectory toward optimizing FPGA implementations for post-quantum cryptography and space applications. His work consistently addresses the performance bottlenecks in high-level synthesis while maintaining practical applicability for industry partners like NASA, CERN, and major semiconductor companies. The recent surge in best paper awards (three in 2024 alone) reflects growing recognition of his contributions to efficient FPGA compilation techniques and cryptographic implementations. Scientific Awards: Best Paper Award at FPL 2024 Best Paper Award at HPEC 2024 Best Paper Award at ISFPGA 2020 Outstanding Short Paper Award at IEEE HPEC 2024 Outstanding TPC Member Award at DAC 2024 IEEE Senior Member (2021) Multiple Best Paper nominations (FCCM 2022, FPL 2022, HiPEAC 2022) Professor Guerrieri actively participates in international research projects including the DyReCte project (2019-2021) on dynamically reconfigurable cryptoengines for nano-satellites. He currently chairs the Onboard Computing topic for the Swiss consortium CHEESE affiliated with NASA SSERVI and collaborates extensively with industry partners including AMD-Xilinx, NVIDIA, Arm, NASA, and CERN, as well as academic institutions like ETH Zurich and University of Geneva. His current research focuses on developing next-generation EDA tools and reconfigurable computing platforms for both terrestrial and space applications. His laboratory work centers around FPGA-based prototyping and validation, with specialized facilities for space applications testing. Professor Guerrieri leads a research team that includes Andres Upegui, Quentin Berthet, Laurent Gantel, and Gabriel Da Silva Marques, focusing on practical implementations of reconfigurable architectures for security and space applications.
